CN208257788U - A kind of high frequency resolution pulse digit generating system - Google Patents
A kind of high frequency resolution pulse digit generating system Download PDFInfo
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- CN208257788U CN208257788U CN201821173605.0U CN201821173605U CN208257788U CN 208257788 U CN208257788 U CN 208257788U CN 201821173605 U CN201821173605 U CN 201821173605U CN 208257788 U CN208257788 U CN 208257788U
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Abstract
The utility model relates to a kind of high frequency resolution pulse digit generating systems, including sequentially connected data processing and control circuit, frequency dividing and delay circuit, timing and frequency dividing circuit and pulse shaper, data processing and control circuit are connected with data input pin, and pulse shaper is connected with signal output end；Phaselocked loop is also parallel between data processing and control circuit, timing and frequency dividing circuit；Phaselocked loop includes sequentially connected phase discriminator, loop filter and voltage controlled oscillator, and the phase discriminator input terminal is connected with the reference frequency source of fixed frequency by frequency divider R, and the output end of the voltage controlled oscillator is connect by frequency divider N with phase discriminator；The data processing and control circuit are connect with phase discriminator, and the voltage controlled oscillator is connect with timing and frequency dividing circuit.The utility model changes fMclk by adjusting the output frequency of phaselocked loop, and output frequency and target frequency difference are narrowed down within 1 hertz, can obtain higher frequency accuracy and control precision.
Description
Technical field
The utility model relates to signal processing systems, belong to signal processing technology field, more particularly to a kind of
High frequency resolution pulse digit generating system.
Background technique
Pulse signal carries out fine mark in signal testing, and driving laser, and there is great application in the fields such as engraving,
Especially in testing field, pulse signal has very high demand for frequency accuracy.The common method for generating pulse mainly has
Make the analogy method into avalanche breakdown critical state using avalanche transistor, also has and carried out using the high-speed figures device such as FPGA
The digital scheme of digital frequency division.
For simulating class pulse generation scheme, pulsed drive frequency is generally obtained by RC oscillating circuit, and to change time frequency
Rate just needs to change the R i.e. resistance parameter in oscillating circuit, and usually atomic small R parameter change also brings along great vibration
Frequency variation is swung, the pulse signal of high frequency resolution can not be obtained in practical operation by adjusting R parameter.
For numeric class scheme, pulse frequency is divided to obtain by system master clock, i.e. f=fMclk/N, and wherein f is to generate
Pulse frequency, fMclk be digital display circuit master clock, N is the frequency division coefficient carried out to the master clock.In order to obtain 1 hertz
Frequency resolution, it is necessary to so that N be more than or equal to fMclk square root, fMclk be 100M when, square root 10000,
By f=fMclk/N it is found that reach 1 hertz frequency resolution ratio, output can only be in 10kHz or less.If being existed with this kind of scheme
When 1MHz is exported, remains to obtain 1 hertz of resolution ratio, system master clock fMclk is needed to reach 1M*1M, the i.e. frequency of 1000GHz,
Clearly for high number digital device of today, which is unpractical.
Therefore, it for the scheme of simulation class, is influenced by analog device parameter regulation accuracy, scheme itself can not be accurate
Learn and control the frequency of pulse generation；For numeric class scheme, since pulse frequency carries out digital frequency division by system master clock
It obtains, can accurately learn current form frequency, but can not accomplish 1 hertz or even higher control essence when generation frequency is higher
Degree.
Utility model content
Based on the above technical problem, the utility model provides a kind of high frequency resolution pulse digit generating system, from
And the signal output of different height frequencies, output signal frequency can not be suitable for simultaneously by solving previous pulse digit generating system
Accuracy and precision difference technical problem.
In order to solve the above technical problems, the technical solution adopted in the utility model is as follows:
A kind of high frequency resolution pulse digit generating system, including sequentially connected data processing and control circuit, point
Frequency and delay circuit, timing and frequency dividing circuit and pulse shaper, data processing and control circuit are connected with data input pin,
Pulse shaper is connected with signal output end；
Wherein,
Phaselocked loop is also parallel between data processing and control circuit, timing and frequency dividing circuit；
Phaselocked loop includes sequentially connected phase discriminator, loop filter and voltage controlled oscillator, and the phase discriminator input terminal is logical
The reference frequency source that frequency divider R is connected with fixed frequency is crossed, the output end of the voltage controlled oscillator passes through frequency divider N and phase discriminator
Connection；
The data processing and control circuit are connect with phase discriminator, and the voltage controlled oscillator and timing and frequency dividing circuit connect
It connects.
Based on system above, the output signal of the phaselocked loop is the master clock fMclk of system, and master clock fMclk passes through
Adjustment frequency divider R and frequency divider N is adjusted, the pulse frequency of the pll output signal by system master clock fMclk by
Following formula divides to obtain:
(f+fdiff)=(fMclk+N*fdiff)/N；
Wherein,
F is the pulse frequency of output signal before phaselocked loop adjusts；
Fdiff is output frequency knots modification；
It (f+fdiff) is actual output frequency after adjustment；
FMclk is the master clock of system；
N is the frequency division coefficient carried out to the master clock；
N*fdiff is the adjustment amount for needing to make fMclk.
In conclusion by adopting the above-described technical solution, the beneficial effects of the utility model are: the utility model is with width
Output signal with phaselocked loop adjusts fMclk as system master clock fMclk in real time, by the output frequency for adjusting phaselocked loop
Rate changes fMclk, is compensated with this to difference fdiff, enable output frequency and target frequency difference narrow down to 1 hertz with
Interior, under identical master clock frequency, compared to conventional digital frequency division scheme, either high-frequency output or low frequency is exported,
Higher frequency accuracy and control precision can be accessed；And it can be directly by adjusting frequency divider N and frequency divider R number tune
Master clock fMclk is saved, and the frequency that adjustment obtains can directly be learnt, be measured again without externally measured instrument, whole system is defeated
Frequency out is more accurate, and control precision is also higher.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model；
Fig. 2 is the structural schematic diagram of the utility model phaselocked loop.
Specific embodiment
The utility model will be further described below with reference to the accompanying drawings.The embodiments of the present invention includes but unlimited
In the following example.
Embodiment
As Figure 1-Figure 2, a kind of high frequency resolution pulse digit generating system, including sequentially connected data processing
And control circuit, frequency dividing and delay circuit, timing and frequency dividing circuit and pulse shaper, data processing and control circuit connect
There is data input pin, pulse shaper is connected with signal output end；
Wherein,
Phaselocked loop is also parallel between data processing and control circuit, timing and frequency dividing circuit；
Phaselocked loop includes sequentially connected phase discriminator, loop filter and voltage controlled oscillator, and the phase discriminator input terminal is logical
The reference frequency source that frequency divider R is connected with fixed frequency is crossed, the output end of the voltage controlled oscillator passes through frequency divider N and phase discriminator
Connection；
The data processing and control circuit are connect with phase discriminator, and the voltage controlled oscillator and timing and frequency dividing circuit connect
It connects.
Based on system above, the output signal of the phaselocked loop is the master clock fMclk of system, and master clock fMclk passes through
Adjustment frequency divider R and frequency divider N is adjusted, the pulse frequency of the pll output signal by system master clock fMclk by
Following formula divides to obtain:
(f+fdiff)=(fMclk+N*fdiff)/N；
Wherein,
F is the pulse frequency of output signal before phaselocked loop adjusts；
Fdiff is output frequency knots modification；
It (f+fdiff) is actual output frequency after adjustment；
FMclk is the master clock of system；
N is the frequency division coefficient carried out to the master clock；
N*fdiff is the adjustment amount for needing to make fMclk.
The utility model adjusts fMclk using the output signal of broadband phase-looked loop as system master clock fMclk in real time,
Output frequency by adjusting phaselocked loop changes fMclk, is compensated with this to difference fdiff, so that output frequency and target
Difference on the frequency can reduce, under identical master clock frequency, compared to conventional digital frequency division scheme, either high-frequency output or low
Rate-adaptive pacemaker can access higher frequency accuracy and control precision；And it can be directly by adjusting frequency divider N and frequency dividing
The digital regulated master clock fMclk of device R, and the frequency that adjustment obtains can directly be learnt, be measured again without externally measured instrument, it is whole
The frequency of a system output is more accurate, and control precision is also higher.
The generation of the present embodiment impulse waveform is still based on timing and frequency dividing circuit, but the master clock of circuit work is by locking phase
Ring provides, and the actual frequency values and target frequency value when high-frequency is exported ask difference to obtain fdiff, by adjusting the defeated of phaselocked loop
Frequency shift fMclk out compensates difference fdiff with this, and output frequency and target frequency difference is enabled to narrow down to 1 hertz
Within hereby.
As shown in Fig. 2, reference signal inputs phase discriminator, phase discriminator is phase comparison device, is used to comparator input signal ui
(t) and the phase of voltage controlled oscillator output signal uo (t), its output voltage ud (t) correspond to the two signal phase differences
Function；The effect of loop filter is the high fdrequency component and noise filtered out in ud (t), to guarantee performance required by loop；
Voltage controlled oscillator draws close frequency of oscillation to the frequency of input signal by the control of loop filter output voltage uc (t), until
The frequency of the two is identical, so that the phase of the phase of voltage controlled oscillator output signal and input signal keeps certain specific pass
System achievees the purpose that PGC demodulation, just can obtain a frequency in output end in this way and multiply for reference signal frequency divided by frequency divider R
With the frequency fo of frequency divider N, which is used as to the reference clock fMclk of system, just can pass through programmable frequency divider R and frequency divider
N adjusts fMclk in real time.
By taking fMclk is approximately equal to 100M as an example, with general digital frequency division scheme, it is desirable to which 100 need to be carried out by obtaining 1MHz and output
Frequency dividing, but near 100 frequency dividings, such as 99 frequency dividings or 101 frequency dividings are only capable of obtaining output frequency 1010101Hz and 990099Hz,
It is unable to reach the output of 1000001Hz or 999999Hz i.e. 1 hertz resolution ratio, and by formula (f+fdiff)=(fMclk+N*
Fdiff)/N can be apparent from, when needing output frequency to change fdiff Hz, it is only necessary to make N* to the frequency of fMclk
The change of fdiff, in this example, to make output be 1000001Hz, it is only necessary to fMclk is adjusted to 100MHz+100Hz, thus
It, can number adjustment output frequency without manually adjusting.And so on, for output of frequency when lower, output frequency can also have
Higher accuracy exports 10kHz if fMclk is equal to 100M, then frequency division coefficient is 10000, by preceding formula (f+fdiff)
=(fMclk+N*fdiff)/N may make the variation of output frequency 0.01Hz it is found that when fMclk generates the variation of 100Hz,
So that the accuracy of output frequency and control precision are higher.
It is as described above the embodiments of the present invention.Each preferred embodiment described previously for the utility model,
Preferred embodiment in each preferred embodiment if not obvious contradictory or premised on a certain preferred embodiment,
Each preferred embodiment can any stack combinations use, the design parameter in the embodiment and embodiment be only for
The utility model verification process of clear statement inventor, not to limit the scope of patent protection of the utility model, this reality
It is still subject to the claims with novel scope of patent protection, in all specifications and attached drawing with the utility model
The variation of equivalent structure made by holding, similarly should be included in the protection scope of the utility model.
Claims (2)
1. a kind of high frequency resolution pulse digit generating system, it is characterised in that: including sequentially connected data processing and control
Circuit, frequency dividing and delay circuit processed, timing and frequency dividing circuit and pulse shaper, data processing and control circuit are connected with number
According to input terminal, pulse shaper is connected with signal output end；
Wherein,
Phaselocked loop is also parallel between data processing and control circuit, timing and frequency dividing circuit；
Phaselocked loop includes sequentially connected phase discriminator, loop filter and voltage controlled oscillator, and the phase discriminator input terminal is by dividing
Frequency device R is connected with the reference frequency source of fixed frequency, and the output end of the voltage controlled oscillator is connected by frequency divider N and phase discriminator
It connects；
The data processing and control circuit are connect with phase discriminator, and the voltage controlled oscillator is connect with timing and frequency dividing circuit.
2. a kind of high frequency resolution pulse digit generating system according to claim 1, it is characterised in that: the locking phase
The output signal of ring is the master clock fMclk of system, and master clock fMclk is adjusted by adjusting frequency divider R and frequency divider N,
The pulse frequency of the pll output signal is divided as follows by system master clock fMclk and is obtained:
(f+fdiff)=(fMclk+N*fdiff)/N；
Wherein,
F is the pulse frequency of output signal before phaselocked loop adjusts；
Fdiff is output frequency knots modification；
It (f+fdiff) is actual output frequency after adjustment；
FMclk is the master clock of system；
N is the frequency division coefficient carried out to the master clock；
N*fdiff is the adjustment amount for needing to make fMclk.
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| CN201821173605.0U CN208257788U (en) | 2018-07-24 | 2018-07-24 | A kind of high frequency resolution pulse digit generating system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566201A (en) * | 2018-07-24 | 2018-09-21 | 成都意科科技有限责任公司 | A kind of high frequency resolution pulse digit generating system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566201A (en) * | 2018-07-24 | 2018-09-21 | 成都意科科技有限责任公司 | A kind of high frequency resolution pulse digit generating system |
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