CN218897214U

CN218897214U - Phase-locked loop, system, digital chip and radar sensor for quick locking

Info

Publication number: CN218897214U
Application number: CN202222036517.9U
Authority: CN
Inventors: 张耀耀; 周文婷
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2023-04-21
Anticipated expiration: 2032-08-03

Abstract

The application provides a phase-locked loop, a system, a digital chip and a radar sensor for quick locking. The phase-locked loop includes: a charge pump outputting a current in response to the frequency-phase-discrimination detection signal; the low-pass filter is connected with the charge pump and used for carrying out low-pass filtering on the current output by the charge pump so as to output a control signal; the voltage-controlled oscillator is connected with the low-pass filter and outputs a clock signal under the control of the control signal; wherein, in a first operation mode, the charge pump and/or the low-pass filter adjusts the control signal to enable the voltage-controlled oscillator to output a clock signal within a first bandwidth range; in a second operation mode, the charge pump and/or the low-pass filter adjusts the control signal to enable the voltage-controlled oscillator to output a clock signal within a second bandwidth range; the second bandwidth is smaller than the first bandwidth so as to achieve the purpose of locking the phase-locked loop.

Description

Phase-locked loop, system, digital chip and radar sensor for quick locking

Technical Field

The application relates to the technical field of feedback control, in particular to a phase-locked loop, a system, a digital chip and a radar sensor for quick locking.

Background

Many modern systems require the use of a phase locked loop to provide the clock signal, so the start-up and locking speed of the phase locked loop has a significant impact on the start-up time of the system. For example, the lock time of a phase locked loop is greatly affected by the loop bandwidth: if the bandwidth of the phase locked loop itself is narrow, the final lock time increases. Thus, the radar sensor in some modes will result in an extended period of time for the digital circuit to wake up, thus requiring a shortened lock on period of the phase locked loop.

The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

Aiming at the defects in the prior art, the application provides a phase-locked loop, a system, a digital chip and a radar sensor for quick locking, which shorten the locking time of the phase-locked loop and realize the locking process with high precision and high locking speed.

According to a first aspect of the present application, a phase locked loop for fast locking is presented, comprising:

a charge pump outputting a current in response to the frequency-phase-discrimination detection signal;

the low-pass filter is connected with the charge pump and used for carrying out low-pass filtering on the current output by the charge pump so as to output a control signal;

the voltage-controlled oscillator is connected with the low-pass filter and outputs a clock signal under the control of the control signal;

wherein, in a first operation mode, the charge pump and/or the low-pass filter adjusts the control signal to enable the voltage-controlled oscillator to output a clock signal within a first bandwidth range; in a second operation mode, the charge pump and/or the low-pass filter adjusts the control signal to enable the voltage-controlled oscillator to output a clock signal within a second bandwidth range; the second bandwidth is smaller than the first bandwidth so as to achieve the purpose of locking the phase-locked loop.

According to some embodiments, the charge pump comprises a first charge pump and a second charge pump:

in the first working mode, the first charge pump works; in the second operation mode, the first charge pump and the second charge pump operate simultaneously.

According to some embodiments, when the first charge pump and the second charge pump work simultaneously, the two charge pumps output reverse currents under the control of the frequency and phase discrimination detection signals so as to inhibit fluctuation of the control signals.

According to some embodiments, the phase locked loop further comprises a phase frequency detector and a frequency divider, wherein:

the frequency divider is connected with the voltage-controlled oscillator, receives the clock signal and outputs a frequency division clock signal;

the frequency and phase discriminator is connected with the frequency divider, receives the reference clock signal and the frequency division clock signal, and outputs the frequency and phase discrimination detection signal.

According to some embodiments, the low pass filter comprises a first tunable circuit and a first capacitor, wherein:

the first adjustable circuit comprises a second capacitor and a first resistor which are connected in series, and at least one of the second capacitor and the first resistor is controlled by an external instruction;

one end of the first capacitor is connected with the first resistor, and the other end of the first capacitor is grounded.

According to some embodiments, the first adjustable circuit further comprises a signal leakage terminal connected to the charge pump;

in the first working mode, no current is transmitted between the signal leakage end and the charge pump;

in the second operation mode, the signal leakage end outputs current to the charge pump.

According to some embodiments, the first adjustable circuit adjusts parameters of the second capacitor and the first resistor according to an operation mode, so that an equivalent integrating capacitor of the low-pass filter is a first capacitance value when the phase-locked loop is in the first operation mode; the equivalent integrating capacitor is a second capacitance value under the condition that the phase-locked loop is in the second working mode;

wherein the first capacitance value is smaller than the second capacitance value.

According to a second aspect of the present application, a system for fast locking a phase locked loop is presented, comprising a phase locked loop as claimed in any of the first aspects;

the lock monitoring circuit is connected with a charge pump and/or a low-pass filter in the phase-locked loop and acquires a frequency division clock signal and a reference clock signal of the phase-locked loop; the lock monitoring circuit detects a frequency division clock signal and a reference clock signal of the phase-locked loop to output to the phase-locked loop in time sequence: an instruction corresponding to the first working mode and an instruction corresponding to the second working mode; and

the lock monitoring circuit generates a lock signal by detecting the frequency division clock signal and the reference clock signal in the second working mode so that the digital circuit can operate according to the clock signal output by the phase-locked loop.

According to a third aspect of the present application, there is provided a digital chip comprising:

the system for fast locking a phase locked loop of the second aspect;

and the signal processing module is connected with the system for rapidly locking the phase-locked loop and is used for performing signal processing on the received digital signal under the clock signal provided by the system for rapidly locking the phase-locked loop.

According to a fourth aspect of the present application, there is provided a radar sensor comprising:

the signal receiving and transmitting system is used for generating a detection signal wave by utilizing the continuous frequency modulation signal, receiving a corresponding echo signal wave and outputting a baseband digital signal by utilizing the detection signal wave and the echo signal wave; wherein the echo signal wave is formed by reflecting the detection signal wave by an object;

the digital chip of the third aspect is connected to the signal transceiver system, and is configured to perform signal processing on a baseband digital signal to obtain measurement information of the radar sensor on the object.

According to some embodiments, the signal transceiving system and the digital chip are packaged in the same integrated circuit.

The application provides a phase-locked loop, a system, a digital chip and a radar sensor for quick locking, which realize the quick locking function of the phase-locked loop without increasing the complexity of a circuit and other additional cost by switching the working mode of the phase-locked loop.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings described below are only some of the embodiments of the present application and are not intended to limit the present application.

Fig. 1 shows a schematic circuit configuration of a phase locked loop including a low pass filter according to an exemplary embodiment;

fig. 2 shows a schematic circuit diagram of a phase locked loop including a charge pump according to an exemplary embodiment;

fig. 3 shows a schematic circuit diagram of a phase locked loop including a charge pump and a loop filter according to an exemplary embodiment;

fig. 4 shows a schematic diagram of the structure of an exemplary embodiment for a fast lock phase locked loop system.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, materials, apparatus, etc. In these instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments, and that the modules or flows in the drawings are not necessarily required to practice the present application, and therefore, should not be taken to limit the scope of the present application.

In some examples, the locking process of the phase locked loop is: closing the charge pump, setting the control voltage of the voltage-controlled oscillator to be a desired value, adjusting the capacitance in the voltage-controlled oscillator to enable the frequency to reach a target value, opening the charge pump, closing the phase-locked loop, and locking the phase of the output clock through negative feedback of the phase-locked loop.

With this locking method, the locking time of the phase-locked loop is greatly affected by the loop bandwidth, and thus the locking time of the phase-locked loop cannot be shortened well.

To this end, the present application provides a fast locking phase locked loop. Wherein the phase-locked loop comprises: a phase frequency detector PFD, a charge pump CP, a low pass filter LPF, a voltage controlled oscillator VCO, and a frequency Divider. The phase frequency detector PFD receives a reference clock signal REFCLK and a frequency-divided clock signal DIVCLK, and outputs phase frequency detection signals (UP signal and DOWN signal). Wherein the UP signal is generated when the reference clock signal REFCLK transitions; the DOWN signal is generated when the divided clock signal DIVCLK transitions. The charge pump CP receives the frequency-phase-discrimination detection signal and outputs a fluctuating current according to the timing and/or time intervals of the UP signal and the DOWN signal. The low pass filter LPF filters the received current and outputs the filtered electrical signal as a control signal to the voltage controlled oscillator VCO. The voltage controlled oscillator VCO adjusts the frequency of the output clock signal under control of the control signal. The clock signal is divided into two paths, one path is output through the output end of the phase-locked loop, and the other path is transmitted to the frequency Divider. The Divider divides the clock signal by a factor of 1/N to generate a divided clock signal DIVCLK, which is fed back to the phase frequency detector PFD, N being greater than 1.

Wherein the charge pump CP and/or the low pass filter LPF comprise an adjustable circuit controlled by an external instruction. The external command may be generated by a circuit including a combination of registers, flip-flops, or signal generators, according to predetermined signal logic. The external instruction is used to cause the phase locked loop to be in either the first mode of operation or the second mode of operation. Wherein, in the first operation mode, the charge pump CP and/or the low pass filter LPF adjust the control signal to make the VCO output a clock signal within a first bandwidth range; in the second operation mode, the charge pump CP and/or the low pass filter LPF adjust the control signal to cause the voltage controlled oscillator VCO to output a clock signal within a second bandwidth range; the second bandwidth is smaller than the first bandwidth, so that the purpose of locking the phase-locked loop is achieved.

In some examples, the low pass filter LPF includes a first adjustable circuit that is controlled by an external command to switch between a first operating mode and a second operating mode set during loss of lock of the phase-locked loop. The first adjustable circuit can continue the setting of the second working mode after the phase-locked loop is locked. For example, the first tunable circuit may include a circuit including a tunable capacitance and/or a tunable resistance within the filter to tune the capacitance specification of the filter.

Referring to fig. 1, a schematic circuit structure of a phase locked loop including a low pass filter is shown. Wherein, low pass filter LPF includes: a first adjustable circuit and a capacitor C2. The first adjustable circuit comprises a capacitor C and a resistor R which are connected in series, and the capacitor C and the resistor R are controlled by external instructions. The first adjustable circuit further comprises a signal leakage end connected with the charge pump CP, and the first adjustable circuit is subjected to working mode to adjust parameters of the capacitor C and the resistor R: in a first working mode, no current is transmitted between the signal leakage end and the charge pump CP, and the equivalent integral capacitance of the low-pass filter is a first capacitance value; in the second operation mode, the signal leakage end outputs a current equivalent integrating capacitor to the charge pump CP as a second capacitance value. Wherein the first capacitance value is smaller than the second capacitance value. One end of the capacitor C2 is connected with the resistor R, and the other end of the capacitor C is grounded.

In some environments where the impedance matching is not required, either of the capacitor C and the resistor R may be controlled by an external command.

In other examples, the charge pump includes a second adjustable circuit that is controlled by an external command to switch between a first mode of operation and a second mode of operation set during a phase locked loop loss of lock. The second adjustable circuit can continue the setting of the second working mode after the phase-locked loop is locked. In some specific examples, the second adjustable circuit includes, for example, a circuit configured inside the charge pump to adjust current output/bleed. For example, the second adjustable circuit includes a capacitor and an adjustable charging circuit and/or an adjustable discharging circuit thereof. Wherein the charge pump outputs a current when receiving the UP signal and discharges the current when receiving the DOWN signal. In the first working mode, the charging rate and/or the discharging speed of the second adjustable circuit are/is high, so that the output current fluctuation is high; in the second operation mode, the charging rate and/or the discharging speed of the charging and discharging circuit are/is low, so that the fluctuation of the output current is small.

Referring to fig. 2, a schematic circuit structure of a phase locked loop including a charge pump is shown. Wherein the charge pump CP comprises a second adjustable circuit. The second adjustable circuit includes a first charge pump CP1 and a second charge pump CP2. When receiving an UP signal, the first charge pump CP1 outputs current, and the second charge pump CP2 discharges current; upon receiving the DOWN signal, the first charge pump CP1 discharges a current, and the second charge pump CP2 outputs a current. In the first working mode, the first charge pump CP1 works, and the charging rate and/or the discharging speed of the second adjustable circuit are/is high, so that the output current fluctuates greatly; in the second working mode, the first charge pump CP1 and the second charge pump CP2 work simultaneously, the two charge pumps CP1 and CP2 output reverse currents under the control of the frequency discrimination phase discrimination detection signal, and the charging rate and/or the discharging speed of the second adjustable circuit are slower, so that the output current fluctuation is smaller, and the fluctuation of the control signal is suppressed.

In another example, the low pass filter LPF comprises a first adjustable circuit and the charge pump CP comprises a second adjustable circuit, the first and second adjustable circuits being controlled by external instructions to switch between a first and a second operation mode set during a phase-locked loop loss of lock. The first adjustable circuit can continue the setting mode of the second working mode after the phase-locked loop is locked. For example, the first tunable circuit may include a circuit including a tunable capacitor and/or a tunable resistor within the filter to tune the capacitive characteristics of the filter. After the phase-locked loop is locked, the first adjustable circuit still maintains the capacitance characteristic set by the second operation mode. As another example, the second adjustable circuit includes a circuit configured inside the charge pump to adjust current output/drain. For example, the second adjustable circuit includes a capacitor and an adjustable charging circuit and/or an adjustable discharging circuit thereof. Wherein the charge pump outputs a current when receiving the UP signal and discharges the current when receiving the DOWN signal. In the first working mode, the charging rate and/or the discharging speed of the second adjustable circuit are/is high, so that the output current fluctuation is high; in the second operation mode, the charging rate and/or the discharging speed of the charging and discharging circuit are/is low, so that the fluctuation of the output current is small. After the phase-locked loop is locked, the second adjustable circuit still maintains the state of the charge pump set in the second working mode. Since the charge pump does not output a control signal in the locked state, the frequency of the clock signal output by the oscillator is stable.

Referring to fig. 3, a schematic circuit diagram of a phase locked loop including a charge pump and a loop filter is shown. As shown in fig. 3, the low-pass filter LPF includes: a first adjustable circuit and a capacitor C2. The first adjustable circuit comprises a capacitor C and a resistor R which are connected in series, and the capacitor C and the resistor R are controlled by external instructions. The first adjustable circuit further comprises a signal leakage end connected with the charge pump CP, and the first adjustable circuit is subjected to working mode to adjust parameters of the capacitor C and the resistor R: in a first working mode, no current is transmitted between the signal leakage end and the charge pump CP, and the equivalent integral capacitance of the low-pass filter is a first capacitance value; in the second operation mode, the signal leakage end outputs a current equivalent integrating capacitor to the charge pump CP as a second capacitance value. Wherein the first capacitance value is smaller than the second capacitance value. One end of the capacitor C2 is connected with the resistor R, and the other end of the capacitor C is grounded.

The charge pump CP includes a second adjustable circuit. The second adjustable circuit includes a first charge pump CP1 and a second charge pump CP2. When receiving the UP signal, the first charge pump CP1 outputs current to the low-pass filter, and the second charge pump CP2 discharges current internally; upon receiving the DOWN signal, the first charge pump CP1 internally bleeds current, and the second charge pump CP2 outputs current to the low-pass filter. In the first working mode, the first charge pump CP1 works, and the charging rate and/or the discharging speed of the second adjustable circuit are/is high, so that the output current fluctuates greatly; in the second working mode, the first charge pump CP1 and the second charge pump CP2 work simultaneously, the two charge pumps CP1 and CP2 output reverse currents under the control of the frequency discrimination phase discrimination detection signal, and the charging rate and/or the discharging speed of the second adjustable circuit are slower, so that the output current fluctuation is smaller, and the fluctuation of the control signal is suppressed.

According to an exemplary embodiment, the direction of the current flowing from the charge pump CP to the integrating capacitor C2 is set to be positive, and the direction of the integrating capacitor C2 flowing to the charge pump CP is set to be negative. When the phase-locked loop is in the first operation mode, the first charge pump CP1 is operated, and the capacitor C and the resistor R are adjusted such that the equivalent integrating capacitance of the low-pass filter is the first capacitance. During the first operation mode, the first charge pump CP1 outputs a positive current according to the received UP signal and outputs a negative current according to the received DOWN signal. The current output by the first charge pump CP1 is filtered by a low-pass filter and converted into a control signal to control the frequency of the clock signal output by the voltage-controlled oscillator. When the phase-locked loop is in the second operation mode, the first charge pump CP1 and the second charge pump CP2 are both operated, and the capacitance C and the resistance R are adjusted such that the equivalent integrating capacitance of the low-pass filter is the second capacitance. During the first operation mode, when the first charge pump CP1 outputs a positive current i_cp1 according to the received UP signal and the second charge pump CP2 outputs a negative current i_cp2 according to the received UP signal, the control signal of the low-pass filter is obtained according to (i_cp1-i_cp2); when the first charge pump CP1 outputs a negative current i_cp1 according to the received DOWN signal and the second charge pump CP2 outputs a positive current i_cp2 according to the received DOWN signal, the control signal outputted by the low-pass filter is obtained according to (1i_cp1+i_cp2).

According to an exemplary embodiment, when the phase-locked loop is in the second operation mode and the first charge pump CP1 and the second charge pump CP2 are operated simultaneously, the two charge pumps output reverse currents under the control of the frequency-discrimination phase-discrimination detection signal, so as to suppress the fluctuation of the control signal.

According to an example embodiment, if the output current i_cp2 is N times the bleed current i_cp1, i_cp2=n×i_cp1, and if the phase-locked loop is in the first operation mode, the first charge pump CP1 is turned on, the second charge pump CP2 is turned off, and the equivalent capacitance ceq=c of the loop filter LPF; in the case of the phase-locked loop in the second operating mode, the first charge pump CP1 and the second charge pump CP2 are turned on, and the equivalent integrating capacitance of the loop filter LPF is ceq=c/(1-N), where C is the capacitance of the integrating capacitance C.

Taking n=0.8 as an example according to an exemplary embodiment, the equivalent integrating capacitance of the loop filter LPF is ceq= 5*C in case the phase locked loop is in the second operation mode.

According to some embodiments, when the phase-locked loop is in the first operation mode, the first charge pump CP1 is turned on, the second charge pump CP2 is turned off, the equivalent capacitance ceq=c of the loop filter LPF is increased, the resistance of the resistor R in the loop filter LPF is increased, or the output current i_cp1 of the first charge pump CP1 is increased, the loop filter LPF outputs a clock signal with a wider bandwidth according to the control voltage VCTRL with a larger magnitude of the large charge output, so that the first bandwidth L1 of the phase-locked loop PLL is increased when the phase margin is satisfied.

According to some embodiments, when the phase-locked loop is in the second working mode, the first charge pump CP1 and the second charge pump CP2 are turned on, the equivalent capacitance ceq=c/(1-N) of the loop filter LPF, and the resistance value of the resistor R in the loop filter LPF, the output current i_cp1 of the first charge pump CP1, and the output current i_cp2 of the second charge pump CP2 are normal set values, and because the loop filter LPF circuit leaks, the control voltage VCTRL is suppressed in a narrow control range, the voltage-controlled oscillator VCO outputs a clock signal with a narrower second bandwidth L2, the phase-locked loop bandwidth is reduced, the accuracy of the output clock is good, and a locking process with high accuracy and fast locking speed can be implemented.

According to an exemplary embodiment, the present application also proposes a system for fast locking of a phase locked loop, as shown in fig. 4, comprising a phase locked loop of the present application and a lock monitoring circuit. The lock monitoring circuit is connected to two input ends of the phase frequency detector PFD in the phase-locked loop to receive the frequency division clock signal DIVCLK and the reference clock signal REFCLK output by the Divider Divider. The lock monitoring circuit is used for providing an external instruction. Specifically, the lock monitoring circuit detects the frequency division clock signal DIVCLK and the reference clock signal REFCLK input into the phase-locked loop to sequentially output an instruction corresponding to the first working mode and an instruction corresponding to the second working mode to the phase-locked loop; and the lock monitoring circuit generates a lock signal by detecting the frequency division clock signal DIVCLK and the reference clock signal REFCLK input into the phase-locked loop in the second working mode so as to enable the digital circuit to operate according to the clock signal output by the phase-locked loop.

The lock monitor circuit is exemplified by a logic circuit composed of digital devices including and gates, registers, flip-flops, and the like. According to the set logic, the lock monitoring circuit operates as follows:

when detecting that the skip edges of the frequency division clock signal and the reference clock signal are not synchronous, the locking monitoring circuit determines that the phase-locked loop is out of lock, does not output a locking signal, and outputs an instruction corresponding to a first working mode so as to adjust a charge pump and/or a filter in the phase-locked loop, so that the phase-locked loop performs locking operation under wide bandwidth. And continuously detecting the jump edges of the acquired frequency division clock signal and the reference clock signal, counting/timing at least one synchronous operation by using devices such as a register or a trigger or a slope generator when the frequency division clock signal and the reference clock signal are synchronous, and adjusting a charge pump and/or a filter in the phase-locked loop to a second working state when the count value/timing duration of the synchronous operation triggers an instruction for generating a second working mode, so that the phase-locked loop performs locking operation under a narrow bandwidth. And continuously detecting the jump edges of the acquired frequency division clock signal and the reference clock signal until the synchronous count value/timing duration of the frequency division clock signal and the reference clock signal meets the threshold value of the locking state, and outputting a locking signal. The locking signal is output to a circuit module comprising a digital circuit for the digital circuit to operate according to a clock signal output by the phase-locked loop. Taking the circuit block in the radar sensor as an example, the digital circuit includes at least one of a logic circuit in the ADC, a processor for processing the baseband digital signal, and the like.

The application also provides a digital chip which comprises the system and a signal processing module, wherein the signal processing module is used for processing the received digital signal under the clock signal provided by the system. The chip is exemplified by a radar sensor chip. The radar sensor chip is used to detect measurement information between it and objects in the surrounding environment. Examples of measurement information include: at least one of distance, relative speed, and angle.

The application also provides a radar sensor configured with an antenna array. The radar sensor measures a physical quantity between the radar sensor and an obstacle in the surrounding environment by using a detection signal wave transmitted by the antenna array and a received echo signal wave, for example, at least one of a relative speed, a relative angle, a relative distance, and a three-dimensional profile of the obstacle.

Here, the radar sensor further includes: and the signal receiving and transmitting system and the digital chip. The signal receiving and transmitting system comprises a signal transmitter and a signal receiver, and is used for generating a detection signal wave by utilizing a continuous frequency modulation signal, receiving a corresponding echo signal wave and outputting a baseband digital signal by utilizing the detection signal wave and the echo signal wave; wherein the echo signal wave is formed by reflecting the detection signal wave by an object. The antenna array, the signal transceiver system and the digital chip all determine the circuit structure according to the surrounding environment measured by the radar sensor, so as to send out detection signal waves and receive echo signal waves in a preset frequency band or fixed frequency, and perform signal processing on corresponding changed electric signals.

The signal transmitter is for transmitting radio frequency transmit signals to transmit antennas in an antenna array. Specifically, the signal transmitter performs frequency modulation/phase modulation processing on a reference clock signal provided by a signal source, and modulates the reference clock signal into a radio frequency transmission signal for output to a transmitting antenna. The signal transmitter can generate a radio frequency transmission signal with a fixed frequency as a center frequency or a radio frequency transmission signal with a frequency sweep with the center frequency and a preset bandwidth. For example, the signal transmitter generates a chirp signal according to a preset continuous frequency modulation mode; obtaining a radio frequency emission signal through frequency multiplication; and fed to the transmitting antenna to transmit the corresponding detection signal wave. When the detection signal wave is reflected by the object, an echo signal wave is formed. The receiving antenna converts echo signal waves into radio frequency receiving signals.

The signal receiver is used for performing down-conversion, filtering, analog-to-digital conversion and the like on the radio frequency receiving signal by utilizing the radio frequency transmitting signal so as to output a baseband digital signal representing the difference frequency between the detection signal wave and the echo signal wave.

The digital chip is connected with the signal receiving and transmitting system and is used for extracting measurement information from the baseband digital signal through signal processing, performing signal processing to obtain the measurement information of the radar sensor on the object and outputting measurement data. The signal processing comprises digital signal processing calculation based on phase, frequency, time domain and the like of at least one path of signals to be processed provided by at least one path of receiving antennas. The measurement data includes at least one of: distance data representing a relative distance of the detected at least one obstacle; speed data representing a relative speed of the detected at least one obstacle; angle data representing the relative angle of the detected at least one obstacle, etc.

It should be clearly understood that this application describes how to make and use particular examples, but is not limited to any details of these examples. Rather, these principles can be applied to many other embodiments based on the teachings of the present disclosure.

Furthermore, it should be noted that the above-described figures are merely illustrative of the processes involved in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules. Exemplary embodiments of the present application are specifically illustrated and described above. It is to be understood that this application is not limited to the details of construction, arrangement or method of implementation described herein; on the contrary, the application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A phase locked loop for fast locking comprising:

2. The phase-locked loop of claim 1, wherein the charge pump comprises a first charge pump and a second charge pump:

3. The phase-locked loop of claim 2, wherein the first charge pump and the second charge pump output reverse currents under control of the phase-discriminating detection signal to suppress fluctuations in the control signal when operated simultaneously.

4. The phase-locked loop of claim 1, further comprising a phase frequency detector and a frequency divider, wherein:

5. The phase-locked loop of claim 1, wherein the low-pass filter comprises a first tunable circuit and a first capacitor, wherein:

6. The phase locked loop of claim 5 wherein said first adjustable circuit further comprises a signal leakage terminal connected to said charge pump;

7. The phase-locked loop of claim 5, wherein the first adjustable circuit adjusts parameters of the second capacitor and the first resistor by an operating mode such that an equivalent integrating capacitance of the low-pass filter is a first capacitance value when the phase-locked loop is in the first operating mode; the equivalent integrating capacitor is a second capacitance value under the condition that the phase-locked loop is in the second working mode;

8. A system for fast locking a phase locked loop, comprising:

a phase locked loop for fast locking as claimed in any one of claims 1 to 7;

the lock monitoring circuit is connected with a charge pump and/or a low-pass filter in the phase-locked loop and acquires a frequency division clock signal and a reference clock signal of the phase-locked loop;

the lock monitoring circuit detects a frequency division clock signal and a reference clock signal of the phase-locked loop to output to the phase-locked loop in time sequence: an instruction corresponding to the first working mode and an instruction corresponding to the second working mode; and

9. A digital chip, comprising:

the system for fast locking a phase locked loop of claim 8;

10. A radar sensor, comprising:

the digital chip of claim 9, connected to the signal transceiver system, for performing signal processing on baseband digital signals to obtain measurement information of the object by the radar sensor.

11. The radar sensor of claim 10, wherein the signal transceiver system and the digital chip are packaged in the same integrated circuit.