CN110784214B

CN110784214B - DLL locking indicating circuit and method

Info

Publication number: CN110784214B
Application number: CN201911042422.4A
Authority: CN
Inventors: 吴江
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2019-10-30
Filing date: 2019-10-30
Publication date: 2021-11-30
Anticipated expiration: 2039-10-30
Also published as: CN110784214A

Abstract

The invention discloses a DLL locking indicating circuit and a DLL locking indicating method, and belongs to the technical field of integrated circuit design. The DLL locking indicating circuit comprises a phase discriminator module and chargesThe device comprises a pump/loop filter module, a voltage-controlled delay line module and a locking indication module, wherein the phase discriminator module compares the phase difference between three input clocks, namely CLKD _0 and CLKD _ N, CLKD _2N, and outputs pulse control signals UP and DN; the charge pump/loop filter module controls the voltage V according to pulse control signals UP and DN_CCarrying out charge and discharge; the voltage-controlled delay line module controls the voltage V_CAdjusting the time delay of the clock signals, and outputting 2N clock signals of CLKD _ 1-CLKD _2N in total; the lock indication module determines whether the DLL is locked based on the 2N clock signals and indicates whether the lock is a correct lock or a harmonic lock.

Description

DLL locking indicating circuit and method

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a DLL locking indicating circuit and a DLL locking indicating method.

Background

With the rapid development of integrated circuits, the operating speed of circuit systems is higher and higher, and challenges are provided for data transmission, recovery and the like. To reduce the need for high speed clocks, multi-phase clocks have become a solution. DLL (Delay-Locked Loop) can generate a multi-phase clock with a fixed interval, and is widely applied to the fields of data recovery, oversampling and the like. As the clock frequency range gets wider, how to ensure that the DLL locks correctly and outputs multi-phase clocks at various frequencies becomes a key requirement for DLL design.

The DLL works under a plurality of frequency bands, the voltage-controlled delay line needs to cover a larger delay range, and harmonic locking is easy to occur at the moment, namely the overall delay of the voltage-controlled delay line is n (n =2,3, 4.) clock cycles, so that the phase of an output clock deviates from the phase of a required clock. In order to ensure the DLL to work normally, a lock indication circuit which can monitor the DLL locking condition on line and give an alarm signal when the DLL is locked in a harmonic mode is designed to be a good solution.

Disclosure of Invention

The invention aims to provide a DLL locking indicating circuit and a DLL locking indicating method, which aim to solve the problem that the phase of an output clock deviates from a required clock phase because the current DLL is easy to generate harmonic locking because a voltage-controlled delay line covers a larger delay range.

In order to solve the above technical problem, the present invention provides a DLL lock indicating circuit for use in a circuit system, the DLL lock indicating circuit comprising:

the phase detector module compares the phase difference between three input clocks of CLKD _0 and CLKD _ N, CLKD _2N and outputs pulse control signals UP and DN;

charge pump/loop filter module based on pulse control signalNumber UP, DN to control voltage V_CCarrying out charge and discharge;

voltage-controlled delay line module by controlling voltage V_CAdjusting the time delay of the clock signals, and outputting 2N clock signals of CLKD _ 1-CLKD _2N in total;

and the locking indicating module is used for judging whether the DLL is locked or not according to the 2N clock signals and indicating whether the locking is correct or harmonic locking.

Optionally, the lock indication module includes a pulse generation unit, a lock detection unit, and a lock type determination unit; wherein the content of the first and second substances,

the PULSE generating unit delays an input clock CLK _ P and generates a narrow PULSE CLK _ PULSE, and the center of the narrow PULSE CLK _ PULSE is aligned with a clock signal CLKD _ 0;

the locking detection unit samples the narrow PULSE CLK _ PULSE, and determines DLL locking and pulls up a locking indication signal when the accumulated M periodic sampling results are all high; m is a counter value of the circuitry configuration;

the locking type judging unit judges the DLL locking type after the locking indication signal is pulled up, and indicates whether the DLL is correctly locked or harmonically locked; when the DLL is locked by harmonic waves, the circuit system resets the DLL and configures the delay of the voltage-controlled delay line module to be the minimum value, so that the DLL retraces and enters a correct locking state.

Optionally, the voltage-controlled delay line module includes 2N same voltage-controlled delay units, an input of which is a clock signal CLKD _0, and the voltage-controlled delay units respectively output the clock signals CLKD _1,. lograph, CLKD _ N,. lograph, CLKD _ 2N.

Optionally, the PULSE width of the narrow PULSE CLK _ PULSE generated by the PULSE generating unit is determined by the number of buffers configured by the circuitry.

Optionally, the pulse generating unit includes two stages of buffers and an xor gate, and the buffers have a delay Δ t_dThe PULSE width of the generated narrow PULSE CLK _ PULSE is 2 Deltat_dThe locked clock signal CLKD _2N is in phase with the clock signal CLKD _0, and if the sampling results are all 1 for M periods, the DLL is judged to be locked.

Optionally, the lock detection unit includes a D flip-flop and a counter M, and an input end of the D flip-flop is connected to an output end of the xor gate.

Optionally, the lock type determining unit includes an and gate and N-1D flip-flops, CLK input ends of the N-1D flip-flops are respectively connected to clock signals CLKD _1,. and CLKD _ (N-1), and D input ends are all connected to a clock CLKD _ 0; the output ends are all connected to the AND gate.

The invention also provides a DLL locking indication method, which comprises the following steps:

step 1, a circuit system configures a buffer in a pulse generating unit and determines the time delay of the buffer;

step 2, the circuit system configures the counter M and determines the times of pulling up the continuous sampling value required by the locking indication to be high;

step 3, after resetting the DLL, starting working and generating a narrow PULSE CLK _ PULSE with the width determined by the step 1;

step 4, sampling the narrow PULSE CLK _ PULSE by a clock signal CLKD _2N clock, judging DLL locking if continuous M periods are all high, and pulling up a locking indication signal;

step 5, when detecting that the locking indication signal is high, the locking type judgment unit starts to work, and clock signals CLKD _1 to CLKD _ (N-1) sample a clock signal CLKD _ 0;

step 6, when all sampling values are in phase with the result being high, the locking type is correct locking, otherwise, the locking type is judged to be harmonic locking;

step 7, resetting the DLL when the DLL is subjected to harmonic locking, and setting the delay of the voltage-controlled delay line module to be minimum;

and 8, repeating the steps 3-7 until the DLL is correctly locked.

The invention provides a DLL locking indicating circuit and a method thereof. The phase discriminator module compares the phase difference between three input clocks of CLKD _0 and CLKD _ N, CLKD _2N and outputs pulse control signals UP and DN; the charge pump/loop filter module controls the signal according to the pulseNumber UP, DN to control voltage V_CCarrying out charge and discharge; the voltage-controlled delay line module controls the voltage V_CAdjusting the time delay of the clock signals, and outputting 2N clock signals of CLKD _ 1-CLKD _2N in total; the lock indication module determines whether the DLL is locked based on the 2N clock signals and indicates whether the lock is a correct lock or a harmonic lock.

The invention has the following beneficial effects:

the locking of the DLL is judged, the DLL is prevented from entering wrong locking, and the circuit system using the DLL can work stably and reliably.

Drawings

FIG. 1 is a schematic diagram of a DLL lock indication circuit provided by the present invention;

fig. 2 is a schematic flow chart of a DLL locking indication method provided by the present invention.

Detailed Description

The DLL locking indicating circuit and method according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a DLL locking indicating circuit, the structure of which is shown in figure 1, comprising a phase discriminator module 11, a charge pump/loop filter module 12, a voltage-controlled delay line module 13 and a locking indicating module 14. Specifically, the phase detector module 11 compares phase differences between three input clock signals CLKD _0 and CLKD _ N, CLKD _2N, and outputs pulse control signals UP and DN; the charge pump/loop filter module 12 couples the control voltage V according to the pulse control signals UP and DN_CCarrying out charge and discharge; the voltage-controlled delay line module 13 controls the voltage V_CAdjusting the delay thereof with respect to the control voltage V_CThe clock signal has monotonicity and good linearity, and 2N clock signals of CLKD _1 to CLKD _2N are output; the lock indication module 14 determines whether the DLL is locked based on the 2N clock signals and indicates whether it is a correct lock or a false lock.In order to meet the requirements of different input frequencies, the delay range of the voltage-controlled delay line module 13 is large, and may cover 0-n clock cycles T, when the DLL is correctly locked, the overall delay of the voltage-controlled delay line module 13 is 1 cycle T, but when the harmonic is locked, the overall delay of the voltage-controlled delay line module 13 is n × T (n =2,3, 4.).

Further, the lock indication module 14 includes a pulse generation unit 141, a lock detection unit 142, and a lock type determination unit 143; wherein, the PULSE generating unit 141 delays the input clock CLK _ P and generates a narrow PULSE CLK _ PULSE with configurable width, the center of the narrow PULSE CLK _ PULSE is aligned with the clock signal CLKD _ 0; the lock detection unit 142 samples the narrow PULSE CLK _ PULSE by using the clock signal output by the voltage-controlled delay line module 13, and determines that the DLL is locked when the sampling results are all high when M cycles (where M is a counter value configured by a circuit system, generally M >100, such as M =256, 512.. et.) are accumulated; after the lock indication signal is pulled high, the lock type determination unit 143 determines the DLL lock type, and indicates whether the DLL is locked correctly or locked in a harmonic mode: when the clock signal CLKD _ 1-CLKD _ (N-1) is correctly locked, the sampling results of the clock signal CLKD _0 are all high, if the sampling results are low, the DLL is in harmonic locking, namely the integral delay of the voltage-controlled delay line module 13 is more than 1 cycle. When the DLL is locked by harmonic waves, the circuit system resets the DLL and configures the delay of the voltage-controlled delay line module 13 to be the minimum value, so that the DLL retraces and enters a correct locking state.

Specifically, referring to fig. 1, the voltage-controlled delay line module 13 includes 2N identical voltage-controlled delay units, that is, the voltage-controlled

delay units

1, 1.. voltage-controlled delay units N, 2N, and the input of the voltage-controlled delay units is the clock signal CLKD _0, and the 2N voltage-controlled delay units output the clock signals CLKD _1, 1.. multidot., CLKD _ N,.. multidot., CLKD _2N to the lock indication module 14, respectively.

Specifically, the PULSE width of the narrow PULSE CLK _ PULSE generated by the PULSE generating unit 141 is determined by the number of buffers configured by the circuitry. As shown in fig. 2, the pulse generating unit 141 includes two stages of buffers and an exclusive-norOr gate, buffer delay delta t_dThe input clock CLK _ P passes through the two-stage buffer to form CLK _ D, and enters the exclusive-OR gate simultaneously with the original input clock CLK _ P, and the PULSE width of the generated narrow PULSE CLK _ PULSE is 2 Deltat_dThe locked clock signal CLKD _2N is in phase with the clock signal CLKD _0, and if the sampling results are all 1 for M periods, the DLL is judged to be locked.

Referring to fig. 2, the lock detection unit 142 includes a D flip-flop and a counter M, and an input terminal of the D flip-flop is connected to an output terminal of the xor gate; the lock type determining unit 143 includes an and gate and N-1D flip-flops, wherein CLK input terminals of the N-1D flip-flops are respectively connected to clock signals CLKD _1, CLKD _2,. and CLKD _ (N-1), and D input terminals are all connected to a clock signal CLKD _ 0; the output ends are all connected to the AND gate; the lock type determining unit 143 indicates the type of lock by sampling the clock signal CLKD _0 through the clock signals CLKD _1, CLKD _2,. and CLKD _ (N-1) after locking.

Example two

The invention provides a DLL locking indication method, a schematic diagram is shown in FIG. 2, and the method comprises the following steps:

and 8, repeating the steps 3-7 until the DLL is correctly locked.

Specifically, the DLL locking indication method judges whether the DLL is locked or not based on the phase relation of the output clock when the DLL is locked, and further judges whether the DLL is correctly locked or is locked in a harmonic mode if the DLL is locked. The buffer of the pulse generating unit 141 may be composed of cascaded reverse phase chains, and the number of delay units thereof may be configured online; to avoid the DLL entering the harmonic locking, the delay of the voltage-controlled delay line module 13 needs to be set from the beginning, if the delay of the voltage-controlled delay line module 13 and the control voltage V are set_CIn direct proportion, the control voltage is pulled to 0 when the power-on reset is carried out, otherwise, the control voltage is pulled to VDD; when the locking type judging unit 143 is high, the DLL is indicated to be correctly locked, and the loop normally works; when the output of the lock type determining unit 143 is low, the lock type determining unit indicates that the DLL is locked by the harmonic wave, and the DLL may be reset according to the signal, so that the DLL operates normally.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A DLL lock indication circuit for use in a circuit system, the DLL lock indication circuit comprising:

a charge pump/loop filter module for controlling the voltage V according to the pulse control signals UP and DN_CCarrying out charge and discharge;

the locking indicating module is used for judging whether the DLL is locked or not according to the 2N clock signals and indicating whether the locking is correct or harmonic locking;

the locking indication module comprises a pulse generation unit, a locking detection unit and a locking type judgment unit; the PULSE generation unit delays an input clock CLK _ P and generates a narrow PULSE CLK _ PULSE, and the center of the narrow PULSE CLK _ PULSE is aligned with a clock signal CLKD _ 0;

the locking type judging unit judges the DLL locking type after the locking indication signal is pulled up, and indicates whether the DLL is correctly locked or harmonically locked; when the DLL is subjected to harmonic locking, the circuit system resets the DLL and configures the delay of the voltage-controlled delay line module to be the minimum value, so that the DLL is retraced and enters a correct locking state;

the voltage-controlled delay line module comprises 2N same voltage-controlled delay units, the input of the voltage-controlled delay line module is a clock signal CLKD _0, and the voltage-controlled delay units respectively output clock signals CLKD _1, clka, CLKD _ N, clkD _ 2N;

the PULSE width of the narrow PULSE CLK _ PULSE generated by the PULSE generation unit is determined by the number of buffers configured by the circuit system;

the pulse generating unit comprises two stages of buffers and an exclusive-OR gate, and the time delay of the buffers is delta t_dThe PULSE width of the generated narrow PULSE CLK _ PULSE is 2 Deltat_dThe locked clock signal CLKD _2N is in phase with the clock signal CLKD _0, and if the sampling results are all 1 for M periods, the DLL is judged to be locked.

2. The DLL lock indication circuit of claim 1, wherein the lock detection unit comprises a D flip-flop and a counter M, the D flip-flop input terminal being connected to the xor gate output terminal.

3. The DLL lock indication circuit of claim 1, wherein the lock type determination unit includes an and gate and N-1D flip-flops, the CLK input terminals of the N-1D flip-flops are respectively connected to clock signals CLKD _1,. and CLKD _ (N-1), and the D input terminals are respectively connected to a clock CLKD _ 0; the output ends are all connected to the AND gate.

4. A DLL lock indication method, comprising the steps of:

and 8, repeating the steps 3-7 until the DLL is correctly locked.