CN106357266B - Lock detecting circuit, method and phase lock circuitry - Google Patents
Lock detecting circuit, method and phase lock circuitry Download PDFInfo
- Publication number
- CN106357266B CN106357266B CN201610737928.7A CN201610737928A CN106357266B CN 106357266 B CN106357266 B CN 106357266B CN 201610737928 A CN201610737928 A CN 201610737928A CN 106357266 B CN106357266 B CN 106357266B
- Authority
- CN
- China
- Prior art keywords
- signal
- operating mode
- sampled
- phaselocked loop
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000001514 detection method Methods 0.000 claims abstract description 29
- 238000005070 sampling Methods 0.000 claims description 22
- 238000010586 diagram Methods 0.000 description 17
- 239000013078 crystal Substances 0.000 description 5
- 241000208340 Araliaceae Species 0.000 description 4
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 4
- 235000003140 Panax quinquefolius Nutrition 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 235000008434 ginseng Nutrition 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/14—Preventing false-lock or pseudo-lock of the PLL
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of lock detecting circuit, method and phase lock circuitries.The lock detecting circuit respectively with the reference signal input terminal and feedback signal input terminal and controller of phaselocked loop are coupled, which includes phase-comparison circuit and state detection circuit；The phase-comparison circuit is for receiving reference signal from the reference signal input terminal of the phaselocked loop respectively, feedback signal is received from the feedback signal input terminal of the phaselocked loop, and operating mode signal is received from the controller, and according to the reference signal, the feedback signal and the operating mode signal, generate contrast signal, the state detection circuit, according to the clock signal and the contrast signal, detects the working condition of the phaselocked loop for obtaining clock signal and the contrast signal.The structure of the lock detecting circuit is simple.
Description
Technical field
The present invention relates to field of communication technology, in particular to a kind of lock detecting circuit, method and phase lock circuitry.
Background technique
Phaselocked loop is one kind under normal operating conditions (i.e. lock state), can make the feedback signal of output and input
Reference signal keeps the closed control circuit of identical frequency and constant phase difference, is generally used for broadcast, communication, frequency
Synthesis and clock such as synchronize at the technical fields.Traditional phaselocked loop is generally by phase frequency detector, charge pump, loop filter, pressure
Control oscillator and frequency divider composition.Due to being easy to cause and answering when phaselocked loop is in abnormal operating state (i.e. out-of-lock state)
It being broken down with the system of the phaselocked loop, it is therefore desirable to special lock detecting circuit determines the working condition of phaselocked loop, with
Just the phaselocked loop in out-of-lock state is detected and is repaired in time.
The device that lock detecting circuit in the related technology is included is more, generally comprises two frequency dividers, two countings
Device and a comparator, the structure of the lock detecting circuit are complex.
Summary of the invention
For the problems in the relevant technologies, the present invention provides a kind of lock-in detection of simplified lock detecting circuit structure electricity
Road, method and phase lock circuitry.The technical solution is as follows:
On the one hand, provide a kind of lock detecting circuit, the lock detecting circuit respectively with the reference signal of phaselocked loop is defeated
Enter end and feedback signal input terminal and controller be coupled, the lock detecting circuit include: phase-comparison circuit and with this
The state detection circuit that phase-comparison circuit is coupled；The phase-comparison circuit is for defeated from the reference signal of the phaselocked loop respectively
Enter end and receive reference signal, receives feedback signal from the feedback signal input terminal of the phaselocked loop, and receive work from the controller
Operation mode signal, wherein operating mode signal designation operating mode of the phaselocked loop under ideal lock state, the work
Mode includes the first operating mode and the second operating mode, and under first operating mode, the phase of the reference signal is lagged behind
The phase of the feedback signal, in this second mode of operation, the phase of the feedback signal lag behind the phase of the reference signal；It should
Phase-comparison circuit is also used to generate contrast signal according to the reference signal, the feedback signal and the operating mode signal, should
Contrast signal indicates the phaselocked loop and closes in the phase relation under actual working state with the phase under the ideal lock state
It whether identical is, wherein phase relation of the phaselocked loop under the actual working state i.e. phase of the reference signal and the feedback signal
Position relationship；The state detection circuit is believed for obtaining clock signal and the contrast signal, and according to the clock signal and the comparison
Number, the working condition of the phaselocked loop is detected, which includes lock state or out-of-lock state.It is provided by the invention
The detection to the working condition of phaselocked loop can be realized by phase-comparison circuit and state detection circuit for lock detecting circuit, should
Element included in lock detecting circuit is less, and circuit structure is relatively simple.
Optionally, which may include: data trigger (English: Data flip-flop；Referred to as: D touching
Send out device) and logic gate；The clock signal input terminal of the d type flip flop is for receiving the reference signal, the data-signal of the d type flip flop
For receiving the feedback signal, the output end of the d type flip flop is connect input terminal with the first input end of the logic gate, D triggering
Device is used to be sampled to obtain sampled signal to the level of the feedback signal using the reference signal as sampled clock signal；This is patrolled
It collects door to be used to receive the sampled signal by first input end, and the operating mode signal is received by the second input terminal, and
Logical operation is carried out according to the sampled signal and the operating mode signal, generates the contrast signal.
Optionally, which may include: d type flip flop and logic gate；The clock signal input of the d type flip flop
End is used to receive the reference signal for receiving the feedback signal, the data signal input of the d type flip flop, the d type flip flop
Output end is connect with the first input end of the logic gate, which is used for using the feedback signal as sampled clock signal, to this
The sampled signal that the level of reference signal is sampled；The logic gate is used to receive sampling letter by first input end
Number, and the operating mode signal is received by the second input terminal, which is used for according to the sampled signal and the operating mode
Signal carries out logical operation, generates the contrast signal.
Optionally, which is one of XOR operation or same or operation.
Optionally, which may include: counter and comparator；The input terminal of the counter is for receiving
The contrast signal, the clock signal terminal of the counter is for receiving the clock signal, the output end of the counter and the comparator
Input terminal connection, the counter be used for according to the clock signal, to pre- in the contrast signal within the preset counting period
If level carries out counting to get count results, and count results are sent to the comparator；The comparator is for tying the counting
Fruit is compared with preset count threshold, and according to comparison result, detects to the working condition of the phaselocked loop.
Optionally, operating mode of the phaselocked loop under ideal lock state is indicated with high level in the operating mode signal
Working mould of the phaselocked loop under ideal lock state is indicated with low level for the first operating mode and the operating mode signal
In the case that formula is the second operating mode, when the sampled signal is to be believed by the d type flip flop using the reference signal as sampling clock
It number is sampled to obtain, and the contrast signal is when being generated by the logic gate by XOR operation, which is high level；
Alternatively, when the sampled signal is to be sampled to obtain using the feedback signal as sampled clock signal by the d type flip flop, and this is right
It is when passing through same or operation by the logic gate to generate than signal, which is high level；Alternatively, when the sampled signal be by
The d type flip flop is sampled to obtain using the reference signal as sampled clock signal, and the contrast signal is led to by the logic gate
When crossing same or operation generation, which is low level；Alternatively, when the sampled signal is by the d type flip flop with the feedback letter
It number is sampled to obtain as sampled clock signal, and the contrast signal is when being generated by the logic gate by XOR operation, this
Predetermined level is low level.
Optionally, operating mode of the phaselocked loop under ideal lock state is indicated with low level in the operating mode signal
Working mould of the phaselocked loop under ideal lock state is indicated with high level for the first operating mode and the operating mode signal
In the case that formula is the second operating mode, when the sampled signal is to be believed by the d type flip flop using the reference signal as sampling clock
It number is sampled to obtain, and the contrast signal is when being generated by the logic gate by XOR operation, which is low level；
Alternatively, when the sampled signal is to be sampled to obtain using the feedback signal as sampled clock signal by the d type flip flop, and this is right
It is when passing through same or operation by the logic gate to generate than signal, which is low level；Alternatively, when the sampled signal be by
The d type flip flop is sampled to obtain using the reference signal as sampled clock signal, and the contrast signal is led to by the logic gate
When crossing same or operation generation, which is high level；Alternatively, when the sampled signal is by the d type flip flop with the feedback letter
It number is sampled to obtain as sampled clock signal, and the contrast signal is when being generated by the logic gate by XOR operation, this
Predetermined level is high level.
Optionally, which is specifically used for: the count results being compared with preset count threshold, when the counting
When being as a result greater than the count threshold, determine that the working condition of the phaselocked loop is out-of-lock state；When the count results are not more than the meter
When number threshold value, determine that the working condition of the phaselocked loop is lock state.
Optionally, the clock signal which obtains can be the reference signal；Alternatively, the lock-in detection
Circuit can also include: clock generator, then the state detection circuit can also obtain the clock signal from the clock generator.
Second aspect provides a kind of lock detecting method, is applied to lock detecting circuit, which includes:
Phase-comparison circuit and the state detection circuit being coupled with the phase-comparison circuit, the lock detecting circuit respectively with, lock
The reference signal input terminal and feedback signal input terminal and controller of phase ring are coupled, this method comprises: respectively from the locking phase
The reference signal input terminal of ring receives reference signal, receives feedback signal, Yi Jicong from the feedback signal input terminal of the phaselocked loop
The controller receives operating mode signal, wherein the operating mode signal designation phaselocked loop is under the ideal lock state
Operating mode, which includes the first operating mode and the second operating mode, and under first operating mode, this is with reference to letter
Number phase lag behind the phase of the feedback signal, in this second mode of operation, the phase of the feedback signal lags behind the ginseng
Examine the phase of signal；According to the reference signal, the feedback signal and the operating mode signal, contrast signal, the comparison are generated
The signal designation phaselocked loop under actual working state phase relation with state the phase relation under ideal lock state at this
It is whether identical, wherein phase relation of the phaselocked loop under the actual working state i.e. phase of the reference signal and the feedback signal
Position relationship；Obtain clock signal and contrast signal, and according to the clock signal and the contrast signal to the work shape of the phaselocked loop
State is detected, which includes lock state or out-of-lock state.Lock detecting method provided by the invention can be from control
Device processed receives operating mode signal, and is detected based on the operating mode signal to the working condition of phaselocked loop, the detection
Journey is relatively simple, and detection efficiency is higher.
Optionally, according to the reference signal, the feedback signal and the operating mode signal, the specific of contrast signal is generated
Process may include: to sample, sampled to the level of the feedback signal using the reference signal as sampled clock signal
Signal；Logical operation is carried out according to the sampled signal and the operating mode signal, generates the contrast signal.
Optionally, it according to the reference signal, the feedback signal and the operating mode signal, generates contrast signal and obtains specifically
Process can also include: to sample, adopted to the level of the reference signal using the feedback signal as sampled clock signal
Sample signal；Logical operation is carried out according to the sampled signal and the operating mode signal, generates the contrast signal.
Optionally, which can be one of XOR operation or same or operation.
Optionally, specific according to the process detected according to clock signal and contrast signal to the working condition of phaselocked loop
It may include: to be counted to get within the preset counting period to the predetermined level of the contrast signal according to the clock signal
Count results；The count results are compared with preset count threshold, and the work according to comparison result, to the phaselocked loop
State is detected.
Optionally, operating mode of the phaselocked loop under ideal lock state is indicated with high level in the operating mode signal
Working mould of the phaselocked loop under ideal lock state is indicated with low level for the first operating mode and the operating mode signal
In the case that formula is the second operating mode, when the sampled signal is to be believed by the d type flip flop using the reference signal as sampling clock
It number is sampled to obtain, and the contrast signal is when being generated by the logic gate by XOR operation, which is high level；
Alternatively, when the sampled signal is to be sampled to obtain using the feedback signal as sampled clock signal by the d type flip flop, and this is right
It is when passing through same or operation by the logic gate to generate than signal, which is high level；Alternatively, when the sampled signal be by
The d type flip flop is sampled to obtain using the reference signal as sampled clock signal, and the contrast signal is led to by the logic gate
When crossing same or operation generation, which is low level；Alternatively, when the sampled signal is by the d type flip flop with the feedback letter
It number is sampled to obtain as sampled clock signal, and the contrast signal is when being generated by the logic gate by XOR operation, this
Predetermined level is low level.
Optionally, operating mode of the phaselocked loop under ideal lock state is indicated with low level in the operating mode signal
Working mould of the phaselocked loop under ideal lock state is indicated with high level for the first operating mode and the operating mode signal
In the case that formula is the second operating mode, when the sampled signal is to be believed by the d type flip flop using the reference signal as sampling clock
It number is sampled to obtain, and the contrast signal is when being generated by the logic gate by XOR operation, which is low level；
Alternatively, when the sampled signal is to be sampled to obtain using the feedback signal as sampled clock signal by the d type flip flop, and this is right
It is when passing through same or operation by the logic gate to generate than signal, which is low level；Alternatively, when the sampled signal be by
The d type flip flop is sampled to obtain using the reference signal as sampled clock signal, and the contrast signal is led to by the logic gate
When crossing same or operation generation, which is high level；Alternatively, when the sampled signal is by the d type flip flop with the feedback letter
It number is sampled to obtain as sampled clock signal, and the contrast signal is when being generated by the logic gate by XOR operation, this
Predetermined level is high level.
Optionally, which is compared by this with preset count threshold, and according to comparison result, to the locking phase
The working condition of ring is detected, comprising: is compared the count results with preset count threshold, when the count results are big
When the count threshold, determine that the working condition of the phaselocked loop is out-of-lock state；When the count results are not more than the count threshold
When, determine that the working condition of the phaselocked loop is lock state.
Optionally, which can be the reference signal；Alternatively, the clock signal can generate for clock generator
Signal.
The third aspect provides a kind of phase lock circuitry, which includes: phaselocked loop, controller and such as first party
Lock detecting circuit described in face, the lock detecting circuit respectively with the reference signal input terminal and feedback signal of phaselocked loop are defeated
Enter end and controller is coupled；The phaselocked loop, which is used to send by the reference signal input terminal to the lock detecting circuit, joins
Signal is examined, and feedback signal is sent to the lock detecting circuit by the feedback signal input terminal；The controller is used for the lock
Regular inspection slowdown monitoring circuit sends operating mode signal, operating mode signal designation work of the phaselocked loop under ideal lock state
Mode, the operating mode include the first operating mode and the second operating mode, in the first operation mode, the phase of the reference signal
Position lags behind the phase of the feedback signal, and in this second mode of operation, the phase of the feedback signal lags behind the reference signal
Phase.
In conclusion technical solution provided by the invention has the benefit that
The present invention provides a kind of lock detecting circuit, method and phase lock circuitry, which includes phase ratio
Compared with circuit and state detection circuit, wherein phase-comparison circuit can be generated and be used to indicate with reference to letter according to operating mode signal
The contrast signal of phase relation number between the feedback signal, state detection circuit can be believed according to reference signal and the comparison
Number, generate state detection signal.Compared to lock detecting circuit in the related technology, in lock detecting circuit provided by the invention
It only include a trigger, a logic gate, a counter and a comparator, the element which is included
Less, circuit structure is relatively simple.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Figure 1A is a kind of structural schematic diagram of phaselocked loop provided in an embodiment of the present invention；
Figure 1B is a kind of partial structural diagram of phaselocked loop provided in an embodiment of the present invention；
Fig. 1 C is the structural schematic diagram of another phaselocked loop provided in an embodiment of the present invention；
Fig. 2 is a kind of application scenarios schematic diagram of lock detecting circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of lock detecting circuit provided in an embodiment of the present invention；
Fig. 4 A is the structural schematic diagram of another lock detecting circuit provided in an embodiment of the present invention；
Fig. 4 B is the sequential relationship schematic diagram of a kind of reference signal and feedback signal provided in an embodiment of the present invention；
Fig. 4 C is the sequential relationship schematic diagram of another reference signal and feedback signal provided in an embodiment of the present invention；
Fig. 5 is a kind of flow chart of lock detecting method provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Figure 1A is a kind of structural schematic diagram of phaselocked loop provided in an embodiment of the present invention, and as shown in Figure 1A, which can
To include crystal oscillator buffer 101, phase frequency detector 102, charge pump 103, low-pass filter 104, voltage-controlled vibrator 105 and frequency dividing
Device 106.Wherein, the crystal oscillator buffer 101 after buffering to the crystal oscillation signal that crystal oscillator input terminal inputs for generating with reference to letter
Number, and the reference signal is exported to phase frequency detector 102, the phase frequency detector 102 is for detecting the reference signal and feedback
The phase difference of signal, and pulse control signal is exported to charge pump 103 according to the phase difference, which is used for basis should
Pulse control signal generates charging current or discharge current, and low-pass filter 104 is used for according to the charging current or electric discharge electricity
The output control voltage of voltage controlled oscillator 105 is flowed to, voltage controlled oscillator 105 can generate oscillating voltage according to the control voltage, with
Just frequency divider 106 generates feedback signal after dividing to the oscillating voltage, and is input to the phase frequency detector 102.From Figure 1A
In as can be seen that the phaselocked loop in phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and frequency divider can be with shape
At a feedback system, which can adjust the frequency and phase of feedback signal so that the frequency of the feedback signal and
Phase is " locked " in the frequency and phase of the reference signal.It that is to say, when the phaselocked loop is in the lock state, this is with reference to letter
Number, constant phase difference identical as the frequency of the feedback signal and phase frequency all the same, or both.
Figure 1B is a kind of partial structural diagram of phaselocked loop provided in an embodiment of the present invention, as shown in Figure 1B, in order to keep away
The non-linear working condition to phaselocked loop for exempting from charge pump 103 in phaselocked loop impacts, generally can also be in charge pump 103
Output end increases compensation electric current (IOffset) 31 improve the non-linear of the charge pump 103, which compensates the phaselocked loop of electric current
Referred to as Offset CP phaselocked loop.When the Offset CP phaselocked loop is in the lock state, have between reference signal and feedback signal
There is certain phase difference.Fig. 1 C is that the structural schematic diagram of another phaselocked loop provided in an embodiment of the present invention as shown in Figure 1 C should
Phaselocked loop includes crystal oscillator buffer 21, phase discriminator 22, low-pass filter 23, voltage controlled oscillator 24 and frequency divider 25, the locking phase
Not set charge pump in ring, the phaselocked loop of the type are also referred to as Type-I phaselocked loop, when the Type-I phaselocked loop is in locking shape
When state, also there is fixed phase difference between reference signal and feedback signal.When for above-mentioned being in the lock state, reference signal
May include two kinds of operating modes with the phaselocked loop of fixed skew between feedback signal: under the first operating mode, reference
The phase of signal lags behind the phase of feedback signal, and in the second operation mode, the phase of feedback signal lags behind reference signal
Phase.
Fig. 2 is a kind of application scenarios schematic diagram of lock detecting circuit provided in an embodiment of the present invention, with reference to Fig. 2, the lock
Regular inspection slowdown monitoring circuit 00 can respectively with the reference signal input terminal a of phaselocked loop 10 and feedback signal input terminal b and controller 20
It is coupled.Fig. 3 is a kind of structural schematic diagram of lock detecting circuit provided in an embodiment of the present invention, as shown in figure 3, the locking is examined
Slowdown monitoring circuit may include: phase-comparison circuit 01 and the state detection circuit being coupled with the phase-comparison circuit 02.
The phase-comparison circuit 01 is used to receive reference signal from the reference signal input terminal a of the phaselocked loop 10 respectively, from
The feedback signal input terminal b of the phaselocked loop 10 receives feedback signal, and receives operating mode signal from the controller 20,
In, operating mode signal designation operating mode of the phaselocked loop under ideal lock state, the operating mode includes first
Operating mode and the second operating mode, under first operating mode, the phase of the reference signal lags behind the feedback signal
Phase, in this second mode of operation, the phase of the feedback signal lag behind the phase of the reference signal.
The phase-comparison circuit 01 is also used to according to the reference signal, the feedback signal and the operating mode signal, raw
In contrast with signal, which indicates phase relation of the phaselocked loop under actual working state and states ideal locking at this
Whether the phase relation under state is identical, wherein phase relation of the phaselocked loop under the actual working state i.e. reference signal
With the phase relation of the feedback signal.
The state detection circuit 02 is used to obtain clock signal and the contrast signal, and according to the clock signal and the comparison
Signal detects the working condition of the phaselocked loop, which includes lock state or out-of-lock state.
Wherein, the operating mode of the phaselocked loop 10, which can be, is controlled by the controller 20, exemplary, for Figure 1B
Shown in Offset CP phaselocked loop, can by control Offset sense of current come control the phaselocked loop ideal lock shape
Operating mode under state, specifically, being to flow to low-pass filter 104 from charge pump 103 when controlling the Offset sense of current
When, operating mode of the phaselocked loop under ideal lock state is the first operating mode；When the control Offset sense of current
It (is i.e. flowed to shown in Figure 1B) when to flow to charge pump from low-pass filter, Working mould of the phaselocked loop under ideal lock state
Formula is the second operating mode.For different types of phaselocked loop, controller is also different to the control method of its operating mode, this hair
Bright embodiment does not limit this.
Fig. 4 A is the structural schematic diagram of another lock detecting circuit provided in an embodiment of the present invention, as shown in Figure 4 A,
In a kind of optional implementation of the present invention, which may include: d type flip flop 011 and logic gate 012.
On the one hand, the clock signal input terminal CK of the d type flip flop 011 is for receiving the reference signal, the number of the d type flip flop
Connect according to signal input part D for receiving the feedback signal, the output end Q of the d type flip flop and the first input end of the logic gate 012
It connects, which is used to be sampled to obtain to the level of the feedback signal using the reference signal as sampled clock signal
Sampled signal.
On the other hand, the clock signal input terminal CK of the d type flip flop 011 can also receive the feedback signal, then the D is triggered
The data signal input D of device 011 receives the reference signal, the output end of the d type flip flop 011 and the first input of the logic gate
End connection, at this point, the d type flip flop can adopt the level of the reference signal using the feedback signal as sampled clock signal
Sample obtains sampled signal.
With reference to Fig. 4 A, which is used to receive the sampled signal of d type flip flop output by the first input end,
And the operating mode signal is received by the second input terminal of the logic gate, and believe according to the sampled signal and the operating mode
Number carry out logical operation, generate contrast signal.Specifically, the logic gate can be XOR gate, then the XOR gate can be right at this time
The sampled signal and the operating mode signal generate the contrast signal after carrying out XOR operation；Alternatively, the logic gate can also be
Same or door, the same or door generate the contrast signal after can carrying out same or operation to the sampled signal and the operating mode signal.
It should be noted that in practical applications, being also provided with multiple logic gates in the phase-comparison circuit 01
012, for example, with door or door perhaps multiple logic gate such as NAND gate can be realized XOR gate or with or door logical effect,
The embodiment of the present invention is not specifically limited the number and type of logic gate in the phase-comparison circuit.
Further, with reference to Fig. 4 A, in a kind of optional implementation of the present invention, which be can wrap
It includes: counter 021 and comparator 022.
The input terminal of the counter 021 is for receiving the contrast signal, and the clock signal terminal CK of the counter 021 is for connecing
Clock signal is received, the output end of the counter 021 is connect with the input terminal of the comparator 022, which is used for basis should
Clock signal carries out the predetermined level in the contrast signal within the preset counting period to count to get count results, and will
The count results are sent to the comparator 022.
Wherein, with reference to Fig. 4 A, which can also include: clock generator 03, which is received
Clock signal can be the dagital clock signal generated by the clock generator 03, the frequency of the clock signal can be according to
Actual conditions are pre-set；Or it can also be directly by the reference signal input terminal and the counter 021 in the phaselocked loop
Clock signal terminal is coupled, and that is to say, using the reference signal in the phaselocked loop as the clock signal of the counter 021.In addition,
The preset counting period can be general to count week according to the actual conditions flexible setting of lock detecting circuit in the counter 021
Phase is longer, and the detection accuracy of the lock detecting circuit is higher.
The comparator 022 is used to for the count results that the counter 021 is sent being compared with preset count threshold, and
The state detection signal is generated according to comparison result.Specifically, determining the locking phase when the count results are greater than the count threshold
The working condition of ring is out-of-lock state；When the count results are not more than the count threshold, the working condition of the phaselocked loop is determined
For lock state.
It should be noted that in practical applications, can be set in the counter 021 defeated for the count pick up period
Enter end, also can be set for count pick up threshold value and count the input terminal in period, the comparator 022 in the comparator 022
The count results received within the counting period can be compared with preset count threshold.
In a kind of optional implementation of the present invention, it is assumed that the phaselocked loop is in the first operating mode (i.e. reference signal
Phase lag behind the phase of feedback signal) when, the operating mode signal of controller output is high level, which is in the
When two operating modes (i.e. the phase of feedback signal lags behind the phase of reference signal), which is low level, ginseng
Fig. 4 A is examined, reference signal is received with the clock signal terminal CK of the d type flip flop 011, data signal end D receives feedback signal, this is patrolled
Door 012 is collected as XOR gate, the working principle of the lock detecting circuit is described in detail.Due to the d type flip flop 011
Clock signal terminal CK receives reference signal, therefore the d type flip flop 011 can be using the reference signal as sampled clock signal, logarithm
It is sampled, be that is to say according to the feedback signal that signal end D is inputted, in the rising edge of the reference signal, to the of the logic gate 012
One input terminal exports the level of the feedback signal.
Fig. 4 B and Fig. 4 C are phaselocked loop provided in an embodiment of the present invention reference signal and feedback letters under different working modes
Number timing diagram.Wherein Fig. 4 B be phaselocked loop in the first operating mode (i.e. the phase of reference signal lags behind feedback signal
Phase) under, the timing diagram of reference signal and feedback signal, it is assumed that the reference signal and feedback signal are effective in high level,
Then it can be seen in fig. 4b when the phase of reference signal lags behind the phase of feedback signal, if the reference signal and feedback letter
Phase relation between number stablizes (i.e. when phaselocked loop is in the lock state), rising edge pair of the d type flip flop 011 in reference signal
When feedback signal is sampled, obtained sampled signal is high level (i.e. the level of A point in Fig. 4 B), and the d type flip flop is defeated at this time
Out 1；If the phase relation between the reference signal and feedback signal is unstable (i.e. when phaselocked loop is in out-of-lock state), the D
The sampled signal for the feedback signal that trigger 011 exports then may be 1, it is also possible to also include 0.
Fig. 4 C is phaselocked loop under the second operating mode (i.e. the phase of feedback signal lags behind the phase of reference signal), ginseng
The timing diagram for examining signal and feedback signal can be seen that from Fig. 4 C when the phase of feedback signal lags behind the phase of reference signal
When, if phase relation between the reference signal and feedback signal is stablized, d type flip flop 011 reference signal rising edge to anti-
When feedback signal is sampled, the signal sampled is low level (i.e. the level of B point in Fig. 4 C), i.e. d type flip flop output 0；
If the phase relation between the reference signal and feedback signal is unstable, the sampling letter of the feedback signal of d type flip flop output
It number then may be 0, it is also possible to also include 1.
The working principle of XOR gate is as shown in table 1, i.e. when the level of two input terminals input is different, exporting is 1, and two defeated
When entering to hold the level of input identical, exporting is 0.
Table 1
| First input end | Second input terminal | Output end |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Therefore, when phaselocked loop is in the first operating mode, if the phase relation between the reference signal and feedback signal
Stablize, then the d type flip flop 011 should be 1 to the signal that the first input end of XOR gate 012 exports, due to the XOR gate 012 at this time
The operating mode signal of second input terminal input is 1, then the contrast signal of 012 output end of XOR gate output should be all 0；If the ginseng
The phase relation examined between signal and feedback signal is unstable, then the first input end of d type flip flop 011 to the XOR gate 012 is defeated
Signal out is also unstable, i.e., the signal that the d type flip flop 011 is exported to the first input end of logic gate 012 at this time may be 1
It may be 0, therefore the contrast signal of the XOR gate 012 output at this time is 1 or 0.
When operating mode of the phaselocked loop under ideal lock state is the second operating mode, the i.e. delayed phase of feedback signal
When the phase of reference signal, if phase relation between the reference signal and feedback signal is stablized, the d type flip flop 011 is to different
Or the signal of the first input end output of door 012 should be 0, due to the Working mould of 012 second input terminal of XOR gate input at this time
Formula signal is 0, then the contrast signal of 012 output end of XOR gate output also should be 0；If between the reference signal and feedback signal
Phase relation it is unstable, then the XOR gate 012 output contrast signal be 1 or 0.
According to above-mentioned analysis it is found that indicating work of the phaselocked loop under ideal lock state in operating mode signal with high level
Operation mode indicates work of the phaselocked loop under ideal lock state for the first operating mode and operating mode signal with low level
Operation mode is the second operating mode, and the clock signal terminal CK of the d type flip flop receives reference signal, and the logic gate 012 is exclusive or
In the case where door, when the phaselocked loop is lock state, the contrast signal of the XOR gate 012 output should be all 0, when the locking phase
When ring is out-of-lock state, the contrast signal of the XOR gate 012 output can be 1 or 0.Therefore, counter 021 is receiving this
After contrast signal, the predetermined level in the contrast signal that is counted can be high level, that is to say, which can be with
Using the reference signal as clock signal, within the preset counting period, the high level of the contrast signal is counted, example
, it is assumed that the counting period is 1s, and the period of the reference signal is 0.1s, then within the counting period, which can be adopted
Sample obtains 10 level signals, and counts to the high level in 10 level signals, if in counting period 1s, meter
The number statistics of device 021 obtains in 10 level signals including 5 high level, then the counter 021 can send count results 5
To comparator 022.If preset count threshold is 3 in the comparator 022, when comparator 022 receives count results 5,
It can determine that the count results 5 are greater than count threshold 3, and then can determine in the phaselocked loop between reference signal and feedback signal
Phase relation it is unstable, and determine the phaselocked loop be out-of-lock state.
In embodiments of the present invention, due to when phaselocked loop is in the first operating mode, which can be
Low level, correspondingly, when phaselocked loop is in as the second operating mode, which is high level, and the d type flip flop
What middle clock signal terminal was accessed can may be feedback signal for reference signal, and the logic gate is to sampled signal and Working mould
The logical operation that formula signal is carried out can may be same or operation for XOR operation.Therefore, what which was counted is pre-
If level can in the level under different working modes, just, in d type flip flop clock signal be terminated according to the operating mode signal
The type (i.e. the type of logical operation) of the signal type entered and the logic gate is configured.
It is specific as shown in table 2, on the one hand, to indicate that the phaselocked loop locks shape in ideal in the operating mode signal with high level
Operating mode under state indicates that the phaselocked loop is locked in ideal for the first operating mode and the operating mode signal with low level
In the case that operating mode under state is the second operating mode, when the sampled signal is by the d type flip flop with the reference signal
It is sampled to obtain as sampled clock signal, and the contrast signal is when being generated by the logic gate by XOR operation, this is pre-
If level is high level；Alternatively, when the sampled signal is to be carried out by the d type flip flop using the feedback signal as sampled clock signal
Sampling obtains, and the contrast signal is when passing through same or operation by the logic gate to generate, which is high level；Alternatively,
When the sampled signal is to be sampled to obtain using the reference signal as sampled clock signal by the d type flip flop, and the comparison is believed
Number be passed through by the logic gate with or operation generate when, which is low level；Alternatively, when the sampled signal is by the D
Trigger is sampled to obtain using the feedback signal as sampled clock signal, and the contrast signal is by the logic gate by different
Or when operation generation, which is low level.
On the other hand, Working mould of the phaselocked loop under ideal lock state is indicated with low level in the operating mode signal
Formula indicates work of the phaselocked loop under ideal lock state for the first operating mode and the operating mode signal with high level
In the case that mode is the second operating mode, when the sampled signal is by the d type flip flop using the reference signal as sampling clock
Signal is sampled to obtain, and the contrast signal is when being generated by the logic gate by XOR operation, which is low electricity
It is flat；Alternatively, when the sampled signal be sampled to obtain using the feedback signal as sampled clock signal by the d type flip flop, and
The contrast signal is when passing through same or operation by the logic gate to generate, which is low level；Alternatively, working as the sampled signal
It is to be sampled to obtain using the reference signal as sampled clock signal by the d type flip flop, and the contrast signal is by the logic
When door is generated by same or operation, which is high level；Alternatively, when the sampled signal is anti-with this by the d type flip flop
Feedback signal is sampled to obtain as sampled clock signal, and the contrast signal is to be generated by the logic gate by XOR operation
When, which is high level.
Table 2
It should be noted that the above embodiment of the present invention is with the significant level of reference signal and feedback signal for high electricity
It is illustrated for flat, in practical applications, the significant level of the reference signal and feedback signal may be low level, then
The height of predetermined level shown in above-mentioned table 2 also needs to be adjusted accordingly.
It should also be noted that, in practical applications, with the lock of fixed skew between reference signal and feedback signal
Xiang Huan can detect the working condition in phaselocked loop using lock detecting circuit provided in an embodiment of the present invention, this
The application scenarios of the inventive embodiments lock detecting circuit are without limitation.In addition, above-mentioned all optional implementations, Ke Yiren
Meaning combines and forms alternative embodiment of the invention.
In conclusion the lock detecting circuit includes phase ratio the embodiment of the invention provides a kind of lock detecting circuit
Compared with circuit and state detection circuit, wherein phase-comparison circuit can be generated and be used to indicate with reference to letter according to operating mode signal
The contrast signal of phase relation number between the feedback signal, state detection circuit can be believed according to reference signal and the comparison
Number, the working condition of the phaselocked loop is detected.Lock detecting circuit provided in an embodiment of the present invention is by d type flip flop, logic
Door, a counter and a comparator composition, the element which is included is less, and circuit structure is more simple
It is single.
Fig. 5 is a kind of flow chart of lock detecting method provided in an embodiment of the present invention, and this method can be applied to such as Fig. 3
Or in lock detecting circuit shown in Fig. 4 A, as can be seen that the lock detecting circuit includes: phase bit comparison from Fig. 3 or Fig. 4 A
Circuit 01 and the state detection circuit 02 being coupled with the phase-comparison circuit, the lock detecting circuit can respectively with, lock
The reference signal input terminal and feedback signal input terminal and controller of phase ring are coupled, as shown in figure 5, this method can wrap
It includes:
Step 501, respectively from the reference signal input terminal of phaselocked loop receive reference signal, it is defeated from the feedback signal of phaselocked loop
Enter end and receive feedback signal, and receives operating mode signal from controller.
Wherein, operating mode signal designation operating mode of the phaselocked loop under ideal lock state, the Working mould
Formula includes the first operating mode and the second operating mode, and under first operating mode, the phase of the reference signal lags behind this
The phase of feedback signal, in this second mode of operation, the phase of the feedback signal lag behind the phase of the reference signal.
Step 502, according to the reference signal, the feedback signal and the operating mode signal, generate contrast signal.
The contrast signal indicates phase relation of the phaselocked loop under actual working state and states ideal locking shape at this
Whether the phase relation under state identical, wherein phase relation of the phaselocked loop under the actual working state i.e. reference signal and
The phase relation of the feedback signal.
Step 503 obtains clock signal and the contrast signal, and according to the clock signal and the contrast signal to the locking phase
The working condition of ring is detected, which includes lock state or out-of-lock state.
Method shown in step 501 and step 502 can by the phase-comparison circuit 01 in above-mentioned lock detecting circuit
It realizes, method shown in step 503 can be realized by the state detection circuit 02 in the lock detecting circuit.Above-mentioned steps
501 to lock detecting method shown in step 503 specific implementation process can with reference to it is aforementioned for lock detecting circuit work
The description of principle, the embodiment of the present invention repeat no more.
The embodiment of the invention also provides a kind of phase lock circuitries, with reference to Fig. 2, the phase lock circuitry may include: phaselocked loop 10,
Controller 20 and lock detecting circuit 00 as described in relation to the first aspect, the lock detecting circuit 00 is respectively with phaselocked loop 10
Reference signal input terminal a and feedback signal input terminal b and controller 20 are coupled.
The phaselocked loop 10 is used to send reference signal to the lock detecting circuit by the reference signal input terminal a, and leads to
It crosses feedback signal input terminal b and sends feedback signal to the lock detecting circuit.
The controller 20 is used to control the operating mode of the phaselocked loop 10, and sends Working mould to the lock detecting circuit 00
Formula signal, the operating mode signal designation operating mode of the phaselocked loop 10 under ideal lock state, the operating mode packet
The first operating mode and the second operating mode are included, in the first operation mode, the phase of the reference signal lags behind the feedback letter
Number phase, in this second mode of operation, the phase of the feedback signal lags behind the phase of the reference signal.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (19)
1. a kind of lock detecting circuit, which is characterized in that the lock detecting circuit respectively with the input of the reference signal of, phaselocked loop
End and feedback signal input terminal and controller are coupled, the lock detecting circuit include: phase-comparison circuit and with institute
State the state detection circuit that phase-comparison circuit is coupled；
The phase-comparison circuit is for receiving reference signal from the reference signal input terminal of the phaselocked loop respectively, from the lock
The feedback signal input terminal of phase ring receives feedback signal, and receives operating mode signal from the controller, wherein the work
Operation mode signal designation operating mode of the phaselocked loop under ideal lock state, the operating mode include the first work
Mode and the second operating mode, in this first operative mode, the phase of the reference signal lags behind the feedback signal
Phase, in the second mode of operation, the phase of the feedback signal lags behind the phase of the reference signal；
The phase-comparison circuit is also used to according to the reference signal, the feedback signal and the operating mode signal,
Contrast signal is generated, the contrast signal indicates phase relation of the phaselocked loop under actual working state and in the reason
Think whether the phase relation under lock state is identical, wherein phase relation, that is, institute of the phaselocked loop under actual working state
State the phase relation of reference signal and the feedback signal；
The state detection circuit is for obtaining clock signal and the contrast signal, and according to the clock signal and described right
Than signal, the working condition of the phaselocked loop is detected, the working condition includes lock state or out-of-lock state.
2. lock detecting circuit according to claim 1, which is characterized in that the phase-comparison circuit, comprising: data touching
Send out device and logic gate；
The clock signal input terminal of the data trigger is for receiving the reference signal, the data letter of the data trigger
For receiving the feedback signal, the first input end of the output end of the data trigger and the logic gate connects for number input terminal
It connects, the data trigger is used to adopt the level of the feedback signal using the reference signal as sampled clock signal
Sample obtains sampled signal；
The logic gate is used to receive the sampled signal by the first input end, and second by the logic gate is defeated
Enter end and receive the operating mode signal, and logical operation is carried out according to the sampled signal and the operating mode signal,
Generate the contrast signal.
3. lock detecting circuit according to claim 1, which is characterized in that the phase-comparison circuit, comprising: data touching
Send out device and logic gate；
The clock signal input terminal of the data trigger is for receiving the feedback signal, the data letter of the data trigger
For receiving the reference signal, the first input end of the output end of the data trigger and the logic gate connects for number input terminal
It connects, the data trigger is used to adopt the level of the reference signal using the feedback signal as sampled clock signal
Sample obtains sampled signal；
The logic gate is used to receive the sampled signal by the first input end, and second by the logic gate is defeated
Enter end and receive the operating mode signal, and logical operation is carried out according to the sampled signal and the operating mode signal,
Generate the contrast signal.
4. lock detecting circuit according to claim 2 or 3, which is characterized in that
The logical operation is one of XOR operation or same or operation.
5. lock detecting circuit according to claim 4, which is characterized in that the state detection circuit, comprising: counter
And comparator；
For the input terminal of the counter for receiving the contrast signal, the clock signal terminal of the counter is described for receiving
Clock signal, the output end of the counter are connect with the input terminal of the comparator, the counter be used for according to it is described when
Clock signal carries out the predetermined level in the contrast signal within the preset counting period to count to get count results, and will
The count results are sent to the comparator；
The comparator is used to for the count results being compared with preset count threshold, and according to comparison result, to institute
The working condition for stating phaselocked loop is detected.
6. lock detecting circuit according to claim 5, which is characterized in that
Indicate that operating mode of the phaselocked loop under ideal lock state is first in the operating mode signal with high level
Operating mode and the operating mode signal indicate operating mode of the phaselocked loop under ideal lock state with low level
In the case where for the second operating mode,
When the sampled signal is to carry out sampling using the reference signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when being generated by the logic gate by XOR operation, the predetermined level is high level；Alternatively,
When the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when passing through same or operation by the logic gate to generate, the predetermined level is high level；Alternatively,
When the sampled signal is to carry out sampling using the reference signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when passing through same or operation by the logic gate to generate, the predetermined level is low level；Alternatively,
When the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when being generated by the logic gate by XOR operation, the predetermined level is low level.
7. lock detecting circuit according to claim 5, which is characterized in that
Indicate that operating mode of the phaselocked loop under ideal lock state is first in the operating mode signal with low level
Operating mode and the operating mode signal indicate operating mode of the phaselocked loop under ideal lock state with high level
In the case where for the second operating mode,
When the sampled signal is to carry out sampling using the reference signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when being generated by the logic gate by XOR operation, the predetermined level is low level；Alternatively,
When the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when passing through same or operation by the logic gate to generate, the predetermined level is low level；Alternatively,
When the sampled signal is to carry out sampling using the reference signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when passing through same or operation by the logic gate to generate, the predetermined level is high level；Alternatively,
When the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by the data trigger
It arrives, and the contrast signal is when being generated by the logic gate by XOR operation, the predetermined level is high level.
8. according to any lock detecting circuit of claim 5 to 7, which is characterized in that the comparator is specifically used for:
The count results are compared with preset count threshold, when the count results are greater than the count threshold,
The working condition for determining the phaselocked loop is out-of-lock state；
When the count results are not more than the count threshold, determine that the working condition of the phaselocked loop is lock state.
9. according to claim 1 to 3 and 5 to 7 any lock detecting circuits, which is characterized in that the state-detection
The clock signal that circuit obtains is the reference signal；
Alternatively, the lock detecting circuit further include: clock generator, the state detection circuit are also used to send out from the clock
Raw device obtains the clock signal.
10. a kind of lock detecting method, which is characterized in that be applied to lock detecting circuit, the lock detecting circuit includes: phase
Bit comparison circuit and the state detection circuit being coupled with the phase-comparison circuit, the lock detecting circuit respectively with,
The reference signal input terminal and feedback signal input terminal and controller of phaselocked loop are coupled, which comprises
Reference signal is received from the reference signal input terminal of the phaselocked loop respectively, from the feedback signal input terminal of the phaselocked loop
Feedback signal is received, and receives operating mode signal from the controller, wherein the operating mode signal designation is described
Operating mode of the phaselocked loop under ideal lock state, the operating mode include the first operating mode and the second operating mode,
In this first operative mode, the phase of the reference signal lags behind the phase of the feedback signal, in second work
Under operation mode, the phase of the feedback signal lags behind the phase of the reference signal；
According to the reference signal, the feedback signal and the operating mode signal, contrast signal, the comparison letter are generated
The phaselocked loop number is indicated in the phase relation under actual working state and the phase relation under the ideal lock state
It is whether identical, wherein the phase relation, that is, reference signal and the feedback letter of the phaselocked loop under actual working state
Number phase relation；
Clock signal and the contrast signal are obtained, and according to the clock signal and the contrast signal to the phaselocked loop
Working condition is detected, and the working condition includes lock state or out-of-lock state.
11. according to the method described in claim 10, it is characterized in that, described according to the reference signal, the feedback signal
And the operating mode signal, generate contrast signal, comprising:
Using the reference signal as sampled clock signal, the level of the feedback signal is sampled, sampled signal is obtained；
Logical operation is carried out according to the sampled signal and the operating mode signal, generates the contrast signal.
12. according to the method described in claim 10, it is characterized in that, described according to the reference signal, the feedback signal
And the operating mode signal, generate contrast signal, comprising:
Using the feedback signal as sampled clock signal, the level of the reference signal is sampled, sampled signal is obtained；
Logical operation is carried out according to the sampled signal and the operating mode signal, generates the contrast signal.
13. method according to claim 11 or 12, which is characterized in that the logical operation is XOR operation or same or fortune
One of calculate.
14. according to the method for claim 13, which is characterized in that described according to the clock signal and the contrast signal
The working condition of the phaselocked loop is detected, comprising:
According to the clock signal, the predetermined level of the contrast signal count to get within the preset counting period
Number result；
Count results are compared with preset count threshold, and according to comparison result, to the working condition of the phaselocked loop
It is detected.
15. according to the method for claim 14, which is characterized in that
Indicate that operating mode of the phaselocked loop under ideal lock state is first in the operating mode signal with high level
Operating mode and the operating mode signal indicate operating mode of the phaselocked loop under ideal lock state with low level
In the case where for the second operating mode,
When the sampled signal be sampled to obtain using the reference signal as sampled clock signal by data trigger, and
The contrast signal is when being generated by logic gate by XOR operation, and the predetermined level is high level；
Alternatively, when the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by data trigger
It arrives, and the contrast signal is when passing through same or operation by logic gate to generate, the predetermined level is high level；
Alternatively, when the sampled signal is to carry out sampling using the reference signal as sampled clock signal by data trigger
It arrives, and the contrast signal is when passing through same or operation by logic gate to generate, the predetermined level is low level；
Alternatively, when the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by data trigger
It arrives, and the contrast signal is when being generated by logic gate by XOR operation, the predetermined level is low level.
16. according to the method for claim 14, which is characterized in that
Indicate that operating mode of the phaselocked loop under ideal lock state is first in the operating mode signal with low level
Operating mode and the operating mode signal indicate operating mode of the phaselocked loop under ideal lock state with high level
In the case where for the second operating mode,
When the sampled signal be sampled to obtain using the reference signal as sampled clock signal by data trigger, and
The contrast signal is when being generated by logic gate by XOR operation, and the predetermined level is low level；
Alternatively, when the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by data trigger
It arrives, and the contrast signal is when passing through same or operation by logic gate to generate, the predetermined level is low level；
Alternatively, when the sampled signal is to carry out sampling using the reference signal as sampled clock signal by data trigger
It arrives, and the contrast signal is when passing through same or operation by logic gate to generate, the predetermined level is high level；
Alternatively, when the sampled signal is to carry out sampling using the feedback signal as sampled clock signal by data trigger
It arrives, and the contrast signal is when being generated by logic gate by XOR operation, the predetermined level is high level.
17. 4 to 16 any method according to claim 1, which is characterized in that it is described by the count results with it is preset
Count threshold is compared, and according to comparison result, is detected to the working condition of the phaselocked loop, comprising:
The count results are compared with preset count threshold, when the count results are greater than the count threshold,
The working condition for determining the phaselocked loop is out-of-lock state；
When the count results are not more than the count threshold, determine that the working condition of the phaselocked loop is lock state.
18. 0 to 12 and 14 to 16 any method according to claim 1, which is characterized in that the clock signal is institute
State reference signal；Alternatively, the clock signal is the signal that clock generator generates.
19. a kind of phase lock circuitry, which is characterized in that the phase lock circuitry includes: phaselocked loop, controller and such as claim 1
To 9 any lock detecting circuits, the lock detecting circuit respectively with the reference signal input terminal and feedback of phaselocked loop
Signal input part and controller are coupled；
The phaselocked loop is used to send reference signal to the lock detecting circuit by the reference signal input terminal, and passes through
The feedback signal input terminal sends feedback signal to the lock detecting circuit；
The controller is used to send operating mode signal, operating mode signal designation institute to the lock detecting circuit
Operating mode of the phaselocked loop under ideal lock state is stated, the operating mode includes the first operating mode and the second Working mould
Formula, in the first operation mode, the phase of the reference signal lag behind the phase of the feedback signal, in second work
Under mode, the phase of the feedback signal lags behind the phase of the reference signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610737928.7A CN106357266B (en) | 2016-08-26 | 2016-08-26 | Lock detecting circuit, method and phase lock circuitry |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610737928.7A CN106357266B (en) | 2016-08-26 | 2016-08-26 | Lock detecting circuit, method and phase lock circuitry |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106357266A CN106357266A (en) | 2017-01-25 |
| CN106357266B true CN106357266B (en) | 2019-07-23 |
Family
ID=57855905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610737928.7A Active CN106357266B (en) | 2016-08-26 | 2016-08-26 | Lock detecting circuit, method and phase lock circuitry |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106357266B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107786202B (en) * | 2017-11-09 | 2021-10-01 | 上海华力微电子有限公司 | Locking indicator circuit with error code eliminating function |
| CN108183708B (en) * | 2018-01-17 | 2022-04-15 | 上海艾为电子技术股份有限公司 | Phase locking detection method and circuit thereof, and phase-locked loop |
| CN108712168B (en) * | 2018-07-26 | 2023-09-26 | 四川知微传感技术有限公司 | Lock detection circuit suitable for analog phase-locked loop |
| CN111222294A (en) * | 2018-11-23 | 2020-06-02 | 深圳市中兴微电子技术有限公司 | Method and device for simulating smooth transition of reference clock in phase-locked loop locking state |
| EP3952089A4 (en) | 2019-04-25 | 2022-03-30 | Huawei Technologies Co., Ltd. | Charge pump, phase-locked loop circuit, and clock control apparatus |
| CN111435827B (en) * | 2020-01-14 | 2023-11-28 | 珠海市杰理科技股份有限公司 | Quick oscillation starting circuit, method, crystal oscillator and integrated chip |
| KR20220106819A (en) | 2020-08-20 | 2022-07-29 | 창신 메모리 테크놀로지즈 아이엔씨 | Detection circuit and detection method |
| CN114076849A (en) * | 2020-08-20 | 2022-02-22 | 长鑫存储技术(上海)有限公司 | Detection circuit and detection method |
| CN112037362B (en) * | 2020-09-04 | 2022-11-11 | 北京骑胜科技有限公司 | Shared vehicle abnormality detection method, shared vehicle abnormality detection device, shared vehicle, and storage medium |
| CN112486248A (en) * | 2020-11-20 | 2021-03-12 | 芯原微电子(上海)股份有限公司 | Transceiving signal recovery method, system and terminal based on multi-FPGA interconnection |
| CN112558684A (en) * | 2020-12-08 | 2021-03-26 | 芯原微电子(上海)股份有限公司 | DUT (device under test) clock signal recovery method and system based on multi-FPGA (field programmable Gate array) interconnection |
| CN114421957B (en) * | 2022-03-29 | 2022-08-16 | 长芯盛（武汉）科技有限公司 | Lock loss detection circuit and lock loss detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388666A (en) * | 2008-10-10 | 2009-03-18 | 哈尔滨工业大学 | Non-linear frequency and phase discriminator without phase discriminating blind zone |
| CN101741380A (en) * | 2009-12-22 | 2010-06-16 | 北京中星微电子有限公司 | Method and system for locking detection of phase-locked loop and phase-locked loop circuit |
| CN104485946A (en) * | 2014-12-05 | 2015-04-01 | 中国航天科技集团公司第九研究院第七七一研究所 | PLL (phase-locked loop) locking state detection circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101750414B1 (en) * | 2011-01-13 | 2017-06-23 | 삼성전자주식회사 | Digital phase frequency detector, digital phase locked loop including the same and method of detecting digital phase frequency |
| US9077512B2 (en) * | 2013-09-18 | 2015-07-07 | Analog Devices, Inc. | Lock detector for phase-locked loop |
-
2016
- 2016-08-26 CN CN201610737928.7A patent/CN106357266B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388666A (en) * | 2008-10-10 | 2009-03-18 | 哈尔滨工业大学 | Non-linear frequency and phase discriminator without phase discriminating blind zone |
| CN101741380A (en) * | 2009-12-22 | 2010-06-16 | 北京中星微电子有限公司 | Method and system for locking detection of phase-locked loop and phase-locked loop circuit |
| CN104485946A (en) * | 2014-12-05 | 2015-04-01 | 中国航天科技集团公司第九研究院第七七一研究所 | PLL (phase-locked loop) locking state detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106357266A (en) | 2017-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106357266B (en) | Lock detecting circuit, method and phase lock circuitry | |
| US8258831B1 (en) | Method and apparatus for clock generator lock detector | |
| CN109639271B (en) | Lock indication circuit and phase-locked loop formed by same | |
| US8536910B2 (en) | System and method for reducing power consumption in a phased-locked loop circuit | |
| US6765444B2 (en) | Cross clocked lock detector circuit for phase locked loop | |
| US8040156B2 (en) | Lock detection circuit and lock detecting method | |
| US7595672B2 (en) | Adjustable digital lock detector | |
| US7676014B2 (en) | Digital lock detector for phase-locked loop | |
| CN111953339B (en) | Phase-locked loop fast locking frequency discrimination circuit | |
| CN101977053A (en) | Locked detection circuit applied to phase locked loop (PLL) with dynamic reconfigurable frequency dividing ratio | |
| CN1917372B (en) | Circuit arrangement for detection of a locking condition for a phase locked loop, and a method | |
| US7859313B2 (en) | Edge-missing detector structure | |
| US20120087402A1 (en) | In-system method for measurement of clock recovery and oscillator drift | |
| CN108768393B (en) | Cycle slip suppression circuit for PLL frequency synthesizer | |
| CN109150171A (en) | A kind of phase frequency detector and clock data recovery circuit of high speed low jitter | |
| CN111464180B (en) | Phase-locked loop circuit with locking detection function | |
| CN107005243B (en) | The phaselocked loop for preventing function is locked with subharmonic | |
| CN107565956A (en) | Applied to the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit | |
| US20050035798A1 (en) | Circuit, apparatus and method for obtaining a lock state value | |
| US8059774B2 (en) | Frequency lock detection | |
| CN106209079A (en) | A kind of phase-locked loop circuit reducing the loop-locking time | |
| CN113489488A (en) | Phase-locked detection circuit | |
| CN103675648B (en) | A kind of device being applied to phaselocked loop irradiation experiment | |
| US20120110365A1 (en) | Method for locking frequency of usb device and usb frequency locking device | |
| US8432201B1 (en) | Phase-locked loop (PLL) circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |