CN114421957B - Lock loss detection circuit and lock loss detection method - Google Patents

Abstract

The invention relates to an out-of-lock detection circuit, which comprises an analog detection circuit, a sampling circuit and a sampling circuit, wherein the analog detection circuit is used for sampling an input signal at a plurality of sampling points of sampling thresholds with different phases and different sizes of the same sampling clock signal so as to obtain a plurality of sampling results; and the logic judgment circuit receives the plurality of sampling results and judges whether the sampling clock signal and the input signal are in an out-of-lock state or not according to the logic relation among the plurality of sampling results. By the technical scheme, the problems of complex and inaccurate detection mode of the current unlocking state can be effectively solved. In addition, the invention also provides a lock loss detection method.

Description

Lock loss detection circuit and lock loss detection method

Technical Field

The present invention relates generally to the field of circuit design. More particularly, the present invention relates to an out-of-lock detection circuit and an out-of-lock detection method.

Background

This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Thus, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.

With the rapid growth of content brought by the development of the internet, the requirements for transmission and storage of data are also higher and higher. The transmission of higher speed data in the medium is inevitably affected by various interferences and noises, so that the data quality is worse and worse, the error rate is higher and higher, and even the data is completely destroyed and cannot be correctly received. Based on this, a clock data recovery circuit is usually inserted in the data transmission path to help save and recover data, completing transmission over long distances. The clock data recovery circuit can help save data and prevent the data from deteriorating to the extent that the data cannot be recovered, and the quality of the data is improved.

Clock and Data Recovery Circuit ("CDR") is a key module in Data transmission, and in order to obtain correct sampling Data, an out-of-lock detection Circuit is required to detect whether the current Circuit state is normal, i.e., whether the input signal and the Clock signal are normally locked. If the lock has been lost, the sampled data cannot be guaranteed to be correct, resulting in a large number of data errors and rate errors. At the moment, the out-of-lock detection circuit is required to send out a flag bit to inform the out-of-lock state of the circuit, and the output is preferably switched to a bypass state through a Multiplexer (MUX), and original data is directly sent without sampling, so that the validity of the data is ensured.

Currently, a great deal of research and papers have proposed some methods of out-of-lock detection to achieve effective monitoring of out-of-lock conditions, but these circuits are often suitable for specific situations or conditions. Two exemplary schemes for implementing out-of-lock detection are described below. For example, the first conventional technical solution is that a circuit counts raw data and sampled data, counts the number of rising edges within a certain time through a Counter, and then compares the output values of the two counters. In the locked situation, the data can be sampled correctly and the values of the two counters should not differ much. If the sampled data cannot be ensured to be correct under the condition of losing lock, the values of the two counters are obviously different, and therefore the information of the losing lock state is obtained.

The first prior art solution has the disadvantage that firstly, if the signal quality of the original data is poor, some edges may not be correctly identified, and in this case, the number of rising edges cannot be accurately counted. Secondly, if the out-of-lock state is that the data rate is slowed or the clock speed is increased, in this case, although the alignment of the data phase and the consistency of the data bit length cannot be guaranteed, the change of data each time can be recorded, so that the indication of the counter to the out-of-lock state is not clear enough, and accurate out-of-lock detection cannot be realized.

The second principle of the prior art is that, in a locked state of the clock data recovery circuit, the phases of the main clock edge and the data edge are aligned, so that if there are two leading clocks and two lagging clocks relative to the phase of the main clock, their edges are necessarily distributed around the data edge, and thus the same or necessary high level of their sampling results is obtained at the data edge, and the high level of the sampling result by the main clock can ensure the continuous accumulation of the following counter. Such a period of time that the counter accumulation will reach a certain threshold value indicates a locked condition. If the lock is lost, the same or certain sampling result of the data edge is low level, the low level is sampled by the main clock, the counter is reset, the accumulated value cannot reach a certain threshold value, the state represents the lock losing state, and therefore the lock losing state is monitored.

In the second prior art, during the execution, an extra clock phase needs to be generated first, and the phase difference of the extra clock needs to be adjusted, which causes difficulty in circuit implementation. Second, the middle requires very short pulses to be generated and phase aligned to the master clock, which is difficult to achieve. Finally, the jitter of the data edge and the clock edge can affect the real-time edge phase alignment, and the larger jitter can further generate wrong pulses to the same or result, thereby affecting the number of counters and causing misjudgment of lock loss. Therefore, the prior art has the problems of complex and inaccurate detection mode of the locking state of the signal, and cannot meet the actual requirement.

Disclosure of Invention

To solve at least one or more of the problems described in the background section, the present invention provides an out-of-lock status detection scheme. By using the scheme of the invention, the monitoring of the input signal out-of-lock state is realized by designing the analog detection circuit and the logic discrimination circuit, the accuracy of the out-of-lock state detection is effectively improved, the circuit structure design is simplified, the algorithm complexity is reduced, and the usability of the circuit is effectively improved. To this end, the present invention provides aspects as follows.

In a first aspect, the present invention provides an out-of-lock detection circuit comprising: the analog detection circuit is used for sampling an input signal at a plurality of sampling points with different phases and different sampling thresholds of the same sampling clock signal so as to obtain a plurality of sampling results; and the logic judgment circuit receives the plurality of sampling results and judges whether the sampling clock signal and the input signal are in an out-of-lock state or not according to the logic relation among the plurality of sampling results.

In one embodiment, the analog detection circuit includes: a clock delay circuit including a multi-stage clock delay buffer for performing one-stage or multi-stage delay on the sampling clock signal to generate a plurality of sampling clock signals of different phases; a data sampling circuit comprising a plurality of samplers, each sampler for sampling the input signal at a corresponding one of the sampling points to obtain a corresponding data sampling signal, wherein each sampler configures the corresponding sampling point by receiving one of the different phase sampling clock signals and/or one of the different size sampling thresholds.

In one embodiment, the plurality of sampling clock signals of different phases includes one or more of: a first sampling clock signal aligned with the center phase of the input signal, one or more second sampling clock signals earlier in phase than the center phase of the input signal, and one or more third sampling clock signals delayed in phase than the center phase of the input signal; and the plurality of samplers comprises a plurality of pairs of samplers, the sampling points of each pair of samplers being configured with a respective sampling clock signal and/or sampling threshold such that the sampling points of each pair of samplers are symmetrical with respect to a horizontal or vertical axis of the input signal.

In one embodiment, the sampler comprises: a pair of first samplers configured to sample the input signal at a second sampling clock signal and a third sampling clock signal, respectively, to obtain corresponding data sampling signals; a pair of second samplers configured to sample the input signal according to a first sampling threshold and a second sampling threshold, respectively, under a first sampling clock signal to obtain corresponding data sampling signals, wherein the first sampling threshold and the second sampling threshold are symmetric with respect to a horizontal axis of the input signal.

In one embodiment, the analog detection circuit further includes a counting circuit connected to the data sampling circuit and configured to count the data sampling signals respectively to obtain a count value of a high level signal or a low level signal within a predetermined time as the sampling result.

In one embodiment, the logic discrimination circuit is further configured to: judging whether a detection area formed by the plurality of sampling points falls into the center of an eye diagram of the input signal or not according to the logic relation among the plurality of sampling results; and outputting a signal indicating an out-of-lock condition in response to the detection region being offset from a center of an eye diagram of the input signal.

In one embodiment, the logic discrimination circuit is further configured to: comparing the sampling results corresponding to the paired samplers pairwise; in response to either comparison exceeding a predetermined deviation, an out-of-lock condition is determined.

In a second aspect, the present invention further provides a lock loss detection method, including: sampling an input signal at a plurality of sampling points with different phases and different sampling thresholds of the same sampling clock signal to obtain a plurality of sampling results; and receiving the plurality of sampling results, and judging whether the sampling clock signal and the input signal are in an out-of-lock state according to the logic relation among the plurality of sampling results.

In one embodiment, the sampling the input signal at a plurality of sampling points having different sampling thresholds of different sizes and different phases of the same sampling clock signal to obtain a plurality of sampling results includes: delaying the sampling clock signal by one or more stages to generate a plurality of sampling clock signals of different phases; and sampling the input signal at a corresponding one of the sampling points to obtain a corresponding data sampling signal, wherein each of the sampling points is configured by one of the sampling clock signals of the different phases and/or one of the sampling thresholds of the different sizes.

In one embodiment, the plurality of sampling clock signals of different phases includes one or more of: a first sampling clock signal aligned with the center phase of the input signal, one or more second sampling clock signals earlier in phase than the center phase of the input signal, and one or more third sampling clock signals delayed in phase than the center phase of the input signal; and the plurality of sampling points comprises a plurality of pairs of sampling points, each pair of sampling points being symmetric with respect to a horizontal axis or a vertical axis of the input signal.

In one embodiment, said sampling said input signal at a corresponding one of said sampling points to obtain a corresponding data sample signal comprises: sampling the input signal under a second sampling clock signal and a third sampling clock signal respectively to obtain corresponding data sampling signals; and under a first sampling clock signal, sampling the input signal according to a first sampling threshold and a second sampling threshold respectively to obtain a corresponding data sampling signal, wherein the first sampling threshold and the second sampling threshold are symmetrical relative to a horizontal axis of the input signal.

In one embodiment, the method further comprises: and counting the data sampling signals respectively to obtain the count value of a high-level signal or a low-level signal in a preset time as the sampling result.

In one embodiment, wherein determining whether the sampling clock signal and the input signal are in an out-of-lock state according to a logical relationship between the plurality of sampling results comprises: judging whether a detection area formed by the plurality of sampling points falls into the center of an eye diagram of the input signal or not according to the logic relation among the plurality of sampling results; and outputting a signal indicating an out-of-lock condition in response to the detection region being offset from a center of an eye diagram of the input signal.

In one embodiment, wherein determining whether the sampling clock signal and the input signal are in an out-of-lock state according to a logical relationship between the plurality of sampling results comprises: comparing the sampling results corresponding to the paired sampling points pairwise; in response to either comparison exceeding a predetermined deviation, an out-of-lock condition is determined.

By using the scheme provided by the invention, the input signals can be sampled at a plurality of sampling points with different phases and sampling thresholds with different sizes through the analog detection circuit, and whether the input signals are in an out-of-lock state or not is judged by using the logic judgment circuit according to the logic relation between sampling results. The whole lock losing detection circuit realizes an adjustable signal detection area and ensures the flexibility of a detection mode. And the out-of-lock state is directly judged according to the sampling result, any short pulse is not required to be generated, the requirement of phase alignment is not required to be met, and the reliability and the usability of the circuit are effectively improved. The logic judgment circuit only needs to work at a very low speed and execute simple logic judgment operation, thereby greatly simplifying the design and implementation difficulty of the logic judgment circuit.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 is a schematic diagram schematically illustrating an exemplary clock data recovery circuit in which embodiments of the present invention are applied;

FIG. 2 is a schematic diagram that schematically illustrates an out-of-lock detection circuit, in accordance with an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an out-of-lock detection circuit according to another embodiment of the present invention;

FIG. 4 is a schematic diagram that schematically illustrates sampling points and an input signal eye diagram in a locked state, in accordance with an embodiment of the present invention;

FIG. 5 is a comparative graph schematically illustrating the relationship of sampling points and input signals in an out-of-lock condition, according to an embodiment of the present invention;

fig. 6 is a schematic diagram that schematically illustrates a method of out-of-lock detection, in accordance with an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by those skilled in the art without making any creative effort based on the embodiments of the present invention, belong to the protection scope of the present invention.

It should be understood that the terms "first", "second", "third" and "fourth", etc. in the claims, the description and the drawings of the present invention are used for distinguishing different objects and are not used for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular form of "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this application refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

The following detailed description of embodiments of the invention refers to the accompanying drawings.

Fig. 1 is a schematic diagram schematically illustrating an exemplary clock data recovery circuit 100 in which embodiments of the present invention are applied. It should be noted that the clock data recovery circuit 100 may be understood as an exemplary application scenario of the out-of-lock detection circuit in the present invention, and the out-of-lock detection circuit in the present invention is not limited thereto.

As shown in fig. 1, the clock recovery circuit 100 may include a phase and frequency detector 101 (i.e., PFD in fig. 1), a voltage-to-current converter 102 (i.e., V2I in fig. 1), a Loop Filter 103 (i.e., Loop Filter in fig. 1), a voltage-controlled oscillator 104 (i.e., VCO in fig. 1), an out-of-lock detection circuit 105 (i.e., LOLD in fig. 1), and a multiplexer 106 (i.e., MUX in fig. 1). The clock recovery circuit 100 is used to recover a clock in a random signal with jitter while sampling an input signal with the recovered clock to obtain a high quality recovered signal. In order to correctly sample the input data, the phase locking relationship between the recovered sampling clock and the input data needs to be maintained, so as to prevent the occurrence of the condition of losing lock under the influence of various external factors. Once the loss-of-lock data occurs, sampling errors and transmission errors occur, the occurrence of the loss-of-lock condition must be detected in time, and therefore, the bypass channel is switched or the upper layer is informed to lock again.

Specifically, when the clock recovery circuit 100 is applied, the input signal (random signal) DIP/DIN and the clock signal CKP/N from the voltage-controlled oscillator 104 obtain the phase error voltage signal UP/DN through the Phase and Frequency Detector (PFD) 101, and are converted into the current signal V2IOUT through the voltage-to-current converter (V2I) 102, and then the control signal VCO _ VCTL to the voltage-controlled oscillator 104 is generated through the Loop Filter (Loop Filter) 103, and finally the output clock frequency of the voltage-controlled oscillator 104 is adjusted to form a closed Loop of the clock recovery circuit, so that the entire clock recovery circuit 100 completes phase locking and performs signal sampling normally. The sampled high quality data is output to a Multiplexer (MUX) through DOP/DON, and the multiplexer 106 is controlled by the loss-of-lock status FLAG bit LOL _ FLAG, or selects the original signal DIP/DIN or selects the locked sampled signal DOP/DON to be output to other subsequent circuits. Wherein the main function of the multiplexer 106 is to quickly switch to the original data path after an out-of-lock condition has occurred. In order to prevent the high-speed signal with abnormal speed from being sent for a long time after the lock losing state occurs, the normal work of a subsequent circuit is influenced. After the out-of-lock state is generated, the data sampled by the clock recovery circuit is not normal data, the sampled data signal is not only that each data bit is possibly wrong and the data rate is also abnormal, so that the out-of-lock state needs to be quickly detected by an out-of-lock detection circuit (LOLD) 105, and the instruction is given to the multiplexer 106 to quickly switch the data channel.

Mainly set forth in the present invention is an out-of-lock detection circuit 105 as shown in fig. 1, which can receive a clock signal CKP/N from a voltage controlled oscillator, a sampling threshold VREFH _ P/N, VREFL _ P/N and an input signal, and generate an out-of-lock status signal (FLAG bit) LOL _ FLAG. The generated clock signal with the corresponding phase is also sent to a phase and frequency detector in the clock recovery circuit to realize phase alignment and sampling with the input data center in a locking state.

Fig. 2 is a schematic diagram that schematically illustrates an out-of-lock detection circuit 105, in accordance with an embodiment of the present invention. It should be noted that the out-of-lock detection circuit 105 can be applied to a circuit requiring signal out-of-lock detection, such as a clock data recovery circuit. The clock data recovery circuit is a key module in ensuring high-speed data transmission, and in order to lock and sample data normally, a clock frequency corresponding to a data rate needs to be found, and then a phase is adjusted to align a clock sampling edge to the middle of the data (for example, the middle position of an input data eye diagram). The out-of-lock detection circuit 105 may be used to detect the locked state of the clock signal and the input signal during this process.

As shown in FIG. 2, the out-of-lock detection circuit 105 may include an analog detection circuit 201 and a logic discrimination circuit 202. Wherein the analog detection circuit 201 may be configured to sample the input signal at a plurality of sampling points having different sized sampling thresholds at different phases of the same sampling clock signal to obtain a plurality of sampling results. In some embodiments, the analog detection circuit 201 may receive a sampling clock signal from a voltage controlled oscillator and then convert the sampling clock signal to a clock signal of a different phase. And then combining the sampling thresholds with different sizes and the clock signals with different phases to obtain a plurality of sampling points, and sampling the input signal according to the plurality of sampling points so as to utilize the sampling result to carry out-of-lock detection. Comprehensive input signal sampling can be realized through the phase of a plurality of sampling clock signals and the setting of a sampling threshold, and the circuit is simple in setting and easy to realize.

The logic determining circuit 202 may be connected to the out-of-lock detection circuit to receive the plurality of sampling results from the analog detection circuit, and determine whether the sampling clock signal and the input signal are in an out-of-lock state according to a logic relationship between the plurality of sampling results. From this, can distinguish the detection of process realization to losing the lock state through simple logic, whole process does not have too much limitation, can effectively promote the flexibility of whole circuit, can realize high-efficient, signal detection processing fast simultaneously to the ease for use of circuit has been improved.

Fig. 3 is a schematic diagram illustrating an out-of-lock detection circuit 300 according to another embodiment of the invention. It should be noted that the out-of-lock detection circuit 300 may be understood as one possible exemplary implementation of the out-of-lock detection circuit 105 in fig. 1. Therefore, the same applies to the following description in connection with fig. 1.

As shown in FIG. 3, the out-of-lock detection circuit 300 may include an analog detection circuit 201 and a logic discrimination circuit 202. Specifically, the analog detection circuit 201 may include a clock delay circuit and a data sampling circuit. The clock DELAY circuit includes a multi-stage clock DELAY buffer 301 (i.e., DELAY _ BUF in fig. 3) to DELAY the sampling clock signal by one or more stages to generate a plurality of sampling clock signals of different phases. In some embodiments, the clock delay circuit may include at least three stages of clock delay buffers 301 to generate three clock signals of different phases. In particular, the plurality of sampling clock signals of different phases may include one or more of: a first sampling clock signal (e.g., CKP/N _ PH1 in fig. 3) phase-aligned with the center of the input signal, one or more second sampling clock signals (e.g., CKP/N _ PH0 in fig. 3) phase-advanced with respect to the center of the input signal, and one or more third sampling clock signals (e.g., CKP/N _ PH2 in fig. 3) phase-delayed with respect to the center of the input signal.

The data sampling circuit may include a plurality of samplers 302, each for sampling an input signal at a corresponding one of the sampling points to obtain a corresponding data sampling signal, wherein each sampler configures the corresponding sampling point by receiving one of the sampling clock signals of a different phase and/or one of the sampling thresholds of a different size. Therefore, the clock delay circuit and the data sampling circuit cooperate to generate different sampling point configurations so as to sample the input signal.

In some embodiments, the plurality of samplers may include a plurality of pairs of samplers, the sampling points of each pair of samplers configured with a respective sampling clock signal and/or sampling threshold such that the sampling points of each pair of samplers are symmetrical with respect to a horizontal or vertical axis of the input signal. In particular, the samplers may include a pair of first samplers (e.g., sampler 302-1 and sampler 302-2 as shown in FIG. 3) and a pair of second samplers (e.g., sampler 302-3 and sampler 302-4 as shown in FIG. 3). Wherein the first sampler may be a sampler without a threshold value, but may also be understood as a sampler with a threshold value of minus infinity. The second sampler may be a thresholded sampler, i.e. a sampler comprising a threshold of a certain size. A pair of first samplers are configured to sample the input signal (DIP/DIN) at a second sampling clock signal (CKP/N _ PH 0) and a third sampling clock signal (CKP/N _ PH 2), respectively, to obtain corresponding data sampling signals (e.g., sampling signal D0 output by sampler 302-1 and sampling signal D2 output by sampler 302-2 shown in fig. 3). A pair of second samplers are configured to sample the input signal (DIP/DIN) according to a first sampling threshold (VREFH _ P/N) and a second sampling threshold (VREFL _ P/N), respectively, under a first sampling clock signal (CKP/N _ PH 1) to obtain corresponding data sampling signals (e.g., D1H output by sampler 302-3 and D1L output by sampler 302-4 shown in fig. 3), wherein the first and second sampling thresholds are symmetric with respect to a horizontal axis of the input signal.

Further, the analog detection circuit 201 may further include a Counter circuit (e.g., Counter shown in fig. 3). In some embodiments, the counting circuit may be connected to the data sampling circuit and configured to count the data sampling signals to obtain a count value of a high level signal or a low level signal for a predetermined time as a sampling result, respectively. Counting the sampling results D0 to D2 as shown in fig. 3 results in corresponding count values CNT0 to CNT 2. Based on this, the logic discrimination circuit 202 can perform the out-of-lock determination according to the count value output by the analog detection circuit 201, thereby effectively reducing the complexity of the out-of-lock detection process.

In some embodiments, the logic discrimination circuit may implement out-of-lock detection by determining a relationship between a detection region formed by a plurality of sampling points and an eye diagram of the input signal. Specifically, whether a detection region formed by a plurality of sampling points falls into the center of the eye diagram of the input signal or not may be determined according to a logical relationship between a plurality of sampling results. If the detection area is detected to be deviated from the center of the eye pattern of the input signal, a signal indicating that the lock is in an unlocked state is output.

In an application scenario, when it is determined whether a detection region formed by a plurality of sampling points falls into the center of the eye pattern of the input signal, two sampling results corresponding to the paired samplers may be compared with each other, and if any one of the comparison results exceeds a predetermined deviation, it is determined that the sampling region is in an out-of-lock state, that is, the detection region is not located in the center of the eye pattern of the input signal. For example, the sampled signal D0 (or count value CNT 0) sampled by the pair of first samplers may be compared with the sampled signal D2 (or count value CNT 2), the sampled signal D1H (or count value CNT 1H) sampled by the pair of second samplers may be compared with the sampled signal D1L (or count value CNT 1L), and if any comparison result exceeds a predetermined deviation, it may be determined that the state is currently out-of-lock.

Fig. 4 is a schematic diagram schematically illustrating a sampling point and an input signal eye diagram in a locked state according to an embodiment of the present invention. FIG. 5 is a comparative graph schematically illustrating the relationship of sampling points and input signals in an out-of-lock condition, according to an embodiment of the present invention.

First, the output clock CKP/N of the vco generates three phase clock signals, namely, the second sampling clock signal CKP/N _ PH0, the first sampling clock signal CKP/N _ PH1, and the third sampling clock signal CKP/N _ PH2, through the clock delay buffer, wherein the first sampling clock signal CKP/N _ PH1 is further sent to the phase and frequency detector in the clock recovery circuit for phase alignment and sampling with the data center (input signal). The clock delay buffer may be an adjustable delay unit or a fixed delay unit.

Of the three phase clock signals, the input data signal DIP/DIN is input to two samplers under the second sampling clock signal CKP/N _ PH0 and the third sampling clock signal CKP/N _ PH2 to obtain two corresponding data sampling results D0 and D2, and the two sampling results are continuously inverted up and down with the change of the input data signal.

Wherein the first sampling clock signal CKP/N _ PH1 is coupled to the input data signal DIP/DIN input to two samplers with thresholds (a pair of second samplers) to obtain two data sampling results D1H and D1L, which are continuously inverted from top to bottom with the input data signal.

The 4 generated data sampling results D0, D1H, D1L, and D2 are sent to 4 counters (counters), respectively, and the counters are responsible for counting the four input data within a predetermined time period to generate 4 count results CNT0, CNT1H, CNT1L, and CNT 2.

Next, the 4 count results CNT0, CNT1H, CNT1L, and CNT2 are transmitted to a subsequent Logic discrimination circuit (Logic) for comparing the results of the counters with each other, and then a judgment is made according to a threshold condition (e.g., a predetermined deviation), generating an out-of-lock status FLAG bit (LOL _ FLAG). And finally, outputting the lock losing status FLAG bit (LOL _ FLAG) to upper-layer control software and a Multiplexer (MUX) for selecting a transmitted data channel after the lock is lost.

As shown in fig. 4, in the locked state, the sampling positions of the 4 samplers in the loss-of-lock detector (LOLD) are in relation to the input data. According to the principle of the clock recovery circuit, it can be known that after the clock recovery circuit is locked, the first sampling clock signal CKP/N _ PH1 is aligned with the center of the eye pattern of the input signal, and then the sampling positions corresponding to the second sampling clock signal CKP/N _ PH0 and the third sampling clock signal CKP/N _ PH2 are respectively aligned with the distances of a delay time before and after the center of the eye pattern on the X-axis, that is, the B position and the D position in fig. 4. While a pair of second samplers (Slicer with VTH) sample using CKP/N _ PH1, seen in the X-axis as the center of the eye diagram, the actual sampling positions are shifted up and down in the Y-axis due to the presence of the positive and negative thresholds introduced by the first and second sampling thresholds VREFH and VREFL, respectively, i.e. the a and C positions in fig. 4. The value range of the sampling threshold value can be set to 50mV to 500mV, for example.

Under normal lock-in conditions, the diamond-shaped detection area formed by A, B, C and D four sampling positions in FIG. 4 exists in the center of the eye diagram, so that the sampling results D0, D1H, D1L and D2 of the 4 samplers corresponding to each sampling are consistent, that is, the results CNT0, CNT1H, CNT1L and CNT2 of the 4 counters are also equal. The logic discrimination circuit compares CNT0 and CNT2, and CNT1H and CNT1L, respectively, and determines an out-of-lock condition by determining that the comparison results are equal or exceed a predetermined deviation. The predetermined deviation set may be set to several tens of times, for example, 50 times, taking 4096 times as an example. If the lock is not kept, the lock losing state FLAG bit (LOL _ FLAG) is kept low.

In the event of loss of lock, the relative phase relationship between the eye pattern of the input data and the sample clocks CKP/N _ PH0, CKP/N _ PH1, CKP/N _ PH2 is uncertain, i.e., the diamond-shaped detection region of fig. 4 consisting of 4 sample positions A, B, C and D cannot be maintained in the middle of the eye pattern, and may occur at the edges or any position of the input data eye pattern.

As shown in fig. 5, the diamond-shaped area is a detection area formed by the sampling points A, B, C and D, and shows several situations that may occur when the position relationship between the falling edge and the rising edge of the input data and the diamond-shaped area is lost:

in the first example, the falling edge of the input signal (curve 501) enters from AB to BC and exits from the diamond detection area, and the sampling results D0 and D2 at the sampling points B and D correspond to high and low levels, respectively, and the two results are different. The sampling results D1H and D1L from sample points a and C both correspond to a low level, and both results are consistent.

In the second example, the falling edge of the input signal (curve 502) enters from AB to CD and exits from the diamond detection area, and the two results are different from the sampling results D0 and D2 at the sampling points B and D, respectively. The sampling results D1H and D1L at the sampling points a and C correspond to low and high levels, respectively, and the two results are different.

In the third example, the falling edge of the input signal (curve 503) enters from AB and exits from AD through the diamond detection region, and both the sampling results D0 and D2 from sample points B and D correspond to high levels, and the two results are consistent. The sampling results D1H and D1L at the sampling points a and C correspond to low and high levels, respectively, and the two results are different.

Under the three falling edge conditions, the sampling results D0 and D2 or D1H and D1L are compared to see the difference of the sampling results, and the occurrence of the out-of-lock condition can be judged.

Further as shown in the right part of fig. 5, the case where a rising edge of the input signal may occur is also shown:

in the 1 st example, the falling edge of the input signal (curve 504) enters from BC to AB and exits from the diamond detection area, and the sampling results D0 and D2 at the sampling points B and D correspond to low and high levels, respectively, and the two results are different. The sampling results D1H and D1L from sample points a and C both correspond to a high level, and both results are consistent.

In the 2 nd example, the falling edge of the input signal (curve 505) enters from BC to AD and exits from the diamond detection area, and the sampling results D0 and D2 at the sampling points B and D correspond to low and high levels, respectively, and the two results are different. The sampling results D1H and D1L at the sampling points a and C correspond to low and high levels, respectively, and the two results are different.

In the 3 rd example, the falling edge of the input signal (curve 506) enters from BC to CD and exits from the diamond detection area, and both the sampling results D0 and D2 from sample points B and D correspond to low level, and the two results are consistent. The sampling results D1H and D1L at the sampling points a and C correspond to low and high levels, respectively, and the two results are different.

In the above 3 rising edge cases, the difference of the sampling results can be seen by comparing the sampling results D0 with D2 or D1H with D1L.

The results of the above are comprehensively analyzed, and it can be seen that the differences of the sampling results can be seen by comparing the sampling results D0 and D2 or D1H and D1L under the condition of losing the lock, and the differences of the sampling results can cause the results CNT0, CNT1H, CNT1L and CNT2 of the following 4 counters to have deviation. The logic discrimination circuit compares CNT0 and CNT2, and CNT1H and CNT1L, respectively, and determines that an out-of-lock state has occurred, i.e., lock cannot be maintained, by determining that the comparison results are not equal or have a large deviation, and then generates a state where an out-of-lock state FLAG (LOL _ FLAG) is high.

It is to be understood that the foregoing diamond-shaped detection regions formed by the sampling points A, B, C and D are illustrative and not restrictive, and those skilled in the art can form different forms of detection regions by setting sampling clock signals and sampling thresholds of different phases according to actual needs. For example, a rectangular or square detection area can be formed by four sampling points. Taking a rectangular detection area as an example, when the detection area is a rectangle, the sampling points are 4 vertices, and the sampling of four points of the rectangle can be realized by only setting 2 pairs of band threshold samplers and the sampling clock phase. The sampling clock, which is output to both the phase and frequency detectors, may be obtained by further delay operations and is not used for sampling in out-of-lock detection. Furthermore, a regular hexagonal detection area can be formed by six sampling points, or other detection areas with symmetrical structures can be formed by a plurality of different sampling points.

The loss of lock detection principle of the present invention is explained in detail in the above with reference to the circuit structure. As can be seen from the above description about the analog detection circuit and the logic discrimination circuit in the out-of-lock detection circuit of the present invention, the out-of-lock detection circuit of the present invention can be flexibly arranged according to application scenarios or requirements without being limited to the architecture shown in fig. 3. Which may be comprised of, on the one hand, parts of a modular circuit, such as elements in an electronic circuit. On the other hand, the circuit functions can be realized by replacing hardware with software, that is, by designing a combinational logic circuit, for example, by using a microcomputer or a processor having a signal acquisition function and logic discrimination, that is, by integrating circuit modules such as a digital signal processor, a microcontroller, a memory, a data converter, and an interface circuit on a single chip, the functions of signal acquisition, conversion, storage, processing, and the like can be directly realized.

FIG. 6 is a schematic diagram that schematically illustrates an out-of-lock detection method 600, in accordance with an embodiment of the present invention. It should be noted that the adjusting method 600 may be implemented according to the out-of-lock detection circuit described in fig. 1 to 5. Therefore, the description above in connection with fig. 1 to 5 also applies hereinafter.

As shown in fig. 6, at step S601, an input signal is sampled at a plurality of sampling points having sampling thresholds of different sizes at different phases of the same sampling clock signal to obtain a plurality of sampling results. As indicated previously, the sampling results herein may be obtained by the aforementioned analog detection circuit. For a specific sampling process, reference may be made to the related descriptions in fig. 1 to fig. 5, which will not be described herein again.

Next, at step S602, a plurality of sampling results are received, and whether the sampling clock signal and the input signal are in an out-of-lock state is determined according to a logical relationship between the plurality of sampling results. As indicated above, the out-of-lock condition can be obtained by the logic discrimination circuit described above. For a specific determination process, reference may be made to the related descriptions in fig. 1 to fig. 5, which will not be described herein again.

The lock losing detection circuit and the lock losing detection method can effectively detect the occurrence of the lock losing state, improve the detection effectiveness and reduce the error probability of data transmission. After the further unlocking state occurs, an unlocking state FLAG bit (LOL _ FLAG) can be generated, and meanwhile, the multiplexer is controlled to switch the data access in time, so that the phenomenon that the wrong data rate has larger destructive influence on a subsequent circuit is prevented. Furthermore, the lock loss detection circuit is not limited to a specific circuit structure, so that the design and implementation difficulty of the lock loss detection circuit is greatly simplified, and the flexibility of the circuit structure arrangement is effectively improved.

While various embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that the module compositions, equivalents, or alternatives falling within the scope of these claims be covered thereby.

Claims (6)

1. An out-of-lock detection circuit, comprising:

the analog detection circuit is used for sampling an input signal at a plurality of sampling points with different phases and different sampling thresholds of the same sampling clock signal so as to obtain a plurality of sampling results;

the analog detection circuit comprises a multi-stage clock delay buffer, a pair of first samplers, a pair of second samplers and a counting circuit corresponding to the samplers, wherein the multi-stage clock delay buffer generates a first sampling clock signal which is aligned with the center phase of an input signal, one or more second sampling clock signals which are ahead of the center phase of the input signal and one or more third sampling clock signals which are delayed from the center phase of the input signal; the phase of a sampling clock signal generated by the clock delay buffer is adjustable;

a pair of first samplers are configured to sample the input signal at a second sampling clock signal and a third sampling clock signal, respectively, to obtain corresponding data sampling signals; the pair of second samplers are configured to sample the input signal according to a first sampling threshold value and a second sampling threshold value respectively under a first sampling clock signal to obtain corresponding data sampling signals, wherein the first sampling threshold value and the second sampling threshold value are symmetrical relative to a horizontal axis of the input signal, and a rhombic detection area is formed by sampling points configured by the pair of first samplers and the pair of second samplers;

the counting circuit respectively counts the data sampling signals obtained by the first sampler and the second sampler within preset time to generate four counting results so as to obtain a counting value of a high-level signal or a low-level signal within the preset time as the sampling result;

a logic discrimination circuit which receives the plurality of sampling results and compares the sampling results of the corresponding pairs of samplers pairwise;

and in response to any comparison result exceeding a predetermined deviation, determining whether the sampling clock signal and the input signal are in an out-of-lock state.

2. The out-of-lock detection circuit of claim 1, wherein the analog detection circuit comprises:

a clock delay circuit including a multi-stage clock delay buffer for performing one-stage or multi-stage delay on the sampling clock signal to generate a plurality of sampling clock signals of different phases;

a data sampling circuit comprising a plurality of samplers, each sampler for sampling the input signal at a corresponding one of the sampling points to obtain a corresponding data sampling signal, wherein each sampler configures the corresponding sampling point by receiving one of the different phase sampling clock signals and/or one of the different size sampling thresholds.

3. The loss of lock detection circuit of claim 1, wherein the logic discrimination circuit is further configured to:

judging whether a detection area formed by the plurality of sampling points falls into the center of an eye diagram of the input signal or not according to the logic relation among the plurality of sampling results; and

outputting a signal indicating an out-of-lock condition in response to the detection region being offset from a center of an eye diagram of the input signal.

4. A lock loss detection method is characterized by comprising the following steps:

sampling an input signal at a plurality of sampling points with different phases and different sampling thresholds of the same sampling clock signal to obtain a plurality of sampling results; wherein the different phases of the same sampling clock signal include a first sampling clock signal phase-aligned with the center of the input signal, one or more second sampling clock signals phase-advanced with respect to the center of the input signal, and one or more third sampling clock signals phase-delayed with respect to the center of the input signal; wherein the phase of the generated sampling clock signal is adjustable;

sampling the input signal under a second sampling clock signal and a third sampling clock signal respectively to obtain corresponding data sampling signals; under a first sampling clock signal, sampling the input signal according to a first sampling threshold and a second sampling threshold respectively to obtain corresponding data sampling signals, wherein the first sampling threshold and the second sampling threshold are symmetrical relative to a horizontal axis of the input signal, and a rhombic detection area is formed by sampling points configured by a pair of first samplers and a pair of second samplers;

counting the data sampling signals obtained at the four sampling points in a preset time respectively to generate four counting results so as to obtain a counting value of a high-level signal or a low-level signal in the preset time as the sampling result;

receiving the plurality of sampling results, and comparing the sampling results of the corresponding pairs of samplers pairwise;

and in response to any comparison result exceeding a predetermined deviation, determining whether the sampling clock signal and the input signal are in an out-of-lock state.

5. The out-of-lock detection method of claim 4, wherein sampling the input signal at a plurality of sampling points having different sampling thresholds of different magnitudes and different phases of the same sampling clock signal to obtain a plurality of sampling results comprises:

delaying the sampling clock signal by one or more stages to generate a plurality of sampling clock signals of different phases; and

sampling the input signal at a corresponding one of the sampling points to obtain a corresponding data sampling signal, wherein each of the sampling points is configured by one of the sampling clock signals of the different phases and/or one of the sampling thresholds of the different sizes.

6. The method of claim 4, wherein determining whether the sampling clock signal and the input signal are in an out-of-lock state according to a logical relationship between the plurality of sampling results comprises:

judging whether a detection area formed by the plurality of sampling points falls into the center of an eye diagram of the input signal or not according to the logic relation among the plurality of sampling results; and

outputting a signal indicating an out-of-lock condition in response to the detection region being offset from a center of an eye diagram of the input signal.

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