CN105468561A - High-speed asynchronous serial communication method - Google Patents
High-speed asynchronous serial communication method Download PDFInfo
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- CN105468561A CN105468561A CN201410398174.8A CN201410398174A CN105468561A CN 105468561 A CN105468561 A CN 105468561A CN 201410398174 A CN201410398174 A CN 201410398174A CN 105468561 A CN105468561 A CN 105468561A
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Abstract
The invention discloses a high-speed asynchronous serial communication method. The method comprises the following processing steps of: inputting a high-speed serial signal, performing over-sampling on the input serial signal, sending the sampled data to a data determination recovery module, detecting whether data redundancy or missing exists in the currently input sampled data through the data determination recovery module according to a phase relationship between former output data and clocks, performing operation of redundant data removal, missed data recovery or normal data determination, updating a phase relationship between current output data and clocks, inputting the determined valid data to a data alignment and series-parallel conversion operation module for performing the data frame format alignment operation according to a data communication protocol, and outputting the valid data. Circuit modules related to the method comprise a data sampling module, the data determination recovery module and the data alignment and series parallel conversion operation module. The method belongs to the field of communication; and through adoption of the method, the data sampling error rate caused by clock or signal jittering in a high-speed serial transmission communication system is reduced, the implementation method is simple and the system is reliable.
Description
Technical field
The present invention relates to the serial transmission communications field, be specifically related to high-speed asynchronous serial data communication system.
Background technology
Along with the development of integrated circuit technique, the requirement of communication system to message transmission rate is more and more higher, and early stage parallel transmission pattern exposes I/O consistency problem gradually due to the lifting of speed and becomes the bottleneck of elevator system transfer rate.Therefore, serial transmission system enjoys deviser to favor.In high speed serial transmission system, the high-speed transfer adopting serioparallel exchange and parallel-serial conversion method to realize data, in transmitting apparatus, exports data and transfer serial data to after coding, export receiving equipment to usually by lower rate parallel; Similarly, in receiving equipment, first sampled data is carried out serioparallel exchange, by parallel low-rate data transmission to subsequent conditioning circuit module.
In serial transmission system, for making receiving equipment can correctly sample input data, sampling clock and data processing become the crucial part of circuit design.Due in actual applications, there is drift and jitter phenomenon in clock signal, such as use error is ± crystal oscillator of 5ppm is as clock source, the time error of walking running one day is (5x24x60x60)/1000000=0.432s, in circuit runs, because clock or signal errors can cause data sampling mistake.For enabling the correct sampled data of receiving end, adopt data clock restoration methods, these method design are complicated more, and cannot solve because clock self is beated drift and the error problem that causes.
Summary of the invention
For reducing or avoiding the data sampling mistake because clock or signal jitter cause, the present invention proposes a kind of High-speed Asynchronous Secial Communication method, can reduce or eliminate sample error.Specific design scheme is described below:
A kind of High-speed Asynchronous Secial Communication method of the present invention comprises: data sampling module, data judging recover module, alignment of data and serioparallel exchange module:
Described data sampling module, carries out with the out of phase over-sampling of frequency and caching original input data, and the sampled data of every phase clock is exported to data judging recovery module, and concrete methods of realizing is as follows:
Utilize phaselocked loop or data clock manager or logical circuit to produce N number of same out of phase sampling clock frequently and be designated as clk1 ~ clkN, as N=2, then the phase differential of clk1 and clk2 is 90 °, when circuit working enable signal is effective, use rising edge and the negative edge sampling input data of clk1 and clk2 simultaneously, export 4 tunnel sampled datas; As N>2, suppose 3≤I≤J≤N, then the phase differential of clock clkI and clkJ is 360 ° of * (J-I)/N; When circuit working enable signal is effective, uses this N number of clock to sample to original input signal, and the sampled data of N number of clock is exported.
Described data judging recovers module and comprises data syn-chronization part and data judging recovered part, is implemented as follows:
Each sampled signal out of phase is synchronized to same clock zone by data syn-chronization part, and each sampled data after synchronous is inputed to data judging recovered part;
Data judging recovered part exports the phase relation of data and output clock according to upper one, judges, if judge present sample data redundancy, abandon present sample data, export without valid data the sampled data after synchronous; If judge there is disappearance in present sample data, increases missing data, exports single-bit missing data and the effective decision data of single-bit simultaneously; Otherwise, export single-bit valid data.
Described alignment of data and serioparallel exchange module comprise serioparallel exchange and alignment of data two parts, are implemented as follows:
Serioparallel exchange part carries out series-parallel operation to input data, and be input as single bit data if current, serioparallel exchange shift register moves 1, to move to left or move to right by circuit design determine, serioparallel exchange counter adds 1; If be input as 2 Bit datas current, serioparallel exchange shift register moves 2, and serioparallel exchange counter adds 2; If without valid data input, serioparallel exchange shift register does not do mobile operation, and serioparallel exchange Counter Value is constant; When a serioparallel exchange has operated, then export serioparallel exchange and operated mark;
Alignment of data part completes data communication frame format detection, if shift register value is the synchronous Key coded signal of data communication frame format, then represent that data are by synchronously, the value of amendment serioparallel exchange part serioparallel exchange counter, the circuit of enable serioparallel exchange part restarts serioparallel exchange work; If serioparallel exchange result is the synchronous commencing signal of data communication frame format, show that valid data frame starts, then start to export serioparallel exchange result; If serioparallel exchange result is the synchronous end signal of data communication frame format, stops exporting serioparallel exchange result, wait for data syn-chronization next time.
Because the present invention is according to the phase relation of previous output data and output clock, sampled data after dynamic judgement current sync, thus carry out deletion redundant data dynamically and increase missing data or normal data decision, every Bit data of serial input is judged, circuit realiration is simple, system stability, ensure that the correctness exporting data.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of High-speed Asynchronous Secial Communication method.
Fig. 2 is data sampling module circuit diagram.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further illustrated.
With reference to Fig. 1, High-speed Asynchronous Secial Communication method comprises: data sampling module, data judging recover module, alignment of data and serioparallel exchange module.
Data sampling module utilizes phaselocked loop or data clock manager or logical circuit to produce N number of same out of phase sampling clock frequently as data sampling clock; When circuit working enable signal is effective, this N number of clock is used to sample to original input signal, and the sampled data of each clock is exported to data judging recovery module, with reference to Fig. 2,2 sampling clock clk1 are adopted in the present embodiment, clk2, uses 4 groups of d type flip flops as input data sampling storage unit.
Data judging recovers module and comprises data syn-chronization part and data judging recovered part, sync section receives the sampled data of data sampling module, and use cross clock domain signal synchronizing method in circuit design from the out of phase sampling data synchronization of frequency extremely local same clock zone, in the present embodiment, to adopt asynchronous FIFO as synchronization mechanism; Data judging recovered part adopts state machine approach in circuit design to realize exporting the judgement of data, and export decision data, in the present embodiment, sampled data has 4 tunnels, and data and the result of determination of sampling are as shown in table 1.
Table 1: data judging method example.
Alignment of data and serioparallel exchange module comprise serioparallel exchange and alignment of data two parts: serioparallel exchange part carries out series-parallel operation to inputting data, and be input as single bit data if current, serioparallel exchange shift register moves 1, and serioparallel exchange counter adds 1; If be input as 2 Bit datas current, serioparallel exchange shift register moves 2, and serioparallel exchange counter adds 2; If without valid data input, serioparallel exchange shift register does not do mobile operation, and serioparallel exchange Counter Value is constant;
Alignment of data part completes data communication frame format detection, if serioparallel exchange result is the synchronous Key coded signal of data communication frame format, then represent that data are by synchronously, the value of amendment serioparallel exchange part serioparallel exchange counter, the circuit of enable serioparallel exchange part restarts serioparallel exchange work; If serioparallel exchange result is the synchronous commencing signal of data communication frame format, show that valid data frame starts, then start to export serioparallel exchange result; If serioparallel exchange result is the synchronous end signal of data communication frame format, stops exporting serioparallel exchange result, wait for data syn-chronization next time.
Claims (4)
1. a High-speed Asynchronous Secial Communication method, is characterized in that, comprising: data sampling module, data judging recover module, alignment of data and serioparallel exchange module:
Described data sampling module, carries out with the out of phase over-sampling of frequency and caching original input data, and the sampled data of every phase clock is exported to data judging recovery module;
Described data judging recovers module, receive heterogeneous sampled data, the phase relation of data and output clock is exported according to upper one, current heterogeneous sampled data is detected, determine whether that redundant data bits and missing data bit occur, carry out corresponding data redundancy removal and recover or normal data decision, export decision data to alignment of data and serioparallel exchange module, and upgrade output data and clock phase relation;
Described alignment of data and serioparallel exchange module, receive decision data, convert data to the parallel data of the equal bit wide with synchronizing signal, and by the parallel data after conversion compared with synchronizing signal, carry out data frame format alignment, output communication agreement valid data.
2. High-speed Asynchronous Secial Communication method according to claim 1, is characterized in that, described data sampling module is implemented as follows:
Utilize phaselocked loop or data clock manager or logical circuit to produce N number of same out of phase sampling clock frequently and be designated as clk1 ~ clkN, as N=2, then the phase differential of clk1 and clk2 is 90 °, when circuit working enable signal is effective, use rising edge and the negative edge sampling input data of clk1 and clk2 simultaneously, export 4 tunnel sampled datas; As N>2, suppose 3≤I≤J≤N, then the phase differential of clock clkI and clkJ is 360 ° of * (J-I)/N; When circuit working enable signal is effective, uses this N number of clock to sample to original input signal, and the sampled data of N number of clock is exported.
3. High-speed Asynchronous Secial Communication method according to claim 1, is characterized in that, described data judging recovers module and comprises data syn-chronization part and data judging recovered part, is implemented as follows:
Each sampled signal out of phase is synchronized to same clock zone by described data syn-chronization part, and each sampled data after synchronous is inputed to data judging recovered part;
Described data judging recovered part exports the phase relation of data and output clock according to upper one, judges, if judge present sample data redundancy, abandon present sample data, export without valid data the sampled data after synchronous; If judge there is disappearance in present sample data, increases missing data, exports single-bit missing data and the effective decision data of single-bit simultaneously; Otherwise, export single-bit valid data.
4. High-speed Asynchronous Secial Communication method according to claim 1, is characterized in that, described alignment of data and serioparallel exchange module comprise serioparallel exchange and alignment of data two parts, are implemented as follows:
Described serioparallel exchange part carries out series-parallel operation to input data, and be input as single bit data if current, serioparallel exchange shift register moves 1, and serioparallel exchange counter adds 1; If be input as 2 Bit datas current, serioparallel exchange shift register moves 2, and serioparallel exchange counter adds 2; If without valid data input, serioparallel exchange shift register does not do mobile operation, and serioparallel exchange Counter Value is constant;
Described alignment of data part completes data communication frame format detection, if serioparallel exchange result is the synchronous Key coded signal of data communication frame format, then represent that data are by synchronously, the value of amendment serioparallel exchange part serioparallel exchange counter, the circuit of enable serioparallel exchange part restarts serioparallel exchange work; If serioparallel exchange result is the synchronous commencing signal of data communication frame format, show that valid data frame starts, then start to export serioparallel exchange result; If serioparallel exchange result is the synchronous end signal of data communication frame format, stops exporting serioparallel exchange result, wait for data syn-chronization next time.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105911348A (en) * | 2016-04-11 | 2016-08-31 | 烽火通信科技股份有限公司 | High speed signal quality test device |
| CN106972916A (en) * | 2017-03-22 | 2017-07-21 | 北京方天长久科技股份有限公司 | One kind is without synchronised clock demblee form serial communication sampling location system of selection |
| CN113364738A (en) * | 2021-05-08 | 2021-09-07 | 武汉中元华电科技股份有限公司 | High-speed FT3 message dynamic self-adaptive receiving method and system based on low-speed clock |
| CN114421957A (en) * | 2022-03-29 | 2022-04-29 | 长芯盛（武汉）科技有限公司 | Lock loss detection circuit and lock loss detection method |
-
2014
- 2014-08-14 CN CN201410398174.8A patent/CN105468561A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105911348A (en) * | 2016-04-11 | 2016-08-31 | 烽火通信科技股份有限公司 | High speed signal quality test device |
| CN106972916A (en) * | 2017-03-22 | 2017-07-21 | 北京方天长久科技股份有限公司 | One kind is without synchronised clock demblee form serial communication sampling location system of selection |
| CN113364738A (en) * | 2021-05-08 | 2021-09-07 | 武汉中元华电科技股份有限公司 | High-speed FT3 message dynamic self-adaptive receiving method and system based on low-speed clock |
| CN114421957A (en) * | 2022-03-29 | 2022-04-29 | 长芯盛（武汉）科技有限公司 | Lock loss detection circuit and lock loss detection method |
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