CN104038215B - A kind of ∑ △ fractional frequencies synthesizer automatic frequency calibration circuit - Google Patents
A kind of ∑ △ fractional frequencies synthesizer automatic frequency calibration circuit Download PDFInfo
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Abstract
It is main to remove 2 comprising one the invention discloses a kind of ∑ △ fractional frequencies synthesizer automatic frequency calibration circuitMFrequency divider, a controlled counter, a comparator and a state machine.It is described to remove 2MThe running of frequency divider control counter, comparator and state machine；Effective counting duration of controlled counter is controlled, for comparator and state machine provide sampling or work clock, and coordinates the sequential relationship between them.Comparator is used for reference clock fREFAnd feedback clock fDIVEnter line frequency to compare.It is thick calibration phase during low level, is thin calibration phase during high level.In thick calibration phase, frequency synthesizer phase-locked loop disconnects, the simulation control end of VCO is connected level, in thick calibration phase, result signals are low level, thus ∑ △ decimals modulator disconnects, and reduce the fractional frequency division of ∑ △ decimals modulator generation than frequency error that part produces to the count value of feedback clock fDIV, and in thin calibration phase, circuit normal operation.
Description
Technical field
The present invention relates to a kind of ∑-△ (sigma-delta) fractional frequency synthesizer automatic frequency calibration circuit, belong to
IC design field.
Background technology
∑-△ fractional frequency synthesizers are the key modules of transceiver radio frequency front end chip, can be various criterion
Transceiver stabilization, programmable, low noise local oscillations clock are provided, its performance is determined or affects whole nothing
The performance of line receive-transmit system.Have that the purity of frequency spectrum is high, working frequency is high because it exports clock, phase noise is low, low in energy consumption, easy
In the advantages of piece is integrated, therefore it is widely used with industrial circle in academia.
As shown in figure 1, be a structured flowchart for typical ∑-△ fractional frequency synthesizers, mainly comprising following
Part：Phase frequency detector, charge pump, loop filter, voltage controlled oscillator (VCO,
VoltageControlOscillator), programmable frequency divider, except 2 frequency dividers, ∑-△ decimals modulator and automatic frequency
Calibration circuit (AFC, Automatic Frequency Calibration).
The effect of each main modular of charge pump phase lock loop frequency synthesizer is briefly described below：
1) phase frequency detector
One input of phase frequency detector is reference clock fREF, another input is to output clock fOUTDivided
Feedback clock f obtained from after frequencyDIV, phase frequency detector enters the ratio of line frequency, phase difference value to reference clock and feedback clock
Compared with, the comparative result of frequency and phase is reflected with the pulsewidth of output signal, that is, produce pulse control signal UP, DOWN.
2) charge pump
Charge or discharge are carried out to electric capacity according to the phase comparative result that phase frequency detector is exported, by pulse control signal
UP, DOWN are converted into current signal Icp, to produce the electricity corresponding with the difference on the frequency of reference clock and feedback clock, phase difference
Pressure.3) loop filter
The current signal I that charge pump is producedcpTo the capacitor charge and discharge in loop filter producing the control of voltage controlled oscillator
Voltage V processedctrl。
4) voltage controlled oscillator
VCO is used to produce the output clock (f of frequency synthesizerOUT).Generally, VCO has digital control end and simulation to control
End.Its frequency of oscillation is by digital control end and analog control voltage VctrlControl.
5) programmable frequency divider
For the output clock of voltage controlled oscillator to be carried out into Fractional-N frequency, because two inputs of phase frequency detector are reference signals
The feedback signal exported with frequency divider, therefore the output of phase frequency detector adjusts voltage controlled oscillator after low pass filter is filtered
Frequency of oscillation, so that the frequency of the output signal of the table frequency divider indirectly.
6) except 2 frequency dividers
Being used to subsequent conditioning circuit such as frequency mixer except 2 frequency dividers are primarily used to form orthogonal I/Q clocks outside phaselocked loop.
7) ∑-△ decimals modulator
On the basis of integral frequency divisioil, ∑-△ decimal modulators are added, entered based on a fixed integral multiple frequency dividing
Row change, exportable fractional frequency division ratio, makes spuious problem be well controlled by randomization frequency dividing ratio in some cycles.Such as
Shown in Fig. 3, the reset termination result signals of ∑-△ decimal modulators, clock end clk meets feedback clock fDIV, input K lead to
Cross spi bus and receive fractional frequency division value.
8) automatic frequency calibration circuit
Using multiband voltage controlled oscillator output frequency when, it is necessary to specifically chosen output band, i.e., first carry out coarse adjustment
Cheng Ranhou carries out thin tuning again.The effect of automatic frequency calibration circuit is exactly the optimum control word for selecting voltage controlled oscillator, it is ensured that
Output frequency tries one's best near the centre frequency of selected frequency band.
Existing automatic frequency calibration circuit is generally based on the automatic frequency calibration circuit for comparing counter type.Such as Fig. 2
It is shown, it is a typical schematic diagram based on the automatic frequency calibration circuit for comparing counter type.Two meters of counter
The sufficiently large number to guarantee to distinguish reference clock and feedback clock that numerical value should be set.Result of the comparison generation UP,
DN signal outputs make state machine saltus step to corresponding frequency band to state machine.
Count value NcntDetermined by following formula：
fVCO=N.FfDIV (2)
fREQ=N.FfREF (3)
F in formulaREFIt is reference clock frequency, therefore (N represents the integer part of frequency dividing ratio, and F represents frequency dividing to be multiplied by frequency dividing ratio N.F
The fractional part of ratio) it is afterwards the target frequency f for needing outputREQ, and fDIVIt is feedback clock frequency, therefore after being multiplied by frequency dividing ratio N.F
That is the frequency f of voltage controlled oscillator outputVCO。fTHIt is the frequency f of voltage controlled oscillator outputVCOWith the target frequency f for needing outputREQ
Difference.NcntIt is a threshold value, when the difference of the counting after comparing by counter is more than this threshold value, state machine will change it
Status word simultaneously repeats above-mentioned comparison procedure until determining optimum control word.The defect of this method is just because NcntValue is one
Individual approximation, thus precision is not enough, and optimal frequency adjustment curve can be not necessarily chosen in frequency calibration procedure.
The content of the invention
Goal of the invention：For the problem and shortage that above-mentioned prior art is present, the invention provides a kind of ∑-△ Fractional Frequencies
Rate synthesizer automatic frequency calibration circuit.
Technical scheme：In order to realize foregoing invention purpose, the present invention discloses proposition kind ∑-△ fractional frequencies synthesizer with certainly
Dynamic frequency calibrates (AFC, Automatic Frequency Calibration) circuit, belongs to IC design field.
∑-△ fractional frequencies synthesizer automatic frequency calibration circuit of the invention includes one except 2MFrequency divider, one
Individual controlled counter, a comparator and a state machine, it is described to remove 2MFrequency divider control counter, comparator and state machine
Running；Except 2MThe input end of clock clk of frequency divider connects the output end of derived reference signal, except 2MFirst output end Qa of frequency divider
The clock signal input terminal clk of comparator is met, except 2MSecond output end Qb of frequency divider connects the clock signal input terminal of state machine
Clk, except 2M3rd output end Qbn of frequency divider receives the input ctrl of control counter, and the input D of controlled counter connects can
The output end of programming frequency division device, the output end Q of controlled counter meets another input D of comparator, and the output end Q of comparator connects
The input D of state machine, the output end rslt output result signals of state machine, while connecing the reset inputs of ∑-△ modulators
End, another output end Q of state machine exports the input that n control word connects voltage controlled oscillator；The reference signal of frequency synthesizer
Source, phase frequency detector, charge pump, loop filter, single-pole double-throw switch (SPDT) SW, voltage controlled oscillator, except 2 frequency divider sequential series connect
Connect；The output end of voltage controlled oscillator is also connected with the input of programmable frequency divider, and the output termination of ∑-△ modulators is programmable
The input of frequency divider.
Described single-pole double-throw switch (SPDT) SW disconnects frequency synthesizer phase-locked loop, voltage controlled oscillator in thick calibration phase
Simulation control end be connected level VDD/2；And thin calibration phase, frequency synthesizer phase-locked loop closure, loop is automatic
Calibrate and operate.
Specifically, effective counting duration of controlled counter is controlled, for comparator and state machine provide sampling or work
Clock, and coordinate the sequential relationship between them；Comparator is used for reference clock fREFAnd feedback clock fDIVEnter line frequency
Compare；State machine module is then on the basis of comparator frequency compares, according to successive approximation algorithm, to produce the frequency control of n
Word processed and result signals：Wherein, n bit digitals control signal is selected by many numerical control ends with voltage controlled oscillator (VCO) of control
Select the frequency band of VCO work；Result signals can be, in thick calibration phase or thin calibration phase, to be during low level with identification circuit
Thick calibration phase, is thin calibration phase during high level；Meanwhile, result signals also control single-pole double-throw switch (SPDT)：By control
Single-pole double-throw switch (SPDT), in thick calibration phase, frequency synthesizer phase-locked loop disconnects, and the simulation control end of VCO is connected electricity
Flat (half of supply voltage), and thin calibration phase, frequency synthesizer phase-locked loop closure, loop are calibrated and operated automatically,
Result signals are also coupled to the reset ends of ∑-△ decimal modulators, and reset ends are reset terminal, it is desirable to have one from low level to
The process of high level could start ∑-△ decimal modulators, and in the thick calibrated stage, result signals are low level, thus ∑-
△ decimals modulator disconnects, and reduces the fractional frequency division of ∑-△ fractional modulations device generation than part to the meter of feedback clock fDIV
The frequency error that numerical value is produced, and in thin calibration phase, circuit normal operation.
It is described except 2MFrequency divider is to input reference clock fREFCarry out 2MDivide again, produce three frequencies to be fREF/2M's
Output clock Qa, Qb and Qbn, wherein, the clock cycle of the advanced Qb1 reference clock fREF of Qa, Qbn is that the logic of Qb is taken
Instead.
Described controlled counter controls end ctrl is connect except 2MThe Qbn ends of frequency divider, data input pin D receives feedback clock
fDIV, output end Q meets the data input pin D of comparator；When controlled counter controls end ctrl is low level, original counting is kept
Value；From low transition be high level when, controlled counter is zeroed out New count of laying equal stress on.
Described comparator clock end clk is connect except 2MThe Qa ends of frequency divider, data input pin D receives the output of control counter
Q, output end Q meet the data input pin D of state machine at end.
Described comparator clk ends clock sampling, latch input terminal D receive data and with fixed value 2M-1It is compared,
Comparative result is exported by output end Q.
Described state machine clock end clk is connect except 2MThe Qb ends of frequency divider, input D meets the output end Q of comparator, resets
Port rst meets external reset signal reset, and output end rslt output signal result, output end Q connect the numeral of voltage controlled oscillator
Control end.
Described state machine input D meets the output end Q of comparator, on the basis of comparator frequency compares according to by
Secondary approximate algorithm, produces the frequency control word and result signals of n, the frequency control word of n to be exported by output end Q,
Result signals are exported by output end rslt.
It is described except 2 based on the basic structure of ∑-△ fractional frequency synthesizersMThe input termination reference clock of counter
fREF, its output end Qa connects the clock end of comparator, and output end Qb connects the clock end of state machine, and output end Qbn receives control and counts
The modulus that device is counted as it.The input of described controlled counter meets feedback clock fDIV, its output termination comparator
Input.The input of the output termination state machine of described comparator.Reset signals are the control of automatic frequency calibration circuit
Port.The output end output result signals of state machine, for controlling single-pole double-throw switch (SPDT) SW, and result signals to be also coupled to
The reset ends of ∑-△ decimal modulators, in the thick calibrated stage, disconnect ∑-△ decimal modulators, to reduce the modulation of ∑-△ decimals
The fractional frequency division that device is produced is than part to feedback clock fDIVCount value produce frequency error, in addition export a multidigit frequently
Rate control word signal controls the voltage controlled oscillator of many bands.
∑-△ fractional frequencies synthesizer experiences two processes from tracking state to lock-out state altogether.First, thick calibration phase.
Size according to output target frequency is automatically selected four control words of voltage controlled oscillator by automatic frequency calibration circuit, selection
Standard is that target frequency should try one's best and be most in close proximity to supply voltage VDD at last in the center of selected subband, i.e. control voltage
Half, i.e. VDD/2.This control word is kept until loop-locking.2nd, thin calibration phase.During this process, voltage controlled oscillator
Change the size of variable capacitance thereon, finally obtain target frequency, and its control voltage is fixed in certain determination value,
It is now usually said loop-locking.Experience the two processes until loop finally lock, a usual excellent in design from
Dynamic frequency calibration circuit is substantially shorter the loop-locking time.Can be by single-pole double throw between thick calibration phase and thin calibrated stage
Switch SW is switched over, and the time point control signal of switching is controlled by the result signals that automatic frequency calibration circuit is exported.
The present invention is described except 2 based on comparing counter typeMCounter and controlled counter connect reference clock respectively
fREFAnd feedback clock fDIV, reference clock and feedback clock are two input clocks that automatic calibration frequency module is used to compare,
Reset signals are the control port of automatic frequency calibration circuit, when reset signals are when logic low is changed into logically high, automatic frequency
Rate calibration circuit is started working, and after calibration is completed, can enter stable state, and voltage controlled oscillator is adjusted by one group of Optimal Control word
Humorous, now single-pole double-throw switch (SPDT) SW connects loop filter end, and phase-locked loop carries out frequency lock procedure, and final loop exports certain
One target frequency value.
Beneficial effect：A kind of ∑-△ fractional frequency synthesizers automatic frequency calibration circuit reliability of present invention design
And traditional high based on the automatic frequency calibration circuit for comparing counter type of ratio of precision, simultaneously as simple structure, is conducive to
Reduce circuit layout area and time cost.
Brief description of the drawings
Fig. 1 is the structured flowchart of ∑-△ fractional frequency synthesizers,
Fig. 2 is a typical schematic diagram based on the automatic frequency calibration circuit for comparing counter type,
Fig. 3 is a kind of ∑-△ fractional frequencies synthesizer automatic frequency calibration circuit proposed by the present invention,
Fig. 4 is the workflow of automatic frequency calibration circuit,
Fig. 5 is by except 2MOutput signal timing diagram after counter,
Fig. 6 is the successive approximation algorithm (4) that state machine is used,
Fig. 7 is the Transient of automatic frequency calibration circuit,
Fig. 8 is the Transient of ∑-△ fractional frequency synthesizers.
Specific embodiment
For the technological means for further illustrating where advantage of the invention and specifically take, below in conjunction with accompanying drawing to this
The specific embodiment of invention is described in further detail.
Fig. 1-Fig. 2 is the introduction of existing background technology, is repeated no more.
As shown in figure 3, a kind of ∑-△ fractional frequency synthesizers automatic frequency calibration circuit bag provided by the present invention
Include：One is removed 2MCounter, a controlled counter, a comparator, a state machine.Wherein, it is described except 2MFrequency divider
Input termination reference clock fREF, its output end Qa connects the clock end of comparator, and output end Qb connects the clock end of state machine, defeated
Go out to hold Qbn to receive the modulus that control counter is counted as it.The input of described controlled counter meets feedback clock fDIV, it
Output termination comparator input.The input of the output termination state machine of described comparator.Reset signals are automatic
The control port of frequency calibration circuit.The output end output result signals of state machine, for controlling single-pole double-throw switch (SPDT) SW, and
And result signals are also coupled to the reset ends of ∑-△ decimal modulators, a multidigit frequency control word signal control is exported in addition
The voltage controlled oscillator of many bands.
It is described except 2MFrequency divider is used for reference clock fREFCounted, its output signal Qa uses edging trigger,
It is the clock for being deposited count results, is deposited in the rising edge of clock；Its output signal Qb uses edging trigger, is shape
The clock of state machine work, the half period that its output signal Qbn is formed is effective counting duration of controlled counter.Described
Controlled counter is used for feedback clock fDIVCounted.Described comparator is used for comparison reference clock fREFWith feedback clock
fDIV2M-1Individual reference clock fREFComparative result in cycle, and for the State Transferring of state of a control machine.Described state machine
Using successive approximation algorithm, for exporting result signals and the frequency control word of n.
As shown in figure 4, being the workflow of automatic frequency calibration circuit.After upper electricity, single-pole double-throw switch (SPDT) SW connections are solid
Determine level VDD/2, that is, voltage controlled oscillator accesses fixed level VDD/2, the initial control word of voltage controlled oscillator is set to 0000
(as a example by 4).Then reset signals are set to logic high, the highest order of voltage controlled oscillator is set to 1, now compares
It is two input clocks：Reference clock fREF, feedback clock fDIVSize, reference clock fREFIt is fixed value, and feedback clock
The value of fDIV is unknown.By reference clock fREFBy except 2MFrequency divider, that is, the clock cycle after dividing is T=2M(1/fREF), half
Feedback clock fDIV is counted in the individual T cycles, ideal value should be MDIV=(T/2)/(1/fDIV)=2M-1(fDIV/fREF),
So to reference clock f within the same timeREFCounted, ideal value should be MREF=2M-1.So working as MDIV>MREFWhen,
Can determine whether fDIV>fREF, while it is 0 to put the control bit, and work as MDIV<MREFWhen, can determine whether fDIV<fREF, while put the control bit being
1.Finally judge whether the position is lowest order, if it is not, then be compared into next bit, if the position is lowest order, i.e.,
Frequency calibration is completed, into the Frequency Locking stage.
If Fig. 5 is by except 2MOutput clock timing diagram after frequency divider.Reference clock fREFBy except 2MIt is defeated after frequency divider
Go out three signals：Qa, Qb and Qbn, their cycle are reference clock fREFThe 2 of cycleMTimes.Qbn controls controlled counting in figure
The working condition of device, when it is converted to high level, controlled counter is zeroed out New count of laying equal stress on；During low level, keep original
Count value.Qa provides the input sample clock of comparator, and rising edge sampling deposit.Qb provides work clock for state machine.By
Figure is visible, and the t1 moment starts to feedback clock fDIVCount, the t2 moment gets up controlled rolling counters forward result register, during t3
Quarter carries out data comparing, while by counter O reset.T1 and t2 time at intervals 2M- 1 reference clock fREFClock cycle, and
T2 and 1 reference clock f of t3 time at intervalsREFClock cycle.
Due to the randomization frequency dividing ratio that ∑-△ fractional modulations device is introduced, the fractional part of frequency dividing ratio causes feedback clock
Count values of the fDIV within half T cycle may be MMIS=2M-1(fDIV/fREF)±1.If f (M)=MMIS-MREF, f (M) can be obtained
=2M-1(fDIV/fREF)±1-2M-1, it is assumed that f (M)>0, fDIV can be obtained>[1±(1/2M-1)]·fREF, now frequency error be
fREF/2M-1If the frequency dividing ratio of programmable frequency divider is N, then frequency error is reflected into the output of voltage controlled oscillator and is exaggerated N
Times, the selection mistake of frequency control word is possibly even caused when serious.In order that frequency error does not influence the choosing of frequency control word
Select, result signals are connected to the reset ends of ∑-△ decimal modulators, reset ends are reset terminal, it is desirable to have one from low electricity
Equalling the process of high level could start ∑-△ decimal modulators, and in the thick calibrated stage, result signals are low level, therefore
∑-△ fractional modulations device disconnects, and fractional frequency division will not be to feedback clock f than partDIVCount value produce influence, reduce frequency
Rate error.
As shown in fig. 6, be the successive approximation algorithm of state machine use, here by taking 4 bit frequency control words as an example.With it is traditional
Binary logic method is compared, and can quickly get Optimal Control word, and importantly, make the degree of accuracy in this way
It is greatly improved.
As shown in fig. 7, being the Transient of automatic frequency calibration circuit.Automatic frequency is expressed as in figure from top to bottom
Calibrate the lowest order D1 of 4 bit frequency control words of the result signals and output of circuit output, secondary the D2, secondary high-order D3,
Highest order D4.As can be seen, 4 state changes of control word be 1000 (by high-order to low level sequence, similarly hereinafter), 1100,1010,
1001, and finally stablize the state 1001, i.e., compare by 4 times, have selected an Optimal Control word 1001, state transition mistake
Cheng Fuhe Fig. 6.
As shown in figure 8, being the Transient of ∑-△ fractional frequency synthesizers.It is expressed as from top to bottom in figure automatic
The result signals of frequency calibration circuit output and the control voltage Vctrl of voltage controlled oscillator.As seen from the figure, at when loop starts
In automatic frequency calibration phase, now result signals holding logic low, the control voltage on voltage controlled oscillator is precharged to
The half (i.e. 0.9V) of supply voltage, after after the determination of optimal frequency control word, now result signals are changed into logically high, at loop
In Frequency Locking stage, the now saltus step since 0.9V of the control voltage on voltage controlled oscillator, until final stabilization is connecing very much
It is bordering on the position of the half VDD/2 (i.e. 0.9V) of supply voltage.
In sum, a kind of ∑-△ fractional frequencies synthesizer that the present invention is provided passes through two with automatic frequency calibration circuit
Individual counter is respectively to reference clock fREFAnd feedback clock fDIVCounted, result of the comparison be deposited at data register,
And in the State Transferring of state of a control machine, using successive approximation algorithm final output optimum control word to voltage controlled oscillator.
The above is only example of the invention, do not constitute any limitation of the invention, it is clear that under thought of the invention,
Any those skilled in the art, are not departing from the range of technical scheme, using the technology of the disclosure above
Content carries out suitably adjusting or optimizing to circuit structure and component size, refers to above example according to technology of the invention
Any simple modification, equivalents and the modification made, belong to the scope of technical solution of the present invention.
Claims (1)
1. a kind of ∑-Δ fractional frequency synthesizer automatic frequency calibration circuit, it is characterised in that：The circuit includes one and removes
2MFrequency divider, a controlled counter, a comparator and a state machine, it is described to remove 2MFrequency divider control counter, compare
The running of device and state machine；Except 2MThe input end of clock clk of frequency divider connects the output end of derived reference signal, except 2MThe of frequency divider
One output end Qa meets the clock signal input terminal clk of comparator, except 2MSecond output end Qb of frequency divider connects the clock of state machine
Signal input part clk, except 2M3rd output end Qbn of frequency divider receives the input ctrl of control counter, controlled counter
Input D connects the output end of programmable frequency divider, and the output end Q of controlled counter meets another input D of comparator, comparator
Output end Q meet the input D of state machine, the output end rslt output result signals of state machine, while connecing sigma-delta modulator
Reset inputs, another output end Q of state machine exports the input that n control word connects voltage controlled oscillator；Frequency synthesizer
Derived reference signal, phase frequency detector, charge pump, loop filter, single-pole double-throw switch (SPDT) SW, voltage controlled oscillator, except 2 frequency dividers
Sequential series are connected；The output end of voltage controlled oscillator is also connected with the input of programmable frequency divider, the output of sigma-delta modulator
The input of programmable frequency divider is terminated, described single-pole double-throw switch (SPDT) SW disconnects frequency synthesizer lock phase in thick calibration phase
Loop back path, the simulation control end of voltage controlled oscillator is connected level VDD/2；And thin calibration phase, frequency synthesizer phaselocked loop
Circuit closed, loop is calibrated and operated automatically.
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| GB2533556A (en) * | 2014-12-16 | 2016-06-29 | Nordic Semiconductor Asa | Oscillator calibration |
| CN104467826B (en) * | 2014-12-18 | 2018-01-30 | 中国电子科技集团公司第五十四研究所 | A kind of △ ∑ fractional frequency synthesizers of the jittered shaping of band |
| CN105187056B (en) * | 2015-09-06 | 2019-02-26 | 四川九洲电器集团有限责任公司 | A kind of clock signal generating device and clock signal creating method |
| CN105577178B (en) * | 2015-12-11 | 2018-12-25 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of broadband low phase noise Sigma-Delta phaselocked loop |
| CN106656173B (en) * | 2016-12-26 | 2020-01-24 | 上海迦美信芯通讯技术有限公司 | Frequency calibration circuit of oscillator and frequency calibration method thereof |
| CN108183707A (en) * | 2018-02-07 | 2018-06-19 | 广州市广晟微电子有限公司 | A kind of low noise automatic frequency control apparatus and its control method |
| CN110113048A (en) * | 2019-05-17 | 2019-08-09 | 芯翼信息科技(南京)有限公司 | Clock calibration circuit and clock correcting method based on phaselocked loop |
| CN112134560B (en) * | 2020-09-30 | 2023-01-24 | 中国科学院微电子研究所 | Low noise frequency synthesizer device |
| CN113541683B (en) * | 2021-06-08 | 2022-11-25 | 西安电子科技大学 | Phase-locked loop automatic frequency calibrator based on programmable three-frequency divider |
| CN116505938B (en) * | 2023-06-16 | 2023-09-08 | 核芯互联科技(青岛)有限公司 | Phase locked loop |
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