CN206060728U - A kind of fast automatic frequency calibration circuit for RF Phase-Lock Loop - Google Patents

Abstract

This utility model is related to a kind of fast automatic frequency calibration circuit for RF Phase-Lock Loop, can make larger output bandwidth is covered under the conditions of relatively low voltage controlled gain using the RF Phase-Lock Loop of this circuit, be provided simultaneously with lock speed faster.This circuit adopts quasi- closed-loop structure, including voltage comparator, a pulse generator and a counter module, with simple structure, lock speed is fast the characteristics of.Counter module further shorten the phase-locked loop frequency coarse adjustment time using binary chop and carry lookahead adder, so as to accelerate locking process.

Description

A kind of fast automatic frequency calibration circuit for RF Phase-Lock Loop

Technical field

This utility model be related to one kind be applied to RF Phase-Lock Loop (Phase Locked Loop, abbreviation PLL) it is quick from Dynamic frequency calibrates (Auto Frequency Calibration, abbreviation AFC) circuit.

Background technology

PLL is an important module in radio frequency sending and receiving chip, and its noiseproof feature directly influences communication quality.It is voltage-controlled to shake Device (VCO) is swung as the nucleus module of PLL, have conclusive impact to the reference frequency output and phase noise performance of PLL.For VCO of the design with broad tuning scope, a kind of method are to increase the voltage controlled gain K of VCO_vco, but this mode significantly can deteriorate Phase noise performance；Another kind of method is to replace fixed capacity with switched capacitor array, takes into account broad tuning scope and low phase position is made an uproar The requirement of sound.Due to adding capacitor array, the bandwidth of VCO is divided for many single frequency sub-band, in every height frequency Slightly change frequency of oscillation by adjusting the capacitance of varactor in section.When the extraneous frequency dividing for producing interference or phaselocked loop During than changing, needing AFC circuit to produce capacitor array control word to select capacitor array, allowing VCO to be operated in suitable frequency sub-band. Meanwhile, communication ageing and require that phaselocked loop has a lock speed faster, therefore research is capable of the low phase position of quick lock in and is made an uproar Sound PLL has very important significance.The locking time of PLL includes frequency rough regulating time and frequency fine regulating time two Point.Frequency rough regulating time can be reduced using quick AFC circuit, so as to accelerate the lock speed of PLL.

Existing AFC mainly has two kinds of structures of open loop and closed loop.In closed-loop structure, each AFC's is relatively required in tuning Voltage V_ctrlCan just carry out after stable, thus locking time is longer.In open loop structure, AFC carries out PLL open circuits, V during choosing band_ctrl It is connected on a reference voltage (typically supply voltage half), VCO output frequencies enter rolling counters forward after Fractional-N frequency, With reference to frequency signal f_refAlso into enumerator, the enumerator incoming frequency first overflowed is high, so as to adjust the control of electric capacity permutation Word.Due to the initial phase of enumerator input signal it is not necessarily identical, in order to ensure calibrate precision, it is desirable to enumerator has enough High digit, but too high number of counter bits can reduce the speed of AFC calibrations, extend the locking time of PLL.

Utility model content

This utility model is in order to overcome the slow-footed problems of existing AFC, there is provided it is a kind of for RF Phase-Lock Loop it is quick from Dynamic frequency calibrates circuit.

What above-mentioned technical problem of the present utility model was mainly addressed by following technical proposals：

A kind of fast automatic band calibration circuit for RF Phase-Lock Loop, using quasi- closed-loop structure, including being sequentially connected Voltage comparator, pulse generator and counter module；The counter module includes that 5 four tunnels being sequentially connected select Device, 5 carry lookahead adders, 5 two-way selectores one, 5 bit registers and 5 two-way selectores two；5 four tunnels Two inputs of selector connect two 5 bit shift registers respectively, are that 5 bit shift registers S1 and 5 bit shifts are posted respectively Storage S2；5 two-way selectores one are also connected with 5 bit registers and 5 two-way selectores two respectively；5 displacement Bit register S1 is used as addition shift register, deposits the true form of addend；The 5 bit shift register S2 shift LDs that subtract Device, deposits the complement code of subtrahend；After comparison procedure, addition shift register moves to right one every time, and highest is shifted into 0, realizes true form The function of halving；Subtraction shift register moves to right one, and highest is shifted into 1, realizes the function that complement code halves.

In a kind of above-mentioned fast automatic band calibration circuit for RF Phase-Lock Loop, 5 carry lookahead adders Device can carry out additive operation and can carry out subtraction again, and wherein subtraction is realized by the complement code plus subtrahend.In conversion process, Adder is determined according to the result of voltage comparison procedure carries out addition or subtraction.During additive operation, VHO gates four routings The C of device<4:0>End, plus the true form input carry lookahead adder deposited in counter/shift register.During subtraction, VLO choosings Lead to the A of four selector switches<4:0>End, the complement code input carry lookahead adder deposited in subtracting counter/shift register.Enter in advance Position adder has obvious speed advantage compared with normal full adder, it is possible to increase AFC circuit selects tape speed

This utility model employs new quasi- closed-loop structure, and circuit structure is simple；It is optimum by binary chop search Capacitor array control word, effectively reduces number of comparisons, and then shortens PLL frequency rough regulating times；Employing in counter module Carry lookahead adder, faster, further shortens locking time than traditional serial adder speed；Counter module is by mending Code carries out subtracting counting, reduces hardware complexity.

Description of the drawings

Fig. 1 is the AFC circuit system block diagram involved by this utility model.

Fig. 2 is the AFC circuit workflow diagram involved by this utility model.

Fig. 3 is the counter module structure chart involved by this utility model.

Specific embodiment：

Fig. 1 is AFC circuit system block diagram, including voltage comparator, three parts of pulse generator and counter module.Electricity Pressure comparator VL ends and VH ends are respectively by outside input reference voltage lower limit (0.5V) and the reference voltage upper limit (1.4V)；Input Vt connects the input of VCO, control voltage of its input value for VCO；Outfan VHI connects the IN1 ends of pulse generator, works as V_t>V_HWhen Output high level；Outfan VLI connects the IN2 ends of pulse generator, works as V_t<V_LWhen export high level.The input of pulse generator IN1, IN2 connect VHI the and VLI ends of voltage comparator respectively；Outfan Out1 and Out2 connect respectively counter module Cnt+ and Cnt-；SW1 terminates the SW2 ends of counter module；CLK is terminated into external timing signal.Counter module input Cnt+ and Cnt- meets the Out1 and Out2 of pulse generator respectively；SW2 terminates the SW1 ends of pulse generator；Outfan Out connects capacitor array Controlling switch, its output valve B<4:0>For five capacitor array control words, initial value is " 10000 "；CLK clock signals are by outer Access in portion.

Fig. 2 is AFC circuit workflow diagram, and the course of work includes：Initialization procedure, voltage comparison procedure and transformed Journey.Initialization procedure disconnects phase-locked loop, while voltage controlled oscillator control voltage Vt to be set to half (this electricity of supply voltage Lu Zhongwei 0.9V), capacitor array control word B<4:0>It is set to " 10000 ", plus counter/shift register initial value C_ount+<4:0> For " 01000 ", subtract counter/shift register initial value C_ount-<4:0>For " 11000 ".Voltage comparison procedure closes phase-locked loop, V_tWith reference voltage lower limit V_LWith upper limit V_HIt is compared (in this circuit, be respectively 0.5V and 1.4V).Work as V_t>V_HWhen, voltage ratio compared with Device VHI ends export high level, VLI ends output low level, pulse generator VHO ends and the of short duration high level pulse of Sw ends generation；When V_t<V_LWhen, voltage comparator VLI ends output high level, VHI ends export low level, and pulse generator VLO ends and the generation of Sw ends are short Temporary high level pulse；Work as V_L<V_t<V_HWhen, VHI and VLI exports low level, and pulse generator is without output.In conversion process, VHO The pulse gate counter module at end plus counting channel so that B<4:0>Increase C_ount+<4:0>；The pulse gate meter at VLO ends Count device module subtracts counting channel so that B<4:0>Increase C_ount-<4:0>.The pulse at Sw ends is used for V_tIt is again set at Two shift registers in 0.9V, and flip-flop number module move to right one, so as to reach C_ount+<4:0>And C_ount-<4:0> The purpose for halving, then carries out the voltage comparison procedure of next round.Voltage comparison procedure and conversion process will alternately until V_L<V_t<V_H, VHI and VLI exports low level, B now<4:0>It is exactly suitable value.

Fig. 3 is the counter module structure chart in AFC circuit, including 5 carry lookahead adders, and one 5 are posted Storage, one 5 No. four selectores, two 5 two-way selectores and two shift registers, wherein S1 are to subtract counting displacement to post Storage, S2 are to add counter/shift register.The D1 ports of S1 connect high level, and CLK1 connects the SW1 ends of pulse generator, whenever SW1 When there is high level pulse in end, data Count- in S1<4:0>One is moved to right, highest is shifted into " 1 ", outfan Q1<4:0> Meet the A of 5 No. four selectores<4：0>End.The D2 ports of S2 connect low level, and CLK2 connects the SW1 ends of pulse generator, whenever SW1 When there is high level pulse in end, data Count+ in S2<4:0>One is moved to right, highest is shifted into " 0 ", outfan Q2<4:0> Meet the C of 5 No. four selectores<4：0>End.The A of 5 No. four selectores<4:0>And C<4:0>The Q1 of S1 is met respectively<4:0>And S2 Q2<4:0>, B<4:0>And D<4:0>Do not connect, a1 and a2 ports meet VHO the and VLO ports of pulse generator, Y respectively<4:0> Meet the B of 5 carry lookahead adders<4:0>, the C when high level occurs in a1<4:0>It is strobed into Y<4：0>Output, when a2 occurs A during high level<4:0>It is strobed into Y<4：0>Output.5 carry lookahead adder A<4：0>End and the A of 5 two-way selectores 1 <4:0>End, 5 bit register SN<4:0>End and Q<4:0>End, 5 two-way selector 2B<4：0>End is connected；5 carry look aheads add Musical instruments used in a Buddhist or Taoist mass B<4:0>End and 5 No. four selector Y<4:0>End is connected；Input carry end CI connects low level；Output carry end CO is not Connect；5 carry lookahead adder outfan Y<4:0>Meet the B of 5 two-way selectores 1<4:0>End.The A of 5 two-way selectores 1< 4:0>End and 5 carry lookahead adder A<4：0>End, 5 bit register SN<4:0>End and Q<4:0>End, 5 two-way selectores 2B<4：0>End is connected；The B of 5 two-way selectores 1<4:0>5 carry lookahead adder outfan Y of termination<4:0>；5 two-ways The outfan Y of selector 1<4:0>Meet 5 bit register A<4:0>End；A termination external circuit input control signals 1.5 bit registers SN<4:0>The A of 5 two-way selectores 1 of termination<4:0>End, 5 carry lookahead adder A<4：0>End, 5 bit register Q<4:0> End, 5 two-way selector 2B<4：0>End；5 bit register A<4:0>The outfan Y of 5 two-way selectores 1 of termination<4:0>；CLK End is input into through a phase inverter by external timing signal；Reset<4:0>Hold by outside input, for by the beginning of 5 bit registers Initial value is set to " 10000 "；Outfan Q<4:0>Meet 5 carry lookahead adder A<4：0>End, the A of 5 two-way selectores 1< 4:0>End, 5 bit register SN<4:0>End, 5 two-way selector 2B<4：0>.5 two-way selector 2A<4：0>End is connect by outside Enter Carry_In<4:0>, value is " 10000 "；5 two-way selector 2B<4：0>5 carry lookahead adder A of termination<4：0> End, the A of 5 two-way selectores 1<4:0>End, 5 bit register SN<4:0>End and Q<4:0>End；B termination external circuit input controls Signal processed 2；5 two-way selector 2Y<4:0>End is connected with capacitor array controlling switch, output valve B<4:0>For capacitor array control Word processed.

Gating signals of the output VHO and VLO of pulse generator as No. four selectores, when VLO has pulse to export, S1 It is strobed, C_ount-<4:0>5 carry lookahead adders of input；S2 gatings, C when VHO has pulse to export_ount+<4:0>Input 5 Position carry lookahead adder；Without output, VHO and VLO show that AFC has found suitable capacitor array control word.Pulses generation CLK end clock signal of the Sw signals of device SW1 ends output as two shift registers, whenever high level arteries and veins occur in SW1 ports Rush data shift right one.The C stored in S1_ount-<4:0>It is initialized as " 11000 ", input termination high level is shifted most every time High-order input 1；The C stored in S2_ount+<4:0>It is initialized as " 01000 ", input termination low level, displacement highest order is defeated every time Enter 0.Per right shift once, the data in S1, S2 halve, so as to the optimum capacitance antenna array control word region of search is reduced by half.Meter The subtraction function of number device module is realized by complement code.Such as capacitor array control word needs to reduce eight, then by adding Realizing, displacement every time obtains 11100,11110 and 11111 from high-order input 1 to upper eight complement code 11000 successively, be respectively- 4, -2 and -1 complement code.The addition function of counter module is realized by true form.For example capacitor array control word needs increase by eight Position, then by the true form 01000 plus eight, displacement every time obtains 00100,00010 and 00001 successively from high-order input 0, point It is not 4,2,1 true form.

Specific embodiment described herein is only explanation for example to this utility model spirit.This utility model institute Category those skilled in the art can make various modifications or supplement or using similar to described specific embodiment Mode substitute, but without departing from it is of the present utility model spirit or surmount scope defined in appended claims.

Claims (1)

1. a kind of fast automatic frequency calibration circuit for RF Phase-Lock Loop, it is characterised in that：Using quasi- closed-loop structure, including Voltage comparator, pulse generator and the counter module being sequentially connected；The counter module includes 5 four for being sequentially connected Road selector, 5 carry lookahead adders, 5 two-way selectores one, 5 bit registers and 5 two-way selectores two；Described 5 Two inputs of position No. four selectores connect two 5 bit shift registers respectively, are 5 bit shift registers S1 and 5 respectively Shift register S2；5 two-way selectores one are also connected with 5 bit registers and 5 two-way selectores two respectively；It is described 5 bit shift registers S1 are used as addition shift register, deposit the true form of addend；The displacement that subtracts of 5 bit shift registers S2 Depositor, deposits the complement code of subtrahend；After comparison procedure, addition shift register moves to right one every time, and highest is shifted into 0, realizes The function that true form halves；Subtraction shift register moves to right one, and highest is shifted into 1, realizes the function that complement code halves.