CN108063618A - A kind of VCO auto-calibration circuits and method - Google Patents
A kind of VCO auto-calibration circuits and method Download PDFInfo
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- CN108063618A CN108063618A CN201711387872.8A CN201711387872A CN108063618A CN 108063618 A CN108063618 A CN 108063618A CN 201711387872 A CN201711387872 A CN 201711387872A CN 108063618 A CN108063618 A CN 108063618A
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- clock counter
- feedback
- state machine
- voltage controlled
- reference clock
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of VCO auto-calibration circuits, including reference clock counter, feedback clock counter, state machine, voltage controlled oscillator, frequency divider and reseting module, reference clock counter, feedback clock counter, reseting module and voltage controlled oscillator are connected with state machine, and reseting module, voltage controlled oscillator and feedback clock counter are connected with frequency divider；State machine is in reset state by reference clock counter, feedback clock counter resets, and make reseting module by divider reset, reference clock counter and feedback clock counter is made to count simultaneously, the feedback count value value that feedback counter obtains is recorded when reference clock counter counts count to pre-set count values, finds the optimal capacitance array of values of voltage controlled oscillator by dichotomy according to the comparative result of pre-set count values and feedback count value.Not the problem of not known this invention removes feedback clock initial phase so as to reduce count accuracy；The time calibrated automatically can be shortened.
Description
Technical field
The invention belongs to IC design technical field more particularly to a kind of VCO auto-calibration circuits and methods.
Background technology
At present, modern communication technology is maked rapid progress, and various wireless communication standards emerge in an endless stream.In the reception and transmitting of signal
In, frequency synthesizer is an important module, for generating stable, accurate, low noise local oscillation signal, realizes and receive (hair
Penetrate) mixing of signal.To realize larger signal bandwidth, it is necessary to which local oscillation signal covers very big scope.It is generated for local oscillator
Voltage controlled oscillator (VCO) generally uses capacitor and inductor resonance structure, and this structure can obtain being much better than the noiseproof feature that ring shakes.It shakes
The control voltage of device is swung by the way that the capacitance of varactor is controlled to adjust the frequency of output.Capacitance is bigger, and output frequency is lower, capacitance
Smaller output frequency is higher.Frequency variation is known as voltage controlled gain compared with the variation of control voltage, as shown in Figure 2.Voltage controlled gain
Mean that identical control voltage change can obtain the output frequency variation of bigger more greatly.
The achievable frequency range of varactor is smaller, while big voltage controlled gain can deteriorate the performances such as noise, spuious.
So general add a switched capacitor array in circuit, when switching Close All, capacitance is disconnected from the circuit, capacitance
Array total capacitance is 0.The switch of opening is more, and the capacitance of capacitor array is bigger.Capacitor array takes different capacitances, cooperation
The variation of varactor capacitance value can realize a larger reference frequency output.This method requirement adjacent capacitor array is defeated
Certain overlapping must be had by going out frequency range, just can guarantee that covering frequency range is continuous；Secondly in required frequency shift, circuit should be able to be certainly
It is dynamic to find suitable capacitor array value.
Finding automatic frequency calibration (AFC) method of appropriate capacitor array mainly has open loop counter, switch analogy method
It is several with closed loop locking means etc..The time that closed loop locking means need is very long, open loop analogy method due to device mismatch and
Comparator imbalance affects accuracy, and open loop method of counting is more commonly used.
But there are following defects for currently existing scheme：
Traditional counting mode needs cross clock domain to read data, be easy to cause metastable problem.When counting, because two
A clock frequency and phase are independent, so the uncertain of initial phase can introduce counting error, as shown in Figure 1, fref is
Reference clock, the feedback clock fdiv of identical frequency, because initial phase is different, count value may have 1 error.fast vco
Frequency calibration techniques for pll applications by using multiphase clock side
Formula reduces phase and does not know the error brought, and such an approach increases the complexities of circuit.
The content of the invention
For overcome the deficiencies in the prior art, one of the objects of the present invention is to provide a kind of VCO auto-calibration circuits,
It is avoided that the uncertainty of phase, shortens the time of automatic frequency calibration.
The second object of the present invention is a kind of VCO automatic calibrating methods, is avoided that the uncertainty of phase, shortens certainly
The time of dynamic frequency calibration.
An object of the present invention adopts the following technical scheme that realization：
A kind of VCO auto-calibration circuits, including reference clock counter, feedback clock counter, state machine, voltage controlled oscillation
Device, frequency divider and reseting module, the reference clock counter, feedback clock counter, reseting module and voltage controlled oscillator are equal
It is connected with state machine, reseting module, voltage controlled oscillator and feedback clock counter are connected with frequency divider；
State machine in reset state by reference clock counter, feedback clock counter resets, and make reseting module will
Divider reset in count status afterwards, makes reference clock counter and feedback clock counter count simultaneously, works as reference
The feedback count value value that feedback counter obtains is recorded when clock counter count down to pre-set count values, resets frequency divider, according to
The comparative result of pre-set count values and feedback count value finds the optimal capacitance array of values of voltage controlled oscillator to adjust by dichotomy
Save the capacitor array of voltage controlled oscillator.
The second object of the present invention adopts the following technical scheme that realization：
A kind of VCO automatic calibrating methods, comprise the following steps：
Reset process：Reference clock counter, feedback clock counter resets are made reseting module that will divide by state machine
Device resets, one middle capacitance value of output to voltage controlled oscillator；
Counting step：Frequency divider divides the output frequency of voltage controlled oscillator；Reference clock counter is outer to coming from
The input reference clock in portion counts up to a pre-set count values, and is sent to state machine；The feedback clock counter counted simultaneously will
Reference clock counter count at the end of feedback count value and be sent to state machine；The feedback count value is by coming from frequency divider
Output numerical value count to get；
Divider reset step：Frequency divider is resetted；
Comparison step：State machine compares the size of pre-set count values and feedback count value, is preset when feedback count value is less than
During count value, reduced by dichotomy and exported to the capacitance of voltage controlled oscillator, when feedback count value is more than pre-set count values,
Then pass through the capacitance of dichotomy increase output to voltage controlled oscillator；
Judgment step：State machine judges whether dichotomy is completed, if so, terminating calibration, otherwise, reference clock is counted
Device and feedback clock counter resets, return to counting step afterwards.
Compared with prior art, the beneficial effects of the present invention are：
The automatic VCO auto-calibration circuits of the present invention are since frequency divider is reset when counting and starting, when feeding back
The initial phase of clock always somewhat later than reference clock, eliminates feedback clock initial phase and does not know to reduce counting accurately
The problem of property；By being resetted to frequency divider, the time calibrated automatically can be shortened.
Description of the drawings
Fig. 1 is influence figure of the initial phase of the prior art to count value；
Fig. 2 is VCO output frequencies and control voltage, the relational graph of capacitor array；
Fig. 3 is a kind of structure chart of VCO auto-calibration circuits of the present invention；
Fig. 4 is a kind of flow chart of VCO automatic calibrating methods of the present invention；
Fig. 5 is the schematic diagram of dichotomy.
Specific embodiment
In the following, with reference to attached drawing and specific embodiment, the present invention is described further, it is necessary to which explanation is, not
Under the premise of conflicting, new implementation can be formed between various embodiments described below or between each technical characteristic in any combination
Example.
As shown in figure 3, the present invention provides a kind of VCO auto-calibration circuits, including reference clock counter 11, feedback clock
Counter 12, state machine 13, voltage controlled oscillator 14, frequency divider 15 and reseting module 16, the reference clock counter 11, feedback
Clock counter 12, reseting module 16 and voltage controlled oscillator 14 are connected with state machine 13, reseting module 16, voltage controlled oscillator 14
It is connected with feedback clock counter 12 with frequency divider 15.
Reference clock counter 11 counts input reference clock Fref under the control of state machine 13.I.e. at state machine 13
It is counted when count status.Feedback clock counter 12 counts the output of frequency divider 15 under the control of state machine 13.I.e. in shape
State machine 13 counts when being in count status.Frequency divider 15 is controlled by reseting module 16, and the output frequency of voltage controlled oscillator 14 is done
Frequency dividing.During the output of reseting module 16 1, the output of frequency divider 15 remains 0, does not work；When the output of reseting module 16 is 0, frequency divider
Work.The reset instruction of state machine 13 is passed to frequency divider 15 by reseting module 16.
If capacitor array digit is n, specific capacitance Cu, then total capacitance is (2^n-1) * Cu.State machine 13 is in reference
Clock driving is lower to work, and state machine 13 finds optimal capacitor array with dichotomy in the present invention, as shown in Figure 5.
It is as follows including step the present invention also provides a kind of VCO automatic calibrating methods with reference to Fig. 4：
S1：Reference clock counter, feedback clock counter resets are made reseting module answer frequency divider by state machine
Position, the middle capacitance value of output capacitance array to voltage controlled oscillator；
In this step, reference clock counter 11 and feedback clock counter 12 are all reset to 0, state machine output
Reset div reset to 1, therefore frequency divider 15 is reset also by reseting module 16, and state machine 13 exports cap sel<n-1:
0>Take median, that is, cap_sel<n-1:0>=2^ (n-1) is the actual value of 14 capacitor array of voltage controlled oscillator.State
Machine 13 exports afc done and is reset to 0, and state machine 13 exports reset cnt by reference clock counter 11 and feedback clock at this time
Counter 12 resets to 0.It should be noted that this step is initialization step, the generation and release of initial reset signal
Clock generates generally with 3 power sense circuits in routine techniques, services nearly all circuit module on chip and resets letter
It number generates, circuit resets upon, and reset signal release, circuit begins to work.The initial reset of circuit common module register
Action is controlled by this signal, but will not usually be generated by this module, in circuit common module, initial reset signal
It is to be controlled from this module, this is this field conventional technical means, therefore actually S1 completes initial reset and reset
The function of releasing, in real work, circuit is after initial reset makes register obtain default value, with regard to releasing and entering at once
Working condition.
S2：Frequency divider divides the output frequency of voltage controlled oscillator；Reference clock counter is to from the defeated of outside
Enter reference clock and count up to a pre-set count values, that is, when reference clock counter counts count to the pre-set count values terminates to count
Number, by pre-set count values and is sent to state machine；Feedback clock counter counts simultaneously, terminates in the counting of reference clock counter
When the output numerical value from frequency divider counted to get into a feedback count value, and be sent to state machine；
More than S2 can be summarized as count status, and under this state, counter 11 counts the fixed cycle to reference clock Fref
Number cnt_ref.Under the control of state machine 13, reseting module 16 releases the reset of frequency divider, the reset of two counters 11 and 12
Also it is released from.The reset of counter 11 can just count after releasing.
After counter 11 count down to designated value cnt_ref, into divider reset state S3.
S3：Frequency divider is resetted；Frequency divider output is reset to 0, and there is no rate-adaptive pacemakers.Because frequency divider be
It counts and is reset when starting, therefore the initial phase of feedback clock is always somewhat later than reference clock, it is thus eliminated that feedback
Not the problem of clock initial phase does not know to reduce count accuracy.
S4：State machine compares the size of pre-set count values and feedback count value, when feedback count value is less than pre-set count values
When, output is reduced to the capacitance of voltage controlled oscillator by dichotomy, when feedback count value is more than pre-set count values, is then passed through
Dichotomy increase is exported to the capacitance of voltage controlled oscillator；
S5：State machine judges whether dichotomy is completed, if so, terminate calibration, otherwise, by reference clock counter and
Feedback clock counter resets, afterwards return to step S3.
Reset in S1 refers to the overall initial reset of entire circuit, resets whole registers, is the normal of circuit
Work is ready.S4 is the counter and pre-set count values for comparing feedback clock counter, so as to determine to increase still
Reduce output capacitance value, also to judge whether dichotomy has been finished afterwards, if being put into done state, otherwise just to ginseng
Clock counter and feedback clock counter resets are examined, is not related to the reset of other registers.
The value of two counters is read and is compared by state machine 13, if cnt_div is less than cnt_ref, illustrates frequency divider
15 output frequencies are smaller, are reduced by the value of capacitance output cap_sel；, whereas if cnt_div is more than cnt_ref, just increase
Large capacitance exports the value of cap_sel.Because frequency divider has been reset, feedback clock counter 12 keeps count status
Numerical value do not have any variation, this eliminates the need for conventional method indefinite state that may be present.In conventional methods where, because with reference to
Clock and feedback clock are non-homogeneous clocks, and relative frequency and phase are all uncertain.Therefore under a clock control
Go the data for reading the generation of another clock threshold that cannot ensure settling time and retention time, it is possible to change in data
When not yet stablizing, data are read.At this moment the high level or low level that the data read are not to determine, but a kind of intermediate shape
State, this metastable presence may cause procedure failure.Although it can be reduced using the method for insertion register synchronization metastable
State causes the probability of failure still cannot thoroughly eliminate.Methods presented herein just solves the problems, such as this well.
If dichotomy completion is put into done state, capacitor array cap_sel is set<n-1:0>For optimum value.State
Machine output afc_done is arranged to 1, and calibration is completed.
Otherwise into counter resets state, the counter of two counters 11 and 12 is reset to 0.Meter is entered back into afterwards
Number state starts a new round and counts.Until dichotomy is completed.
The above embodiment is only the preferred embodiment of the present invention, it is impossible to the scope of protection of the invention is limited with this,
The variation and replacement for any unsubstantiality that those skilled in the art is done on the basis of the present invention belong to institute of the present invention
Claimed scope.
Claims (2)
1. a kind of VCO auto-calibration circuits, which is characterized in that including reference clock counter, feedback clock counter, state
Machine, voltage controlled oscillator, frequency divider and reseting module, the reference clock counter, feedback clock counter, reseting module and pressure
Control oscillator is connected with state machine, and reseting module, voltage controlled oscillator and feedback clock counter are connected with frequency divider；State
Machine, by reference clock counter, feedback clock counter resets, and makes reseting module by divider reset in reset state,
During count status afterwards, reference clock counter and feedback clock counter is made to count simultaneously, when reference clock counter counts
The feedback count value that feedback counter obtains is recorded when counting to pre-set count values, resets frequency divider, according to pre-set count values and instead
The comparative result of feedback count value finds the optimal capacitance array of values of voltage controlled oscillator to adjust voltage controlled oscillator by dichotomy
Capacitor array.
2. a kind of VCO automatic calibrating methods, which is characterized in that comprise the following steps：
Reset process：Reference clock counter, feedback clock counter resets are made reseting module answer frequency divider by state machine
Position, one middle capacitance value of output to voltage controlled oscillator；
Counting step：Frequency divider divides the output frequency of voltage controlled oscillator；Reference clock counter is to from outside
Input reference clock counts up to a pre-set count values, and is sent to state machine；The feedback clock counter counted simultaneously will refer to
Clock counter count at the end of feedback count value and be sent to state machine；The feedback count value is by from the defeated of frequency divider
Go out numeric counter to obtain；
Divider reset step：Frequency divider is resetted；
Comparison step：State machine compares the size of pre-set count values and feedback count value, when feedback count value is less than default count
During value, output is reduced to the capacitance of voltage controlled oscillator by dichotomy, when feedback count value is more than pre-set count values, is then led to
Dichotomy increase output is crossed to the capacitance of voltage controlled oscillator；
Judgment step：State machine judges whether dichotomy is completed, if so, terminate calibration, otherwise, by reference clock counter and
Feedback clock counter resets, return to counting step afterwards.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711387872.8A CN108063618B (en) | 2017-12-20 | 2017-12-20 | VCO automatic calibration circuit and method |
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| CN201711387872.8A CN108063618B (en) | 2017-12-20 | 2017-12-20 | VCO automatic calibration circuit and method |
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| CN108063618B CN108063618B (en) | 2021-09-28 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365335A (en) * | 2019-08-12 | 2019-10-22 | 兆讯恒达微电子技术(北京)有限公司 | A kind of piece internal clock calibration method in technical process and calibration circuit |
| CN110504959A (en) * | 2019-08-12 | 2019-11-26 | 兆讯恒达微电子技术(北京)有限公司 | The calibration method and calibration circuit of a kind of internal clock |
| CN110954878A (en) * | 2019-11-21 | 2020-04-03 | 西安电子工程研究所 | Method for open loop detection of metastable state and correction |
| CN111404545A (en) * | 2020-04-20 | 2020-07-10 | 成都华微电子科技有限公司 | Oscillator circuit with digital trimming function and clock signal generation method |
| CN111414093A (en) * | 2019-01-04 | 2020-07-14 | 瑞鼎科技股份有限公司 | Capacitive touch detection circuit |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111414093A (en) * | 2019-01-04 | 2020-07-14 | 瑞鼎科技股份有限公司 | Capacitive touch detection circuit |
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| CN110954878A (en) * | 2019-11-21 | 2020-04-03 | 西安电子工程研究所 | Method for open loop detection of metastable state and correction |
| CN110954878B (en) * | 2019-11-21 | 2023-03-10 | 西安电子工程研究所 | Method for open loop detection of metastable state and correction |
| CN111404545A (en) * | 2020-04-20 | 2020-07-10 | 成都华微电子科技有限公司 | Oscillator circuit with digital trimming function and clock signal generation method |
| CN111404545B (en) * | 2020-04-20 | 2022-07-29 | 成都华微电子科技股份有限公司 | Oscillator circuit with digital trimming function and clock signal generation method |
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