CN110954878B

CN110954878B - Method for open loop detection of metastable state and correction

Info

Publication number: CN110954878B
Application number: CN201911149891.6A
Authority: CN
Inventors: 朱康生; 余铁军; 王栋; 由法宝; 郝金华; 王瑞斌; 于萌
Original assignee: Xian Electronic Engineering Research Institute
Current assignee: Xian Electronic Engineering Research Institute
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2023-03-10
Anticipated expiration: 2039-11-21
Also published as: CN110954878A

Abstract

The invention relates to a method for open loop detection metastable state and correction, wherein a frequency synthesizer outputs a coherent clock signal to a test tool, and the test tool generates a PRF signal by taking the coherent clock signal as a reference and outputs the PRF signal to the frequency synthesizer; the frequency synthesis takes a PRF signal as the output timing of a complex waveform signal; the metastable state detection logic is adopted for frequency synthesis to judge the relation between the local logic clock and PRF edge-edge (rising edge), and the frequency synthesis can stably acquire the PRF signal by switching the clock, so that the edge sampling is avoided, and the metastable state problem is solved.

Description

Method for open loop detection of metastable state and correction

Technical Field

The invention relates to a method for open-loop metastable state detection and correction, belongs to the technical field of radars, and is applied to a radar system.

Background

In a radar system, a Frequency synthesizer (hereinafter referred to as a "Frequency synthesizer") generally outputs a coherent clock signal to a signal processor (hereinafter referred to as a "signal processing unit"), and the signal processing unit generates a radar system timing signal based on the clock signal, wherein a Pulse Repetition Frequency (PRF) signal output to the Frequency synthesizer is used as an output timing of a complex waveform signal of the Frequency synthesizer, and the Frequency synthesizer uses a local logic clock (which is the same source as the PRF signal) to sample the PRF signal to determine an output start of the complex waveform signal. Due to factors such as PRF signal transmission link time delay, device temperature drift, related clock frequency division multiple phases and the like, the situation that the rising edge of a local logic clock is adopted to the rising edge of a PRF signal, namely the so-called 'edge-adopted edge' or 'metastable state', is unstable in the acquisition output state, and initial phase random jump of a complex frequency synthesis waveform signal is caused.

Disclosure of Invention

Technical problem to be solved

In order to solve the metastable state problem between the frequency synthesis local logic clock and the PRF signal, the initial phase of the complex waveform signal is stabilized. The invention provides a method for open loop detection of metastable state and correction.

Technical scheme

A method for open-loop metastability detection and correction, comprising the steps of:

step 1: the frequency synthesizer outputs the coherent clock signal to a test tool at the analog signal position;

step 2: the test tool generates a PRF signal by taking the coherent clock signal as a reference and outputs the PRF signal to the frequency synthesizer; the frequency synthesizer takes a PRF signal as the output timing of a complex waveform signal;

and step 3: frequency synthesis real-time checking whether the count values of the PRF adjacent periods are equal, if so, no metastable state occurs, and the current local logic clock is still adopted; if not, metastable state occurs, and the clock after phase shift is selected as the current local logic clock;

and 4, step 4: the frequency synthesizer can stably acquire the PRF signal by switching the clock, avoid 'edge acquisition', and solve the problem of metastable state.

The step 3 is as follows: firstly, synchronously latching an externally input PRF signal 2 beat trigger by a local logic clock to obtain reg _ PRF, then taking the front edge of the reg _ PRF with the single period width as the counting enable of a counter, simultaneously taking the enable signal as the latching enable of a count value, and checking whether the count values cnt1[ n-1..0] and cnt2[ n-1..0] of adjacent periods are equal or not in real time, if so, no metastable state occurs, and the current local logic clock is still adopted; if the clock signals are not equal to the local logic clock, a metastable state occurs, the detection result identifier is set at the moment, and the signal selects the clock with the phase shift of 90-180 degrees as the current local logic clock through the mux.

Advantageous effects

Compared with the prior art, the method for detecting the metastable state and correcting the metastable state by the open loop has the following advantages that:

1) The novel metastable state detection and correction method designed by the invention only carries out open loop detection and correction by the frequency synthesizer per se, and does not relate to the expenses of software and hardware of other systems;

2) The novel metastable state detection and correction method designed by the invention is suitable for different environmental temperatures and device aging factors, and can be used for real-time calibration;

3) The hardware scheme of the metastable state detection and correction method designed by the invention is consistent with the original scheme and is unchanged in aspects of cost, volume, weight and the like;

4) The novel metastable state detection and correction method designed by the invention is not changed in the aspects of electromagnetic compatibility, phase noise, stray and the like;

drawings

FIG. 1 is a block diagram of an implementation of the present invention;

FIG. 2 is a block diagram of the process flow of the present invention;

FIG. 3 is a block diagram of the processing sequence of the present invention;

FIG. 4 is a block diagram of the experimental verification of the present invention.

Detailed Description

The invention will now be further described with reference to the following examples and drawings:

the invention consists of 2 parts: frequency synthesis and testing tools (simulating the timing of the letter position);

1) The frequency synthesizer generally comprises a crystal oscillator, a control unit and a frequency synthesis unit (local oscillator signal, complex waveform signal, coherent clock signal, etc.);

2) The frequency synthesizer outputs a reference clock signal (generally a signal sampling clock) to a test tool (the test tool is not needed in the actual work of the frequency synthesizer, and the test tool only simulates partial functions of a signal and is used for test verification);

3) The test tool generates a PRF signal by taking the coherent clock signal as a reference and outputs the PRF signal to the frequency synthesizer; the frequency synthesizer takes a PRF signal as the output timing of a complex waveform signal;

4) The metastable state detection logic is adopted for frequency synthesis to judge the relation between the local logic clock and PRF (rising edge): frequency synthesis real-time checking whether the count values of the PRF adjacent periods are equal, if so, no metastable state occurs, and the current local logic clock is still adopted; if not, then a metastable state occurs, and at this time, the phase-shifted clock is selected as the current local logic clock.

5) If the 'edge-edge' is close, the frequency synthesizer shifts the phase of the local logic clock through a PLL inside the FPGA (if the system error allows, the phase can be directly shifted by 180 degrees), and the 'edge-edge' is pulled open, so that the PRF signal can be stably acquired, the 'edge acquisition' is avoided, and the problem of a metastable state is solved.

FIG. 1 is a block diagram of frequency synthesis open loop metastability and correction. The intermediate frequency comprehensive testing tool (the intermediate frequency comprehensive does not need the testing tool in actual work, the testing tool only simulates partial functions of a signal part and is used for test verification) outputs coherent clock signals, the testing tool generates PRF signals by taking the clock as a reference and outputs the PRF signals to the intermediate frequency comprehensive, and whether the video comprehensive function of a communication interface is needed or not is generally used for controlling switching waveforms and types of the PRF signals.

FIG. 2 shows the process flow of the frequency synthesis open loop detection metastability and correction. After a system is electrified, firstly, synchronously latching an externally input PRF signal 2-beat trigger by using a local logic clock to obtain reg _ PRF, then taking the front edge of the reg _ PRF with a single period width as a counter (the module value is larger than the period of the known system PRF), enabling the counting of the counter, simultaneously taking an enabling signal as the latching enabling of a counting value, checking whether the counting values cnt1[ n-1..0] and cnt2[ n-1..0] of adjacent periods are equal or not in real time, and if so, generating no metastable state and still adopting the current local logic clock; if the local clock is not equal to the local clock, a metastable state occurs, the detection result identifier is set at the moment, and the signal selects the clock with the phase shift (considering the temperature drift of the system and taking the phase shift value of 90-180 degrees) as the current local logic clock through the mux.

FIG. 3 is a diagram illustrating the loop-locked loop detection metastability and correction timing. When the frequency synthesizer detects that the count values of the adjacent PRF periods are not equal, the 'edge-edge' is considered to be close (t) ₁ Time of day), a metastable state exists, and the logic clock phase-shifted by a phase-locked loop (usually an internal PLL of an FPGA) is selected as the current local logic clock. At this time, the phase-shifted clock can stably acquire the PRF signal (t) ₂ Time of day).

FIG. 4 is a graph showing the verification of the frequency synthesis open loop for meta-stability detection and correction test. The PRF signal is delayed by the variable delayer and then output to the frequency synthesizer, the variable delayer manually delays the PRF signal by 100ps, and the complex waveform signal can be observed on an oscilloscope to be subjected to coaxial detection and then to single jitter relative to the PRF (a typical value is that if the phase shift is 180 degrees, the complex waveform signal is jittered for 1 time about every 0.5 local clock period), and the complex waveform signal can be always corrected to a phase stable state relative to the PRF. Meanwhile, a logic analyzer (such as signalcap) embedded in an FPGA (field programmable gate array) in the frequency synthesizer can be used for capturing the count value, and the change of the adjacent count value when the metastable state occurs is observed.

Table 1 lists a comparison of this scheme with a closed loop scheme.

Table 1 comparison table between this scheme and closed-loop scheme

As can be seen from Table 1, the scheme has better independence, and real-time reliable detection and stable correction are completed by frequency synthesis, so that the reliability and the environmental adaptability of the system are improved.

Claims

1. A method for open-loop metastability detection and correction, comprising the steps of:

step 1: outputting the coherent clock signal to a test tool of an analog signal position by the frequency synthesizer;

and 2, step: the test tool generates a PRF signal by taking the coherent clock signal as a reference and outputs the PRF signal to the frequency synthesizer; the frequency synthesizer takes a PRF signal as the output timing of a complex waveform signal;

and step 3: frequency synthesis real-time checking whether the count values of the PRF adjacent periods are equal, if so, no metastable state occurs, and the current local logic clock is still adopted; if not, a metastable state occurs, and the clock after phase shifting is selected as the current local logic clock;

firstly, synchronously latching an externally input PRF signal 2 beat trigger by a local logic clock to obtain reg _ PRF, then taking the front edge of the reg _ PRF with the single period width as the counting enable of a counter, simultaneously taking the enable signal as the latching enable of a count value, and checking whether the count values cnt1[ n-1..0] and cnt2[ n-1..0] of adjacent periods are equal or not in real time, if so, no metastable state occurs, and the current local logic clock is still adopted; if the two clock signals are not equal, metastable state occurs, the detection result is identified and set at the moment, and the signal selects a clock with phase shift of 90-180 degrees as the current local logic clock through the mux;