CN114441860B - Digital pulse width capturing system and method - Google Patents
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Abstract
A digital pulse width capture system and method, the said system includes, delay unit, border detecting element, first border detecting element, FIFO and control unit step by step, and the digital timer, the said delay unit step by step, it delays the main clock signal step by step, produce multiple step by step delayed clock signals; each of the plurality of edge detection units detects an edge of an input signal by using the step-by-step delay clock signal and outputs an edge detection signal with a logic level of '1'; the first edge detection unit is used for detecting a plurality of edge detection signals and outputting the path number which jumps first as the decimal part of a measured value; the digital timer measures an input signal by using an input main clock signal and generates an integer part output of a measured value; the FIFO and control unit combines the integer part of the measurement value and the fractional part of the measurement value to obtain the final measurement value output.
Description
Technical Field
The invention relates to the technical field of electronic circuit design, in particular to a digital pulse width capture system and a digital pulse width capture method.
Background
In an MCU (micro control Unit) chip, it is generally necessary to measure a period, a duty ratio, and the like of an externally input Digital signal through a Digital Capture Unit (Digital Capture Unit). Generally, the unit includes a timer with an increasing count value every period, and the count value of the timer at the moment can be configured and stored at the rising edge or the falling edge (or double edges) of the signal; and then calculating the period or duty ratio of the signal by means of software or hardware. In some cases, the digital capture unit needs to have a high measurement accuracy, for example, an accuracy of 100ps or even higher.
At present, the measurement precision of the digital input pulse width is improved mainly by improving the input clock frequency, if the measurement precision needs to be further improved, the input clock frequency of the timer needs to be improved, for example, for the precision of 1ns, the input clock frequency needs to be more than 1 GHz; or by a high-speed sampling chip (for example, some oscilloscopes can provide a sampling rate of more than 20G), and then analyzing the sampling signal to obtain a more accurate measurement value. The former has too high frequency, so that it is difficult to satisfy the timing requirement when implementing the chip, and the latter requires extremely high cost.
For the MCU chip which is used in a large amount in practical applications, the operating frequency is often much less than 1GHz (corresponding to 1ns accuracy). It is therefore desirable to find a way to achieve higher measurement accuracy (e.g., 100 ps) at lower operating frequencies (e.g., 100 MHz).
Disclosure of Invention
In order to solve the defects of the prior art, the present invention aims to provide a digital pulse width capture system and method, which can significantly improve the pulse width measurement (capture) precision of a digital input signal at a lower input clock frequency, and is convenient to implement in a chip, especially a chip with a lower operating frequency.
To achieve the above object, the present invention provides a digital pulse width capture system, which comprises a step-by-step delay unit, an edge detector unit, a first edge detector unit, a FIFO and control unit, and a digital timer, wherein,
the step-by-step delay unit delays the main clock signal step by step to generate a plurality of step-by-step delay clock signals;
each of the plurality of edge detection units detects an edge of an input signal by using the progressive delay clock signal and outputs an edge detection signal having a logic level of '1';
the first edge detection unit is used for detecting a plurality of edge detection signals and outputting the path number which jumps first as the decimal part of the measured value;
the digital timer measures an input signal by using an input main clock signal and generates an integer part output of a measured value;
the FIFO and control unit combines the integer part of the measurement value and the fractional part of the measurement value to obtain the final measurement value output.
Further, the progressive delay unit comprises a master delay line, a slave delay line control unit and a slave delay line, wherein,
the master delay line generates a control signal according to a received master clock signal and sends the control signal to the slave delay line control unit;
the slave delay line control unit generates a plurality of delay unit control signals according to the control signals and respectively sends the delay unit control signals to the plurality of slave delay lines;
and each of the plurality of slave delay lines controls the delay time of the master clock signal according to the delay unit control signal, generates a plurality of step-by-step delay clock signals and outputs the step-by-step delay clock signals to the corresponding edge detection unit.
Furthermore, the slave delay line control unit determines the number of the required delay units and the number of the control signals of the delay units according to the control signals output by the master delay line.
Further, the main delay line comprises a phase detection control unit and a delay unit, wherein,
the input end of the phase detection control unit is respectively connected with a main clock signal and the output end of the last delay unit in the plurality of step-by-step connected delay units; the output end of the delay unit outputs a control signal to control the enabling or direct connection of each delay unit and adjust the phase deviation to be half of the period of the main clock signal;
the first-stage input of the delay units connected in a stage-by-stage manner is connected with a main clock signal, and the last-stage output of the delay units is connected with one input end of the phase detection control unit.
Further, the edge detector cell structure includes a D flip-flop and an exclusive or gate, wherein,
the CP input end of the D trigger is connected with the output end of the step-by-step delay unit, and the D input end of the D trigger is connected with an input signal; the output end of the exclusive-or gate is connected with one input end of the exclusive-or gate;
the other input end of the exclusive-or gate is connected with a main clock signal, and when the input signal has a jump, the output end of the exclusive-or gate outputs an edge detection signal with a logic level of '1'.
In order to achieve the above object, the present invention further provides a digital pulse width capturing method, including the following steps:
1) measuring an input signal by using a digital timer, and taking a measurement result as an integer part of a measurement value;
2) step-by-step delaying the main clock signal to generate a plurality of step-by-step delayed clock signals;
3) detecting the edge of an input signal by utilizing a step-by-step delay clock signal to generate an edge detection signal;
4) detecting a path which jumps firstly from the edge detection signal, and taking the number of an output path as the decimal part of a measured value;
5) the integer part of the measurement is combined with the fractional part of the measurement to obtain the final measurement.
Further, the step 2) further comprises the steps of,
detecting a phase deviation between an input clock and an output clock and generating a control signal;
determining the number of the delay units and the control signals of the delay units according to the control signals;
and controlling the delay time of the main clock signal according to the delay unit control signal to generate a plurality of step-by-step delay clock signals.
Further, the step 3) may further include detecting the input signal using the progressive delay clock signal, and outputting an edge detection signal having a logic level of '1' when the input signal has a transition.
In order to achieve the above object, the present invention further provides a digital pulse width capture chip, which includes the above digital pulse width capture system.
In order to achieve the above object, the present invention further provides a digital pulse width capture device, which includes the above digital pulse width capture chip.
To achieve the above object, the present invention further provides an electronic device, which includes a processor, and a memory, where the memory stores a computer program, and the computer program, when read and executed by the processor, executes the steps of the above digital pulse width capture method.
To achieve the above object, the present invention further provides a computer-readable storage medium, in which a computer program is stored, the computer program being configured to perform the steps of the above digital pulse width capture method when executed.
Compared with the prior art, the digital pulse width capturing system and the method thereof have the following beneficial effects:
the input clock signal is sampled for a plurality of times after being delayed, a path (as a decimal part) which jumps first in a main clock period is detected, and an accurate measurement value is obtained by combining the counting (integer part) of the input clock signal on a main delay line. Assuming that the period of the input main clock is T, under the condition of adopting N delay units, the measured time resolution is up to T/N, namely the precision is increased by N times, and the precision of digital pulse width capture is obviously improved under the condition of not increasing the frequency of the input clock.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a digital pulse width capture system according to the present invention;
FIG. 2 is a schematic diagram of a stage-by-stage delay unit according to the present invention;
FIG. 3 is a schematic diagram of a waveform of an input pulse signal after passing through a step-by-step delay unit according to the present invention;
FIG. 4 is a schematic diagram of a main delay line structure according to the present invention;
FIG. 5 is a schematic diagram of a slave delay line structure according to the present invention;
FIG. 6 is a schematic diagram of an edge detector cell according to the present invention;
FIG. 7 is a flow chart of a digital pulse width capture method according to the present invention;
fig. 8 is a schematic view of a scenario according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical scheme provided by the invention is mainly applied to automobile electronic circuits, the working frequency of the MCU chip which is used in a large amount in practical application is often far less than 1GHz (corresponding to 1ns precision), the digital input pulse width measurement precision is improved mainly by improving the input clock frequency at present, if the measurement precision needs to be further improved, the input clock frequency of a timer needs to be improved, or a high-speed sampling chip is adopted, the former has too high required frequency, so that the time sequence requirement is difficult to meet when the chip is realized, and the latter needs extremely high cost.
The embodiment of the invention provides that a Master delay line (Master DLL) and a Slave delay line (Slave DLL) achieve the effect of gradually delaying an input Master clock through the Master delay line and a plurality of Slave delay lines, and the clock which is gradually delayed is input into an edge detection unit at the lower stage for detecting the edge of an input signal.
Example 1
Fig. 1 is a schematic diagram of a digital pulse width capture system according to the present invention, as shown in fig. 1, the digital pulse width capture system of the present invention comprises a progressive delay unit 10, an edge detection unit 20, a first edge detection unit 30, a FIFO and control unit 40, and a digital timer 50, wherein,
the progressive delay unit 10 performs progressive delay on the received master clock signal (CLK _ 0), generates a plurality of progressive delay clock signals (CLK _1, CLK _2 … … CLK _ N-1), and respectively sends the signals to the corresponding edge detection units 20.
Each of the plurality of Edge detecting units 20 receives the progressive delay clock signal from the progressive delay unit 10, detects an Edge of the INPUT signal (INPUT) using the progressive delay clock signal, detects whether the INPUT signal on each path has a transition, and outputs an Edge Detected signal (Edge _ Detected _ x) having a logic level of '1' when the INPUT signal has a transition.
The first Edge detector 30 receives Edge detection signals (Edge _ Detected _1, Edge _ Detected _2 … … Edge _ Detected _ N-1) from the plurality of Edge detectors 20, is combinational logic, detects a path that makes a transition first in one master clock cycle, and sends an output path number as a fractional part of a measurement value to the FIFO and control unit 40 at a rising Edge of the next master clock signal.
And a digital timer 50 for measuring an input signal using the input master clock signal and transmitting the measurement result to the FIFO and control unit 40 as an integer part of the measurement value.
A FIFO and control unit 40 which receives the integer part of the measurement value from the digital timer 50 and the fractional part of the measurement value from the first Edge detector unit 30, respectively, and pushes the integer part and fractional part (Edge Detected Out) of the measurement value into the FIFO at the rising Edge of the main clock signal for subsequent software to read.
Fig. 2 is a schematic diagram of a structure of a progressive delay unit according to the present invention, and as shown in fig. 2, the progressive delay unit 10 of the present invention includes a master delay line 11, a Slave delay line control unit (Slave DLL Cfg) 12, and a Slave delay line 13, wherein,
and a master delay line 11 for generating a control signal (DLY _ CELL _ N [ N:0 ]) according to the received master clock signal and transmitting the control signal to a slave delay line control unit 12.
And a slave delay line control unit 12 for generating a plurality of delay unit control signals (DLL _ CTL _1, DLL _ CTL _2 … … DLL _ CTL _ N-1) according to the control signal from the master delay line 11, and transmitting the delay unit control signals to the slave delay line 13, respectively.
In the embodiment of the present invention, the slave Delay line control unit 12 generates the control signal DLL _ CTL _ x of each slave Delay line according to DLY _ CELL _ N (representing the number of Delay CELLs required for delaying 180 degrees) output by the master Delay line 11. Wherein DLL _ CTL _ x = DLY _ CELL _ N × 2/N × x.
Each of the plurality of slave delay lines 13 controls the delay time of the master clock signal according to the received delay cell control signal of the slave delay line control unit 12, and generates a plurality of progressive delayed clock signals (CLK _1, CLK _2 … … CLK _ N-1) to be respectively output to the corresponding edge detecting units 20.
Fig. 3 is a waveform diagram of the input pulse signal after passing through the stage-by-stage Delay units according to the present invention, and as shown in fig. 3, the slave Delay line control unit 12 generates the control signal DLL _ CTL _ x of each slave Delay line according to DLY _ CELL _ N (representing the number of Delay CELLs required to Delay 180 degrees) output by the master Delay line 11. Wherein DLL _ CTL _ x = DLY _ CELL _ N × 2/N × x. And waveforms and phase relations of the clocks (CLK _1 to CLK _ N-1) delayed by the slave delay lines, wherein Tdelay _1 is the delay time of the clock signal CLK _1, and Tdelay _ N-1 is the delay time of the clock signal CLK _ N-1. Assuming that the period of CLK _0 (master clock) is T, Tdelay _1 = T/N, Tdelay _2 = 2 × T/N, and Tdelay _ N-1 = (N-1)/N × T, the periods of CLK _1 to CLK _ N-1 are unchanged and remain T.
Fig. 4 is a schematic diagram of a main delay line structure according to the present invention, as shown in fig. 4, a main delay line 11 of the present invention includes a phase detection Control Unit (phase Detect and Control Unit) 110, a plurality of delay units (delay cell, delay Unit-1, delay Unit-2 … … delay Unit-N), wherein,
the input end of the phase detection control unit 110 is connected to the master clock signal and the output end of the last Delay unit of the plurality of Delay units, and the output end thereof outputs a control signal (DLY _ CELL _ N [ N:0 ]) to control the enable or Bypass of each Delay CELL to adjust the phase deviation to half the cycle of the master clock signal (i.e. 180 degrees).
The input ends and the output ends of a plurality of delay units (delay unit-1 and delay unit-2 … … delay unit-N) are connected step by step, the input end of the first-stage delay unit is connected with the main clock signal, and the output end of the last-stage delay unit is connected with the input end of the phase detection control unit 110.
IN the embodiment of the present invention, the main Delay line 11 detects the Phase deviation between the input clock and the output clock (CLK _ OUT) through the Phase Detect and Control Unit, and generates the Control signal DLY _ CELL _ N [ N:0] to Control the enable or Bypass of the Delay CELL to adjust the Phase deviation to half the CLK _ IN period (i.e. 180 degrees). For each Delay Cell, the Delay of the clock input to it is generated if enabled. If the frequency of CLK _ OUT changes (e.g., due to temperature changes), the Phase Detect and Control Unit dynamically adjusts the value of DLY _ CELL _ N [ N:0] to ensure that the Phase offset is adjusted to half the CLK _ IN period.
Fig. 5 is a schematic diagram of a slave delay line structure according to the present invention, and as shown in fig. 5, the slave delay line 13 of the present invention has the same structure as the master delay line 11 except that no phase detection control unit is needed, and is not described again.
Fig. 6 is a schematic diagram of an edge detector cell 20 according to the present invention, as shown in fig. 6, which includes a D flip-flop 21 and an exclusive or gate 22, wherein,
the CP input end of the D flip-flop 21 is connected to the progressive delay clock signal output by the progressive delay unit 10, the D input end is connected to the input signal, and the output end is connected to one input end of the exclusive or gate 22.
The other input terminal of the exclusive or gate 22 is connected to the main clock signal, and when the input signal has a transition, the output terminal thereof outputs an Edge detection signal (Edge _ Detected _ x) having a logic level of '1'.
Example 2
The invention also provides a digital pulse width capturing method. Fig. 7 is a flowchart of a digital pulse width capturing method according to the present invention, which will be described in detail with reference to fig. 7.
First, in step 701, an input signal is measured by a digital timer, and the measurement result is taken as an integer part of the measurement value.
In step 702, the master clock signal is delayed stage by stage to generate a plurality of stage-by-stage delayed clock signals.
In the embodiment of the invention, a phase detection control unit of a main delay line 11 detects the phase deviation between an input clock and an output clock and generates a control signal DLY _ CELL _ N [ N:0 ]; the slave delay line control unit 12 generates each delay unit control signal according to the control signal DLY _ CELL _ N [ N:0 ]; the slave delay line controls the delay time of the master clock signal according to the delay unit control signal to generate a plurality of step-by-step delay clock signals.
In step 703, the edge of the input signal is detected using the step-by-step delayed clock signal to generate an edge detection signal.
In the embodiment of the invention, the Edge detection unit detects the input signal by using the step-by-step delay clock signal, and outputs the Edge detection signal (Edge _ Detected _ x) with the logic level of '1' when the input signal jumps.
In step 704, the path that first jumps is detected from the edge detection signal, and the output path number is used as the fractional part of the measured value.
In the embodiment of the invention, the first edge detection unit detects the path which jumps first from a plurality of received edge detection signals, and takes the output path number as the decimal part of the measured value.
In step 705, the integer portion of the measurement is combined with the fractional portion of the measurement to obtain a final measurement.
Example 3
For a scenario with multiple inputs, the progressive delay units and the delay clocks (CLK _1 to CLK _ N-1) can be multiplexed, i.e. only one progressive delay unit is needed for high precision pulse width measurement of multiple input signals. Fig. 8 is a schematic diagram of a scenario according to an embodiment of the present invention, and as shown in fig. 8, when the input signal is two input signals, the system includes a progressive delay unit, and each input signal corresponds to a group of edge detection units, a first edge detection unit, a digital timer, and a FIFO and control unit, respectively. The structure for accommodating more input signals is similar here and will not be described again.
Example 4
The embodiment of the invention also provides a digital pulse width capturing chip, which comprises the digital pulse width capturing system in the embodiment.
Example 5
The embodiment of the invention also provides a digital pulse width capturing device, which comprises the digital pulse width capturing chip in the embodiment.
Example 6
Embodiments of the present invention further provide an electronic device, which includes a processor and a memory, where the memory stores a computer program, and the computer program, when read and executed by the processor, performs the steps in the above digital pulse width capture method embodiments.
Example 7
Embodiments of the present invention further provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in the above digital pulse width capture method embodiments when running.
The invention provides a digital pulse width capturing system and a method thereof, wherein the method provides a plurality of configurable delay units by using the technologies of a digital phase-locked loop and the like, the delay units respectively carry out different delays on a main clock, then a plurality of delay clocks are used for sampling the same input digital signal and recording a path (as a decimal part) sampled to a jump edge firstly, and the accurate measured value is obtained by combining the counting (integer part) of the main clock. Assuming that the period of the input main clock is T, under the condition of adopting N delay units, the measured time resolution is up to T/N, namely the precision is increased by N times, and the digital pulse width capture precision is obviously improved under the condition of not increasing the frequency of the input clock.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described above, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A digital pulse width capture system comprising a progressive delay unit, an edge detector unit, a first edge detector unit, a FIFO and control unit, and a digital timer, wherein,
the step-by-step delay unit delays the main clock signal step by step to generate a plurality of step-by-step delay clock signals;
each of the plurality of edge detection units detects an edge of an input signal by using the progressive delay clock signal and outputs an edge detection signal having a logic level of '1';
the first edge detection unit is used for detecting a plurality of edge detection signals and outputting the path number which jumps first as the decimal part of the measured value;
the digital timer measures an input signal by using an input main clock signal and generates an integer part output of a measured value;
the FIFO and control unit combines the integer part of the measured value and the decimal part of the measured value to obtain the final measured value output;
the stage-by-stage delay unit comprises a master delay line, a slave delay line control unit and a slave delay line, wherein,
the master delay line generates a control signal according to a received master clock signal and sends the control signal to the slave delay line control unit;
the slave delay line control unit generates a plurality of delay unit control signals according to the control signals and respectively sends the delay unit control signals to the plurality of slave delay lines;
and each of the plurality of slave delay lines controls the delay time of the master clock signal according to the delay unit control signal, generates a plurality of step-by-step delay clock signals and outputs the step-by-step delay clock signals to the corresponding edge detection unit.
2. The digital pulse width capture system of claim 1, wherein the slave delay line control unit determines the number of delay units and delay unit control signals required based on the control signal output by the master delay line.
3. The digital pulse width capture system of claim 1, wherein the main delay line comprises a phase detection control unit and a delay unit, wherein,
the input end of the phase detection control unit is respectively connected with a main clock signal and the output end of the last delay unit in the plurality of step-by-step connected delay units; the output end of the delay unit outputs a control signal to control the enabling or direct connection of each delay unit and adjust the phase deviation to be half of the period of the main clock signal;
the first-stage input of the delay units connected in a stage-by-stage manner is connected with a main clock signal, and the last-stage output of the delay units is connected with one input end of the phase detection control unit.
4. The digital pulse width capture system of claim 1, wherein the edge detector cell structure comprises a D flip-flop and an XOR gate, wherein,
the CP input end of the D trigger is connected with the output end of the step-by-step delay unit, and the D input end of the D trigger is connected with an input signal; the output end of the exclusive-or gate is connected with one input end of the exclusive-or gate;
and the other input end of the exclusive-OR gate is connected with an input signal, and when the input signal has a jump, the output end of the exclusive-OR gate outputs an edge detection signal with the logic level being '1'.
5. A digital pulse width capture method using the digital pulse width capture system of any of claims 1-4, comprising the steps of:
1) measuring an input signal by using a digital timer, and taking a measurement result as an integer part of a measurement value;
2) carrying out step-by-step delay on the main clock signal to generate a plurality of step-by-step delay clock signals;
3) detecting the edge of an input signal by utilizing a step-by-step delay clock signal to generate an edge detection signal;
4) detecting a path which jumps firstly from the edge detection signal, and taking the number of an output path as the decimal part of a measured value;
5) the integer part of the measurement is combined with the fractional part of the measurement to obtain the final measurement.
6. The digital pulse width capture method of claim 5, wherein the step 2) further comprises,
detecting a phase deviation between an input clock and an output clock and generating a control signal;
determining the number of the delay units and the control signals of the delay units according to the control signals;
and controlling the delay time of the main clock signal according to the delay unit control signal to generate a plurality of step-by-step delay clock signals.
7. The digital pulse width capture method of claim 5, wherein step 3) further comprises detecting the input signal using the progressive delay clock signal, and outputting an edge detection signal having a logic level of '1' when the input signal has a transition.
8. A digital pulse width capture chip comprising the digital pulse width capture system of any of claims 1-4.
9. A digital pulse width capture device comprising the digital pulse width capture chip of claim 8.
10. An electronic device comprising a processor and a memory, characterized in that the memory stores a computer program which, when read and executed by the processor, performs the steps of the digital pulse width capture method of any of claims 5-7.
11. A computer-readable storage medium, in which a computer program is stored which is arranged such that it executes the steps of the digital pulse width capture method according to any one of claims 5 to 7.
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