CN104242930B - A kind of frequency synthesizer applied to wireless transceiver system - Google Patents
A kind of frequency synthesizer applied to wireless transceiver system Download PDFInfo
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- CN104242930B CN104242930B CN201410454548.3A CN201410454548A CN104242930B CN 104242930 B CN104242930 B CN 104242930B CN 201410454548 A CN201410454548 A CN 201410454548A CN 104242930 B CN104242930 B CN 104242930B
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Abstract
The invention discloses a kind of frequency synthesizer applied to wireless transceiver system, including two modules of automatic frequency control module and phaselocked loop, the frequency relation of automatic frequency control logic comparison reference clock and feedback clock quickly produces corresponding gate array Capacity control code under coarse mode, modulates digital controlled oscillator（DCO）Frequency of oscillation, it is final to cause the two frequency error to meet coarse adjustment frequency departure demand；Phaselocked loop passes through programmed charges pump under fine setting pattern（CP）And low pass filter（LPF）Module, realize output clock quick lock in target frequency.The frequency synthesizer adopts, the characteristics such as output clock frequency scope wide, frequency resolution high and phase noise performance good fast with loop-locking speed.Above characteristic make it that sending and receiving the frequency synthesizer that the shared single DCO of system is realized becomes a reality.
Description
Technical field
The invention mainly relates to wireless communication field, the receive-transmit system of radio communication is can be applied to, more particularly to one kind
Applied to the frequency synthesizer of wireless transceiver system, the structure to meet to receive using the frequency synthesizer of single digital controlled oscillator
Reference clock frequency that hair system proposes is wide, high resolution and noiseproof feature are good etc., and challenging needs become reality.
Background technology
As a nucleus module in wireless transceiver system, it is predominantly received between loop offer frequency frequency synthesizer
Every the high-frequency local oscillation signal corresponding with sending loop, while provide high-frequency carrier signal for transmission loop and realize that frequency is adjusted
System.The communications field is growing at present, RF communication system to the operating frequency range of frequency synthesizer, frequency resolution,
Locking time and noise perfomiance requirements are also increasingly strict therewith.
The frequency synthesizer of traditional phaselocked loop composition, as shown in figure 1, mainly by phase frequency detector, loop filter, pressure
The part such as controlled oscillator and frequency divider forms.For the structure, its output clock frequency meets Fre_vco=N*Fre_ref.For
The output clock signal that wide frequency range, precision are high and phase noise performance is good is obtained, frequency synthesizer is typically using drop
Low reference clock frequency Fre_ref technologies export the frequency resolution of clock to improve；It is defeated to realize using increase Frequency Dividing Factor N
Go out the frequency range of clock.However, using compared with small frequency reference clock, it is meant that the loop bandwidth of frequency synthesizer needs therewith
Reduce, cause the loop-locking time elongated therewith；Meanwhile narrower loop bandwidth can cause phase noise of the loop to VCO
Rejection ability is inadequate, reduces VCO phase noise performances；Using big Frequency Dividing Factor N so that phase noise contribution is proportional to frequency dividing
The phase noise increase of factor N other submodules, deteriorates frequency synthesizer overall noise.Due in loop bandwidth, phase
It is difficult to accomplish that compromise is handled on the Key Performance Indicator such as noise and locking time of position, causes traditional frequency synthesizer to meet
Modern communicationses field is fast to locking time of proposition, operating frequency range, frequency resolution are high and phase noise performance is good etc.
Performance requirement.
In addition, voltage controlled oscillator operating frequency is limited in scope in traditional frequency synthesizer, in order to meet to send loop with
And loop is received to the different demands of high frequency clock frequency range, it can be typically designed using double pressure-controlled oscillator structure, this
Sample significantly increases the design area of chip, adds chip design cost.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of frequency synthesizer applied to receive-transmit system.The frequency
Rate synthesizer mainly includes two modules of automatic frequency control logic and phaselocked loop, wherein automatic frequency control logic, DCO and anti-
Loop coarse adjustment can be rapidly completed by presenting frequency dividing composition coarse tuning loop, ensure that the frequency departure of reference clock and feedback clock enters appearance
Perhaps in the range of；Then by programming CP and LPF modules, big charging and discharging currents, lower order filter and big loop bandwidth make
Obtain phaselocked loop fine setting loop output clock quick lock in and substantially reduce locking time to target frequency, above-mentioned technology；Lead to simultaneously
Cross programming CP and LPF module so that loop bandwidth diminishes after frequency synthesizer locking, and charging and discharging currents reduce, filter order
Improve, greatly improve the phase noise performance of output clock；The frequency synthesizer uses gate array capacitance technology, realizes multiband
The clock output of wide frequency ranges, realize the frequency synthesizer based on single DCO structures and meet that receive-transmit system exports to clock
The demand of wide frequency range.
The frequency synthesizer, under conditions of reference clock frequency is not reduced, using Sigma-Delta modulator and gulp down
The decimal frequency divider that pulse technique is realized ensure that receive-transmit system while clock signal frequency scope is wide, obtain clock letter
Number high benefit of frequency resolution.
The content of the invention
The problem to be solved in the present invention is：The problem of existing for prior art, the present invention provide one kind and are applied to nothing
Line receive-transmit system frequency synthesizer, it is defeated that the frequency synthesizer realizes the clock for providing wide frequency ranges using single oscillator
Go out, meet to receive and send the needs of system is to wide reference clock frequency；The structure is using coarse tuning loop technology, regulating ring simultaneously
Road technique and VCInitial value technology is assigned, realizes target frequency quick lock in, meets current wireless transceiver system to locking
Time, fast frequency-hopped index demand；The structure is realized also using loop bandwidth Programmable Technology, Fractional Frequency-Dividing Technology simultaneously
The high frequency clock output that frequency resolution is high, phase noise performance is good.
To realize above-mentioned technical problem, solution proposed by the present invention is：A kind of frequency applied to wireless transceiver system
Rate synthesizer, it is characterised in that：Including two modules of automatic frequency control logic and phase-locked loop module；
Above-mentioned frequency synthesizer, in reception pattern, it provides correct local oscillator clock signal for receive-transmit system；
When reception pattern enables, frequency synthesizer carries out ring by automatic frequency control logic, DCO and feedback divider
Road coarse adjustment so that the frequency departure of reference clock and feedback clock is rapidly entered within design requirement, terminates loop coarse mode；
After opening fine setting pattern, phaselocked loop is finely adjusted using the CP and lower order filter of high current structure, realizes that fine setting loop is quick
Locking；
When starting to receive data, phaselocked loop programming two modules of CP and LPF, CP and the high-order filter of low current structure are realized
Ripple device carries out loop fine setting, produces the good local oscillator clock signal of phase noise performance；
Above-mentioned frequency synthesizer, in sending mode, it provides high-frequency carrier signal for receive-transmit system, while realizes frequency
Rate modulation function；
When sending mode enables, frequency synthesizer carries out ring by automatic frequency control logic, DCO and feedback divider
Road coarse adjustment so that the frequency departure of reference clock and feedback clock is rapidly entered within design requirement, terminates loop coarse mode；
After opening fine setting pattern, phaselocked loop is finely adjusted using the CP and lower order filter of high current structure, realizes that fine setting loop is quick
Locking, produce high frequency carrier clock signal；
When starting to send data, phaselocked loop programming LPF modules, realize that fine setting loop disconnects, while analog-modulated voltage
Start to be input to the capacitance control terminal of DCO modulating capacitors, realize frequency modulation(PFM)；Simultaneously by Buffer modules in LPF by VCElectricity
Pressure is followed, and ensures that loop being capable of quick lock in during fine setting loop closure.
In said frequencies synthesizer, described automatic frequency control logic, mainly by TIMER, COUNTER, look-up table and
Four module compositions such as SAR_ADC, wherein reference clock REF_CLK is timed by TIMER, while COUNTER is in TIMER
Cycle count, the final frequency obtained between reference clock and feedback clock are carried out in the defined time to feedback clock FD_CLK
Relation, and the SAR_ADC corresponding with the frequency relation number of comparisons and saltus step direction are found out by look-up table, then pass through
SAR_ADC causes gate array Capacity control code to carry out corresponding saltus step；
In said frequencies synthesizer, described SAR_ADC, the number of comparisons provided based on look-up table and saltus step direction, from
Initial value is that " 1000 " start saltus step, and its output does not change after terminating saltus step, and produces the id signal for terminating loop coarse adjustment, should
Signal disconnects V as enable signalCVoltage, which assigns the operation of initial value and enabled fine setting loop, makes its start-up operation.
Said frequencies are integrated wherein, mainly by PFD（Phase frequency detector）、CP（Charge pump）、LPF（Low pass filter）、DCO
（Digital controlled oscillator）, the module group such as the decimal frequency divider realized of frequency divider and Sigma-Delta modulator and swallowing pulse technique
Into；
In said frequencies synthesizer, described charge pump, according to the mode of operation of frequency synthesizer, its charging and discharging currents can
It is large and small current programmed to carry out；
In said frequencies synthesizer, described low pass filter, according to the mode of operation of frequency synthesizer, its equivalent circuit
It can be changed, realize lower order filter, higher order filter and VCFollow the switching of three kinds of circuit structures；
In said frequencies synthesizer, described digital controlled oscillator, realize that wherein electric capacity includes door using LC cavity resonator structures
Array capacitor, the electric capacity and natural capacity realized warbled electric capacity, realize loop fine setting；
In the receiving mode, digital controlled oscillator is mainly that frequency synthesizer provides high frequency clock signal；
In the transmit mode, digital controlled oscillator mainly provides high-frequency carrier signal, and realizes frequency modulation function；
In said frequencies synthesizer, described decimal frequency divider, including Sigma-Delta modulator and swallow counter
Two modules, wherein Sigma-Delta modulator are converted to target fractional divisor factor the input signal P of swallow counter
And S, wherein S characterize big Frequency Dividing Factor N+1 frequency dividing number, P characterizes small Frequency Dividing Factor N frequency dividing number；
Compared with prior art, the advantage of the invention is that：
1st, there is the characteristics of quick frequency locking.Compared with traditional frequency synthesizer, the present invention is patrolled using automatic frequency control
The loop coarse adjustment technology realized is collected, the loop with programming LP bandwidth and CP charging and discharging currents finely tunes technology, and it is fast to realize loop
Speed locking.
2nd, with the good characteristic of output clock frequency high resolution and phase noise performance.With traditional frequency synthesizer phase
Than present invention employs loop bandwidth Programmable Technology, and reduction loop bandwidth optimizes phase noise after realizing loop-locking
Energy；Employ Sigma-Delta modulator simultaneously and swallowing pulse technique realizes high-precision decimal frequency divider, substantially increase output
The resolution ratio of clock frequency.
3rd, there is the wide characteristic of output clock frequency scope.Compared with traditional fraction frequency device, present invention employs door
Array capacitor technology, considerably increase DCO output clock frequency scope so that the frequency synthesizer realized using single DCO
Meet the wide range of frequencies demand for sending and receiving loop simultaneously.
Brief description of the drawings
Fig. 1 is a kind of structural representation of conventional phase locked loops frequency synthesizer in background of invention；
Fig. 2 is the structural representation of frequency synthesizer of the present invention；
Fig. 3 is the coarse mode structural representation of frequency synthesizer of the present invention；
Fig. 4 is frequency synthesizer SAR_ADC of the present invention searching algorithm；
Fig. 5 is the enabled fine setting loop structure schematic diagram of frequency synthesizer reception/sending mode of the present invention；
Fig. 6 is the fine setting loop structure schematic diagram that frequency synthesizer of the present invention enters reception pattern；
Fig. 7 is the structural representation that frequency synthesizer of the present invention enters sending mode.
Embodiment
The present invention is described in further details below with reference to the drawings and specific embodiments.
A kind of frequency synthesizer applied to wireless transceiver system shown in Figure 2, of the invention, it is main to include automatic frequency
Two parts of rate control logic and phaselocked loop.
With reference to shown in Fig. 2, when wireless transceiver system enables reception signal pattern, automatic frequency control logic, DCO and anti-
Feedback frequency dividing forms coarse tuning loop；First, bias voltage generation module provides V to DCOCInitial voltage, analog-modulated voltage module
A compliance voltage level is provided for modulating capacitor, DCO vibrations is produced the clock of a certain frequency and is exported.；
Meanwhile system will determine intended communication channel based on communication protocol, digital processing logic is according to reference clock frequency
The target Frequency Dividing Factor of decimal frequency divider is obtained with intended communication channel, and is supplied to Sigma-Delta modulator as input
Signal, it is realized with reference to swallow counter carries out target fractional frequency division to high frequency clock caused by DCO.
Reference clock REF_CLK is respectively supplied to Sigma-Delta modulator and automatic frequency control logic.For decimal
For frequency divider, Sigma-Delta carries out the output of P and S numerical value in the rising edge of each reference clock so that swallow counter
Realize the fractional frequency division that average division factor is target fractional divisor factor；For automatic frequency control logic, TIMER with
Carry out counting and timing on the basis of the REF_CLK cycles, while feedback clock FD_CLK was entered within the identical time by COUNTER
Row counts, and so as to obtain the frequency relation between feedback clock and reference clock, is obtained and the frequency relation pair by look-up table
The SAR_ADC answered transition times and saltus step direction, the saltus step of gate array Capacity control code is realized eventually through SAR_ADC, is changed
Become DCO output frequency so that reference clock REF_CLK and feedback clock FD_CLK frequency departure enter the mistake of default
In difference, loop coarse adjustment is completed, as shown in figure 4, wherein f1 is reference clock frequency, f2 is detailed SAR_ADC searching algorithm
Feedback clock frequency.
Assuming that gate array column capacitance is controlled using 4 control codes, deposited corresponding to described gate array Capacity control code
Device initial value is " 1000 ".
Within first search cycle, when automatic frequency control logic 200 is by comparison reference clock REF_CLK and feedback
Clock FD_CLK frequency relation, corresponding gate array Capacity control code is produced, such as when reference clock REF_CLK frequency f1 is big
When feedback clock frequency FD_CLK frequency f2, control code is jumped to " 0100 " by " 1000 "；Work as f1<During f2, control code by
" 1000 " jump to " 1100 ", and otherwise output control code is constant.
Within second search cycle, automatic frequency control logic 200 passes through comparison reference clock frequency f1 and newly anti-
Present clock frequency f2（Clock frequency caused by control code modulation DCO caused by first search cycle）, produce corresponding gate array
Column capacitance control code, for example, when first search cycle control code exports " 0100 ", work as f1>During f2, control code output is
“1000”；Work as f1<During f2, control code output is " 0110 "；As f1=f2, control code output is constant.In first search cycle
When control code output is " 1100 ", work as f1>During f2, control code output is " 1010 "；Work as f1<During f2, control code output is
“1110”；As f1=f2, control code output is constant.
By that analogy, after four search cycles, automatic frequency control logic will produce optimal gate array column capacitance control
Code processed, the control code will make it that reference clock frequency f1 and feedback clock frequency f2 error are minimum.Certainly, if completing four times
In search procedure, as long as there is reference clock frequency and feedback clock frequency error meets system design considerations, search operation is just
Can be immediately finished, and keep this time search for before control code it is constant.
After frequency synthesizer loop coarse adjustment terminates, coarse adjustment logic produces enable signal and disconnects bias voltage module to VCTax
Initial voltage operates, and phaselocked loop fine setting loop is closed into working condition, now carries out the CP of discharge and recharge and low using high current
Rank wave filter realizes the quick response to frequency departure, realizes fine setting loop quick lock in target frequency, its structure such as Fig. 5
It is shown.
After loop-locking is finely tuned, wireless transceiver system enters reception signal pattern, and the CP in loop is by charge and discharge TV university electricity
Stream switches to low current, while improves the exponent number of low pass filter, reaches the effect for reducing loop bandwidth, optimizes output clock
Phase noise performance, eventually reduce local oscillation signal and noise energy introduced in whole reception system, Fig. 6 describes entrance
The fine setting loop structure of reception pattern.
When wireless transceiver system enables sending mode, mode control signal will change DCO in natural capacity so that
Same VCUnder conditions of initial voltage, analog-modulated compliance voltage level and gate array capacitance structure, DCO, which is produced, meets transmission mould
The clock signal of frequency range needed for formula.
Equally, system will determine intended communication channel based on communication protocol, and digital processing logic is according to reference clock frequency
The target Frequency Dividing Factor of decimal frequency divider is obtained with intended communication channel, and is supplied to Sigma-Delta modulator as input
Signal, it is realized with reference to swallow counter carries out target fractional frequency division to high frequency clock caused by DCO.
The coarse tuning loop that automatic frequency control logic, DCO and feedback division are formed provides correct gate array electricity for DCO
Hold control code so that feedback clock frequency and reference clock frequency deviation enter in tolerance, specific coarse adjustment operation principle
It is similar with reception pattern.
After frequency synthesizer loop coarse adjustment terminates, coarse adjustment logic produces enable signal and disconnects bias voltage module to VCTax
Initial voltage operates, and phaselocked loop fine setting loop is closed into working condition, now carries out the CP of discharge and recharge and low using high current
Rank wave filter realizes the quick response to frequency departure, realizes fine setting loop quick lock in target frequency, its structure such as Fig. 5
It is shown.
After loop-locking is finely tuned, wireless transceiver system, which enters, sends signal mode, now programs LPF and realizes that loop breaks
Open, and by BUFFER by finely tune loop-locking when VCVoltage follow ensures that fine setting loop closes again to LPF input
Being capable of quick lock in during work.High frequency clock frequency caused by fine setting loop after disconnection no longer changes, characterize original number it is believed that
The simulative debugging voltage of breath is now input to the input of the modulating capacitor module in DCO as modulated signal, finally causes DCO
Realize and controlled in the enterprising line frequency modulation of high frequency clock, its modulation depth and modulation rate by analog-modulated voltage, Fig. 7 is described
The structural representation of sending mode lower frequency modulation.
The schematic diagram of each module and realization refer to all implementations with the function above.Electricity shown in those figures
Road is merely illustrative, and device is simply replaced to caused circuit variation and also belongs to protection scope of the present invention, guarantor of the invention
Shield scope should be defined by claims.
Claims (8)
1. a kind of loop programmable frequency synthesizer applied to wireless transceiver system, including automatic frequency control logic and lock phase
Two modules of ring moulds block, it is characterised in that：
In reception pattern, it provides correct local oscillator clock signal for receive-transmit system；
When reception pattern enables, frequency synthesizer passes through automatic frequency control logic, digital controlled oscillator DCO and feedback divider
Carry out loop coarse adjustment so that the frequency departure of reference clock and feedback clock is rapidly entered within design requirement, and it is thick to terminate loop
Mode transfer formula；After opening fine setting pattern, phaselocked loop is finely adjusted using the charge pump CP and lower order filter of high current structure, is realized
Finely tune loop quick lock in；
When starting to receive data, phaselocked loop two modules of programmed charges pump CP and low pass filter LPF, low current structure is realized
Charge pump CP and higher order filter carry out loop fine setting, produce the good local oscillator clock signal of phase noise performance；
In sending mode, it provides high-frequency carrier signal for receive-transmit system, while realizes frequency modulation function；
When sending mode enables, frequency synthesizer passes through automatic frequency control logic, digital controlled oscillator DCO and feedback divider
Carry out loop coarse adjustment so that the frequency departure of reference clock and feedback clock is rapidly entered within design requirement, and it is thick to terminate loop
Mode transfer formula；After opening fine setting pattern, phaselocked loop is finely adjusted using the charge pump CP and lower order filter of high current structure, is realized
Loop quick lock in is finely tuned, produces high frequency carrier clock signal；
When starting to send data, phaselocked loop programming low pass filter LPF modules, realize that fine setting loop disconnects, while simulate tune
Voltage processed starts to be input to the capacitance control terminal of digital controlled oscillator DCO modulating capacitors, realizes frequency modulation(PFM)；Pass through low pass filtered simultaneously
Buffer modules are by V in ripple device LPFCVoltage is followed, and ensures that loop being capable of quick lock in during fine setting loop closure.
2. frequency synthesizer as claimed in claim 1, it is characterised in that：Described automatic frequency control logic is by timer
Tetra- TIMER, counter COUNTER, look-up table and gradually-appoximant analog-digital converter SAR_ADC module compositions, wherein when referring to
Clock REF_CLK is timed by timer TIMER, at the same COUNTER within the time as defined in TIMER to feedback clock FD_
CLK carries out cycle count, the final frequency relation obtained between reference clock and feedback clock, and is found out by look-up table with being somebody's turn to do
The corresponding gradually-appoximant analog-digital converter SAR_ADC of frequency relation number of comparisons and saltus step direction, then by gradually forcing
Near-lying mode number converter SAR_ADC causes gate array Capacity control code to carry out corresponding saltus step.
3. frequency synthesizer as claimed in claim 2, it is characterised in that：Described gradually-appoximant analog-digital converter SAR_ADC
The number of comparisons provided based on look-up table and saltus step direction, the saltus step since initial value is " 1000 ", it is exported after terminating saltus step
Do not change, and produce the id signal for terminating loop coarse adjustment, the signal disconnects V as enable signalCVoltage assigns the behaviour of initial value
Make and enabled fine setting loop makes its start-up operation.
4. frequency synthesizer as claimed in claim 1, it is characterised in that：Described phaselocked loop is by phase frequency detector PFD, electric charge
Pump CP, low pass filter LPF, digital controlled oscillator DCO, frequency divider and Sigma-Delta modulator and swallowing pulse technique are realized
The part of decimal frequency divider six composition.
5. frequency synthesizer as claimed in claim 4, it is characterised in that：Described charge pump is according to the work of frequency synthesizer
Pattern, realize large and small charging and discharging currents programming.
6. frequency synthesizer as claimed in claim 4, it is characterised in that：Described low pass filter is according to frequency synthesizer
Mode of operation, realize lower order filter, higher order filter and VCFollow the switching of three kinds of circuit structures.
7. frequency synthesizer as claimed in claim 4, it is characterised in that：Described digital controlled oscillator uses LC cavity resonator structures
Realize, wherein electric capacity includes gate array column capacitance Varactor-Array, realizes warbled modulating capacitor Modulater-
Varactor, the electric capacity and natural capacity for realizing loop fine setting；
In the receiving mode, digital controlled oscillator provides high frequency clock signal for frequency synthesizer；
In the transmit mode, digital controlled oscillator provides high-frequency carrier signal, and realizes frequency modulation function.
8. frequency synthesizer as claimed in claim 4, it is characterised in that：Described decimal frequency divider includes Sigma-Delta
Target fractional divisor factor is converted to and gulped down by two modules of modulator and swallow counter, wherein Sigma-Delta modulator
The input signal P and S of pulse counter, the big Frequency Dividing Factor N+1 of wherein S signs frequency dividing number, P characterize small Frequency Dividing Factor N's
Divide number.
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| CN104796139B (en) * | 2015-04-22 | 2017-12-26 | 西安电子科技大学 | A kind of stable voltage controlled oscillator of fast frequency |
| CN106817125A (en) * | 2016-12-23 | 2017-06-09 | 长沙景嘉微电子股份有限公司 | One kind is applied to automatic frequency control（AFC）Loop coarse adjustment algorithm |
| CN106817126B (en) * | 2016-12-23 | 2020-07-10 | 长沙景美集成电路设计有限公司 | High-precision digital frequency locking ring with wide output frequency range and high frequency locking speed |
| CN112953520A (en) * | 2021-03-23 | 2021-06-11 | 北京理工大学 | Phase-locked loop all-digital frequency band switching technology based on successive approximation logic |
| CN114264325B (en) * | 2021-12-15 | 2023-07-04 | 江南大学 | Multimode microwave detection system and method based on rapid frequency hopping technology |
| CN116405058B (en) * | 2023-06-09 | 2023-09-29 | 中星联华科技（北京）有限公司 | Fast frequency hopping locking circuit and operation method thereof |
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| US5493700A (en) * | 1993-10-29 | 1996-02-20 | Motorola | Automatic frequency control apparatus |
| CN101938276A (en) * | 2010-08-26 | 2011-01-05 | 上海南麟电子有限公司 | Phase frequency detector (PFD), phase frequency detection method thereof, phase locking loop (PLL) and frequency synthesizer |
| CN102931918A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Frequency channel programmable LC_digitally controlled oscillator (DCO) circuit structure |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
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| KR100717134B1 (en) * | 2005-07-26 | 2007-05-10 | 인티그런트 테크놀로지즈(주) | Automatic frequency control loop circuit |
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| US5493700A (en) * | 1993-10-29 | 1996-02-20 | Motorola | Automatic frequency control apparatus |
| CN101938276A (en) * | 2010-08-26 | 2011-01-05 | 上海南麟电子有限公司 | Phase frequency detector (PFD), phase frequency detection method thereof, phase locking loop (PLL) and frequency synthesizer |
| CN102931918A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Frequency channel programmable LC_digitally controlled oscillator (DCO) circuit structure |
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