CN104242930A - Frequency synthesizer for wireless receiving and sending system - Google Patents
Frequency synthesizer for wireless receiving and sending system Download PDFInfo
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- CN104242930A CN104242930A CN201410454548.3A CN201410454548A CN104242930A CN 104242930 A CN104242930 A CN 104242930A CN 201410454548 A CN201410454548 A CN 201410454548A CN 104242930 A CN104242930 A CN 104242930A
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Abstract
The invention discloses a frequency synthesizer for a wireless receiving and sending system. The frequency synthesizer for the wireless receiving and sending system comprises an automatic frequency control module and two modules of a phase-locked loop, in the rough adjustment mode, the frequency relation between a reference clock and a feedback clock is obtained by means of the automatic frequency control module through logic comparison, so that a corresponding gate array capacitance control code is generated rapidly, the oscillation frequency of a digital-controlled oscillator (DCO) is modulated, and finally the frequency difference between the reference clock and the feedback clock is made to meet the requirement for frequency deviation of rough adjustment; in the fine adjustment mode, rapid locking of a target output clock frequency is achieved by means of the phase-lock loop through the charge pump (CP) module and the low pass filter (LPF) module . The frequency synthesizer for the wireless receiving and sending system has the advantages that the loop locking speed is high, the output clock frequency range is wide, the frequency resolution is high, and the phase noise performance is good. In this way, the frequency synthesizer for the wireless receiving and sending system is obtained with the single DCO.
Description
Technical field
The present invention relates generally to wireless communication field, can be applicable to the receive-transmit system of radio communication, particularly relate to a kind of frequency synthesizer being applied to wireless transceiver system, this structure make to adopt the frequency synthesizer of single digital controlled oscillator to meet the challenging needs such as reference clock frequency that receive-transmit system proposes is wide, resolution is high and noiseproof feature is good become reality.
Background technology
Frequency synthesizer is as the nucleus module of in wireless transceiver system, and it is mainly the high-frequency local oscillation signal receiving loop and provide frequency interval corresponding with sending loop, provides high-frequency carrier signal and realizes frequency modulation(FM) simultaneously for sending loop.The current communications field growing, radio-frequency (RF) communication system is to the operating frequency range of frequency synthesizer, frequency resolution, locking time and noise perfomiance requirements also increasingly stringent thereupon.
The frequency synthesizer of traditional phase-locked loop composition, as shown in Figure 1, primarily of part compositions such as phase frequency detector, loop filter, voltage controlled oscillator and frequency dividers.For this structure, its output clock frequency meets Fre_vco=N*Fre_ref.In order to obtain wide frequency range, precision is high and phase noise performance is good clock signal, frequency synthesizer generally adopts and reduces reference clock frequency Fre_ref technology to improve the frequency resolution of output clock; Adopt and increase the frequency range that Frequency Dividing Factor N realizes output clock.But, adopt comparatively small frequency reference clock, mean that the loop bandwidth of frequency synthesizer needs to reduce thereupon, cause the loop-locking time can be thereupon elongated; Meanwhile, narrower loop bandwidth can make loop inadequate to the phase noise reduction ability of VCO, reduces VCO phase noise performance; Adopt large Frequency Dividing Factor N, the phase noise making phase noise contribution be proportional to other submodules of Frequency Dividing Factor N increases, and worsens frequency synthesizer overall noise.Owing to being difficult to accomplish compromise process on the Key Performance Indicators such as loop bandwidth, phase noise and locking time, the performance requirements such as modern communications field is fast to the locking time proposed, operating frequency range, frequency resolution are high and phase noise performance is good that cause legacy frequencies synthesizer not meet.
In addition, in traditional frequency synthesizer, voltage controlled oscillator operating frequency range is limited, in order to satisfied transmission loop and reception loop are to the different demands of high frequency clock frequency range, double pressure-controlled oscillator structure generally can be adopted to design, so greatly increase the design area of chip, add chip design cost.
In order to solve the problems of the technologies described above, the present invention proposes a kind of frequency synthesizer being applied to receive-transmit system.This frequency synthesizer mainly comprises automatic frequency control logic and phase-locked loop two modules, wherein automatic frequency control logic, DCO and feedback division formation coarse tuning loop can complete loop coarse adjustment fast, ensures that the frequency departure of reference clock and feedback clock enters in permissible range; Then by programming CP and LPF module, large charging and discharging currents, lower order filter and large loop bandwidth make phase-locked loop finely tune loop output clock quick lock in target frequency, and above-mentioned technology substantially reduces locking time; Simultaneously by programming CP and LPF module, after frequency synthesizer is locked, loop bandwidth diminishes, and charging and discharging currents reduces, and filter order improves, and greatly improves the phase noise performance of output clock; This frequency synthesizer adopts gate array capacitance technology, and the clock realizing multiband wide frequency ranges exports, and the frequency synthesizer achieved based on single DCO structure meets the demand of receive-transmit system to clock output frequency wide ranges.
Described frequency synthesizer, under the condition not reducing reference clock frequency, the decimal frequency divider adopting Sigma-Delta modulator and swallowing pulse technique to realize ensure that receive-transmit system is while clock signal frequency wide ranges, obtains the benefit that clock signal frequency resolution is high.
Summary of the invention
The problem to be solved in the present invention is: for prior art Problems existing, the invention provides one and be applied to wireless transceiver system frequency synthesizer, this frequency synthesizer achieves and adopts single oscillator and provide the clock of wide frequency ranges to export, and satisfied reception and transmitting system are to the demand of wide reference clock frequency; This structure adopts coarse tuning loop technology, regulating ring road technique and V simultaneously
ccompose initial value technology, achieve target frequency quick lock in, meet current wireless transceiver system to locking time, fast frequency-hopped index demand; This structure also adopts loop bandwidth Programmable Technology, Fractional Frequency-Dividing Technology simultaneously, achieves the high frequency clock that frequency resolution is high, phase noise performance is good and exports.
For realizing above-mentioned technical problem, the solution that the present invention proposes is: a kind of frequency synthesizer being applied to wireless transceiver system, is characterized in that: comprise automatic frequency control logic and phase-locked loop module two modules;
Above-mentioned frequency synthesizer, when receiving mode, it provides correct local oscillator clock signal for receive-transmit system;
When receiving mode is enable, frequency synthesizer carries out loop coarse adjustment by automatic frequency control logic, DCO and feedback divider, and the frequency departure of reference clock and feedback clock is entered within designing requirement fast, terminates loop coarse mode; After opening fine setting pattern, phase-locked loop adopts the CP of big current structure and lower order filter to finely tune, and realizes fine setting loop quick lock in;
When starting to receive data, phase-locked loop programming CP and LPF two modules, the CP and the higher order filter that realize small area analysis structure carry out loop fine setting, produce the local oscillator clock signal that phase noise performance is good;
Above-mentioned frequency synthesizer, when sending mode, it provides high-frequency carrier signal for receive-transmit system, realizes frequency modulation function simultaneously;
When sending mode is enable, frequency synthesizer carries out loop coarse adjustment by automatic frequency control logic, DCO and feedback divider, and the frequency departure of reference clock and feedback clock is entered within designing requirement fast, terminates loop coarse mode; After opening fine setting pattern, phase-locked loop adopts the CP of big current structure and lower order filter to finely tune, and realizes fine setting loop quick lock in, produces high frequency carrier clock signal;
When starting to send data, phase-locked loop programming LPF module, realize fine setting loop and disconnect, analog-modulated voltage starts the capacitance control end being input to DCO modulating capacitor simultaneously, realizes frequency modulation(FM); Simultaneously by Buffer module in LPF by V
cvoltage is followed, and when ensureing that fine setting loop closes, loop can quick lock in.
In said frequencies synthesizer, described automatic frequency control logic, primarily of TIMER, COUNTER, four module compositions such as look-up table and SAR_ADC, wherein reference clock REF_CLK carries out timing by TIMER, COUNTER carries out cycle count to feedback clock FD_CLK in TIMER official hour simultaneously, frequency relation between final acquisition reference clock and feedback clock, and number of comparisons and the saltus step direction of the SAR_ADC corresponding with this frequency relation is found out by look-up table, then gate array Capacity control code is made to carry out corresponding saltus step by SAR_ADC,
In said frequencies synthesizer, described SAR_ADC, the number of comparisons provided based on look-up table and saltus step direction, saltus step from initial value is " 1000 ", after terminating saltus step, its output does not change, and produces the id signal terminating loop coarse adjustment, and this signal disconnects V as enable signal
coperation and the enable fine setting loop of voltage tax initial value make it start working.
Said frequencies is comprehensive wherein, primarily of PFD(phase frequency detector), CP(charge pump), LPF(low pass filter), DCO(digital controlled oscillator), the module composition such as the decimal frequency divider that realizes of frequency divider and Sigma-Delta modulator and swallowing pulse technique;
In said frequencies synthesizer, described charge pump, according to the mode of operation of frequency synthesizer, its charging and discharging currents can carry out large and small current programmed;
In said frequencies synthesizer, described low pass filter, according to the mode of operation of frequency synthesizer, its equivalent electric circuit can change, and realizes lower order filter, higher order filter and V
cfollow the switching of three kinds of circuit structures;
In said frequencies synthesizer, described digital controlled oscillator, adopts LC cavity resonator structure to realize, wherein the electric capacity electric capacity and the natural capacity that comprise gate array electric capacity, realize warbled electric capacity, realize loop fine setting;
In the receiving mode, digital controlled oscillator is mainly frequency synthesizer and provides high frequency clock signal;
In the transmit mode, digital controlled oscillator mainly provides high-frequency carrier signal, and realizes frequency modulation function;
In said frequencies synthesizer, described decimal frequency divider, comprise Sigma-Delta modulator and swallow counter two modules, wherein the target fractional frequency division factor is converted to input signal P and S of swallow counter by Sigma-Delta modulator, wherein S characterizes the frequency division number of times of large Frequency Dividing Factor N+1, and P characterizes the frequency divider number of times of little Frequency Dividing Factor N;
Compared with prior art, the invention has the advantages that:
1, there is the feature of quick frequency locking.Compared with traditional frequency synthesizer, the loop coarse adjustment technology that the present invention adopts automatic frequency control logic to realize, with the loop fine setting technology of programming LP bandwidth sum CP charging and discharging currents, achieves loop quick lock in.
?2, there is the characteristic that output clock frequency resolution is high and phase noise performance is good.Compared with traditional frequency synthesizer, present invention employs loop bandwidth Programmable Technology, reduce loop bandwidth after realizing loop-locking and optimize phase noise performance; Have employed Sigma-Delta modulator and swallowing pulse technique realizes high accuracy decimal frequency divider simultaneously, substantially increase the resolution of output clock frequency.
3, there is the characteristic of output clock wide frequency range.Compared with traditional fraction frequency device, present invention employs gate array capacitance technology, considerably increase the output clock frequency range of DCO, make the frequency synthesizer adopting single DCO to realize meet the wide range of frequencies demand sending and receive loop simultaneously.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of conventional phase locked loops frequency synthesizer in background technology of the present invention;
Fig. 2 is the structural representation of frequency synthesizer of the present invention;
Fig. 3 is the coarse mode structural representation of frequency synthesizer of the present invention;
Fig. 4 is the searching algorithm of frequency synthesizer SAR_ADC of the present invention;
Fig. 5 is the enable regulating ring line structure schematic diagram of frequency synthesizer reception/sending mode of the present invention;
Fig. 6 is the regulating ring line structure schematic diagram that frequency synthesizer of the present invention enters receiving mode;
Fig. 7 is the structural representation that frequency synthesizer of the present invention enters sending mode.
Embodiment
Below with reference to the drawings and specific embodiments, the present invention is described in further details.
Shown in Figure 2, a kind of frequency synthesizer being applied to wireless transceiver system of the present invention, mainly comprises automatic frequency control logic and phase-locked loop two parts.
Shown in composition graphs 2, when the enable Received signal strength pattern of wireless transceiver system, automatic frequency control logic, DCO and feedback division form coarse tuning loop; First, bias voltage generation module provides V to DCO
cinitial voltage, analog-modulated voltage module provides a compliance voltage level for modulating capacitor, and the clock making DCO vibration produce a certain frequency exports.；
Simultaneously, system will based on communication protocol determination intended communication channel, digital processing logic obtains the target Frequency Dividing Factor of decimal frequency divider according to reference clock frequency and intended communication channel, and being supplied to Sigma-Delta modulator as input signal, its high frequency clock realized DCO produces in conjunction with swallow counter carries out target fractional frequency division.
Reference clock REF_CLK is supplied to Sigma-Delta modulator and automatic frequency control logic respectively.For decimal frequency divider, Sigma-Delta carries out P and S numerical value at the rising edge of each reference clock and exports, swallow counter is realized fractional frequency division that average division factor is the target fractional frequency division factor, for automatic frequency control logic, TIMER with the REF_CLK cycle for benchmark carries out counting and timing, by COUNTER, feedback clock FD_CLK is counted within the identical time simultaneously, thus the frequency relation obtained between feedback clock and reference clock, transition times and the saltus step direction of the SAR_ADC corresponding with this frequency relation is obtained by look-up table, the saltus step of gate array Capacity control code is realized eventually through SAR_ADC, change the output frequency of DCO, the frequency departure of reference clock REF_CLK and feedback clock FD_CLK is made to enter in the error of default, complete loop coarse adjustment, the searching algorithm of detailed SAR_ADC as shown in Figure 4, wherein f1 is reference clock frequency, f2 is feedback clock frequency.
Suppose that gate array electric capacity adopts 4 control codes to control, the register initial value of described gate array Capacity control code correspondence is " 1000 ".
Within first search cycle, automatic frequency control logic 200 is by comparing the frequency relation of reference clock REF_CLK and feedback clock FD_CLK, produce corresponding gate array Capacity control code, such as when the frequency f 1 of reference clock REF_CLK is greater than the frequency f 2 of feedback clock frequency FD_CLK, control code is jumped to " 0100 " by " 1000 "; As f1<f2, control code is jumped to " 1100 " by " 1000 ", otherwise it is constant to export control code.
Within second search cycle, the clock frequency that automatic frequency control logic 200 is produced by the control code modulation DCO comparing reference clock frequency f1 and new feedback clock frequency f 2(first search cycle generation), produce corresponding gate array Capacity control code, such as, when first search cycle control code exports " 0100 ", as f1>f2, control code exports as " 1000 "; As f1<f2, control code exports as " 0110 "; As f1=f2, control code exports constant.When first search cycle control code exports as " 1100 ", as f1>f2, control code exports as " 1010 "; As f1<f2, control code exports as " 1110 "; As f1=f2, control code exports constant.
By that analogy, after four search cycles, automatic frequency control logic will produce optimum gate array Capacity control code, and this control code will make the error of reference clock frequency f1 and feedback clock frequency f 2 minimum.Certainly, if complete in four search procedures, as long as occur that reference clock frequency and feedback clock frequency error meet system design considerations, search operation will terminate immediately, and keeps the control code before this search constant.
After the coarse adjustment of frequency synthesizer loop terminates, coarse adjustment logic produces enable signal and disconnects bias voltage module to V
ctax initial voltage operation, phase-locked loop fine setting loop is closed into operating state, now adopt big current to carry out CP and the quick response of lower order filter realization to frequency departure of discharge and recharge, achieve fine setting loop quick lock in target frequency, its structure as shown in Figure 5.
When after fine setting loop-locking, wireless transceiver system enters Received signal strength pattern, discharge and recharge big current is switched to small area analysis by the CP in loop, improve the exponent number of low pass filter simultaneously, reach the effect reducing loop bandwidth, optimize the phase noise performance of output clock, eventually reduce local oscillation signal and introduce noise energy in whole receiving system, Fig. 6 describes the regulating ring line structure entering receiving mode.
When the enable sending mode of wireless transceiver system, the natural capacity that mode control signal will change in DCO, makes at same V
cunder the condition of initial voltage, analog-modulated compliance voltage level and gate array capacitance structure, DCO produces the clock signal of the frequency range met needed for sending mode.
Equally, system will based on communication protocol determination intended communication channel, digital processing logic obtains the target Frequency Dividing Factor of decimal frequency divider according to reference clock frequency and intended communication channel, and being supplied to Sigma-Delta modulator as input signal, its high frequency clock realized DCO produces in conjunction with swallow counter carries out target fractional frequency division.
The coarse tuning loop that automatic frequency control logic, DCO and feedback division are formed is that DCO provides correct gate array Capacity control code, make feedback clock frequency and reference clock frequency deviation enter in tolerance, concrete coarse adjustment operation principle and receiving mode similar.
After the coarse adjustment of frequency synthesizer loop terminates, coarse adjustment logic produces enable signal and disconnects bias voltage module to V
ctax initial voltage operation, phase-locked loop fine setting loop is closed into operating state, now adopt big current to carry out CP and the quick response of lower order filter realization to frequency departure of discharge and recharge, achieve fine setting loop quick lock in target frequency, its structure as shown in Figure 5.
When after fine setting loop-locking, wireless transceiver system enters transmission signal mode, and the LPF that now programmes realizes loop and disconnects, and by BUFFER by V during fine setting loop-locking
cvoltage follow to the input of LPF, ensure fine setting loop again Operating In Persistent Current Mode time can quick lock in.The high frequency clock frequency that fine setting loop after disconnection produces no longer changes, the simulative debugging voltage characterizing primary data information (pdi) is now input to the input of the modulating capacitor module in DCO as modulation signal, DCO is finally made to realize in the enterprising line frequency modulation of high frequency clock, its modulation depth and modulation rate are by analog-modulated voltage control, and Fig. 7 describes the structural representation of sending mode lower frequency modulation.
The schematic diagram of each module refers to all implementations with this function with realizing above.Circuit shown in each figure is only example above, and device is replaced simply caused circuit variation and also belong to protection scope of the present invention, protection scope of the present invention should be as the criterion with claims.
Claims (10)
1. be applied to a frequency synthesizer for receive-transmit system, it is characterized in that: comprise automatic frequency control logic and phase-locked loop module two modules.
2. frequency synthesizer as claimed in claim 1, is characterized in that: when receiving mode, and it provides correct local oscillator clock signal for receive-transmit system;
When receiving mode is enable, frequency synthesizer carries out loop coarse adjustment by automatic frequency control logic, digital controlled oscillator (DCO) and feedback divider, the frequency departure of reference clock and feedback clock is entered within designing requirement fast, terminates loop coarse mode; After opening fine setting pattern, phase-locked loop adopts the CP of big current structure and lower order filter to finely tune, and realizes fine setting loop quick lock in;
When starting to receive data, phase-locked loop programming CP and LPF two modules, the CP and the higher order filter that realize small area analysis structure carry out loop fine setting, produce the local oscillator clock signal that phase noise performance is good.
3. frequency synthesizer as claimed in claim 1, is characterized in that: when sending mode, and it provides high-frequency carrier signal for receive-transmit system, realizes frequency modulation function simultaneously;
When sending mode is enable, frequency synthesizer carries out loop coarse adjustment by automatic frequency control logic, DCO and feedback divider, and the frequency departure of reference clock and feedback clock is entered within designing requirement fast, terminates loop coarse mode; After opening fine setting pattern, phase-locked loop adopts the CP of big current structure and lower order filter to finely tune, and realizes fine setting loop quick lock in, produces high frequency carrier clock signal;
When starting to send data, phase-locked loop programming LPF module, realize fine setting loop and disconnect, analog-modulated voltage starts the capacitance control end being input to DCO modulating capacitor simultaneously, realizes frequency modulation(FM); Simultaneously by Buffer module in LPF by V
cvoltage is followed, and when ensureing that fine setting loop closes, loop can quick lock in.
4. frequency synthesizer as claimed in claim 1, it is characterized in that: described automatic frequency control logic is primarily of TIMER, COUNTER, four module compositions such as look-up table and SAR_ADC, wherein reference clock REF_CLK carries out timing by TIMER, COUNTER carries out cycle count to feedback clock FD_CLK in TIMER official hour simultaneously, frequency relation between final acquisition reference clock and feedback clock, and number of comparisons and the saltus step direction of the SAR_ADC corresponding with this frequency relation is found out by look-up table, then gate array Capacity control code is made to carry out corresponding saltus step by SAR_ADC.
5. automatic frequency control logic as claimed in claim 4, it is characterized in that: the number of comparisons that described SAR_ADC mainly provides based on look-up table and saltus step direction, saltus step from initial value is " 1000 ", after terminating saltus step, its output does not change, and producing the id signal terminating loop coarse adjustment, this signal disconnects V as enable signal
coperation and the enable fine setting loop of voltage tax initial value make it start working.
6. frequency synthesizer as claimed in claim 1, is characterized in that: described phase-locked loop is primarily of PFD(phase frequency detector), CP(charge pump), LPF(low pass filter), DCO(digital controlled oscillator), the module composition such as the decimal frequency divider that realizes of frequency divider and Sigma-Delta modulator and swallowing pulse technique.
7. phase-locked loop as claimed in claim 6, is characterized in that: described charge pump is mainly according to the mode of operation of frequency synthesizer, and its charging and discharging currents can carry out large and small current programmed.
8. phase-locked loop as claimed in claim 6, is characterized in that: described low pass filter is mainly according to the mode of operation of frequency synthesizer, and its equivalent electric circuit can change, and realizes lower order filter, higher order filter and V
cfollow the switching of three kinds of circuit structures.
9. phase-locked loop as claimed in claim 6, it is characterized in that: described digital controlled oscillator mainly adopts LC cavity resonator structure to realize, wherein electric capacity comprise gate array electric capacity (Varactor Array), realize warbled modulating capacitor (Modulater Varactor), realize loop fine setting electric capacity and natural capacity;
In the receiving mode, digital controlled oscillator is mainly frequency synthesizer and provides high frequency clock signal;
In the transmit mode, digital controlled oscillator mainly provides high-frequency carrier signal, and realizes frequency modulation function.
10. phase-locked loop as claimed in claim 6, it is characterized in that: described decimal frequency divider mainly comprises Sigma-Delta modulator and swallow counter two modules, wherein the target fractional frequency division factor is converted to input signal P and S of swallow counter by Sigma-Delta modulator, wherein S characterizes the frequency division number of times of large Frequency Dividing Factor N+1, and P characterizes the frequency divider number of times of little Frequency Dividing Factor N.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796139A (en) * | 2015-04-22 | 2015-07-22 | 西安电子科技大学 | Quick frequency stabilization voltage-controlled oscillator |
| CN106817126A (en) * | 2016-12-23 | 2017-06-09 | 长沙景美集成电路设计有限公司 | A kind of fireballing high accuracy number FLL of reference frequency output frequency locking wide |
| CN106817125A (en) * | 2016-12-23 | 2017-06-09 | 长沙景嘉微电子股份有限公司 | One kind is applied to automatic frequency control（AFC）Loop coarse adjustment algorithm |
| CN112953520A (en) * | 2021-03-23 | 2021-06-11 | 北京理工大学 | Phase-locked loop all-digital frequency band switching technology based on successive approximation logic |
| CN114264325A (en) * | 2021-12-15 | 2022-04-01 | 江南大学 | Multimode microwave detection system and method based on rapid frequency hopping technology |
| CN116405058A (en) * | 2023-06-09 | 2023-07-07 | 中星联华科技（北京）有限公司 | Fast frequency hopping locking circuit and operation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5493700A (en) * | 1993-10-29 | 1996-02-20 | Motorola | Automatic frequency control apparatus |
| US20070025491A1 (en) * | 2005-07-26 | 2007-02-01 | Integrant Technologies Inc. | Automatic frequency control loop circuit |
| CN101938276A (en) * | 2010-08-26 | 2011-01-05 | 上海南麟电子有限公司 | Phase frequency detector (PFD), phase frequency detection method thereof, phase locking loop (PLL) and frequency synthesizer |
| CN102931918A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Frequency channel programmable LC_digitally controlled oscillator (DCO) circuit structure |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
-
2014
- 2014-09-09 CN CN201410454548.3A patent/CN104242930B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5493700A (en) * | 1993-10-29 | 1996-02-20 | Motorola | Automatic frequency control apparatus |
| US20070025491A1 (en) * | 2005-07-26 | 2007-02-01 | Integrant Technologies Inc. | Automatic frequency control loop circuit |
| CN101938276A (en) * | 2010-08-26 | 2011-01-05 | 上海南麟电子有限公司 | Phase frequency detector (PFD), phase frequency detection method thereof, phase locking loop (PLL) and frequency synthesizer |
| CN102931918A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Frequency channel programmable LC_digitally controlled oscillator (DCO) circuit structure |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796139A (en) * | 2015-04-22 | 2015-07-22 | 西安电子科技大学 | Quick frequency stabilization voltage-controlled oscillator |
| CN104796139B (en) * | 2015-04-22 | 2017-12-26 | 西安电子科技大学 | A kind of stable voltage controlled oscillator of fast frequency |
| CN106817126A (en) * | 2016-12-23 | 2017-06-09 | 长沙景美集成电路设计有限公司 | A kind of fireballing high accuracy number FLL of reference frequency output frequency locking wide |
| CN106817125A (en) * | 2016-12-23 | 2017-06-09 | 长沙景嘉微电子股份有限公司 | One kind is applied to automatic frequency control（AFC）Loop coarse adjustment algorithm |
| CN106817126B (en) * | 2016-12-23 | 2020-07-10 | 长沙景美集成电路设计有限公司 | High-precision digital frequency locking ring with wide output frequency range and high frequency locking speed |
| CN112953520A (en) * | 2021-03-23 | 2021-06-11 | 北京理工大学 | Phase-locked loop all-digital frequency band switching technology based on successive approximation logic |
| CN114264325A (en) * | 2021-12-15 | 2022-04-01 | 江南大学 | Multimode microwave detection system and method based on rapid frequency hopping technology |
| CN116405058A (en) * | 2023-06-09 | 2023-07-07 | 中星联华科技（北京）有限公司 | Fast frequency hopping locking circuit and operation method thereof |
| CN116405058B (en) * | 2023-06-09 | 2023-09-29 | 中星联华科技（北京）有限公司 | Fast frequency hopping locking circuit and operation method thereof |
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