CN101582695A - Phase lock loop frequency synthesizer with quick lock function - Google Patents
Phase lock loop frequency synthesizer with quick lock function Download PDFInfo
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- CN101582695A CN101582695A CNA200910040382XA CN200910040382A CN101582695A CN 101582695 A CN101582695 A CN 101582695A CN A200910040382X A CNA200910040382X A CN A200910040382XA CN 200910040382 A CN200910040382 A CN 200910040382A CN 101582695 A CN101582695 A CN 101582695A
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Abstract
The invention discloses a phase lock loop frequency synthesizer with quick lock function, comprising a phase lock loop (101) and a quick lock logic unit (102). The phase lock loop (101) consists of a frequency discrimination phase discriminator (501), a charge pump (502), a voltage control oscillator (503), a programmable multimode frequency divider (504) and a loop filter (511). The quick lock logic unit (102) consists of a logic control circuit (508), a unit gain follower (509) and a phase lock monitor (510). The invention realizes the quick lock of the frequency synthesizer, and the quick lock logic unit has simple structure and low power consumption. The invention is especially suitable for a wireless radio frequency communication system which requires low power consumption and quick lock.
Description
Technical field
The invention belongs to the technical field of electronic communication or less radio-frequency, specifically be meant a kind of phase-locked loop frequency integrator with quick lock in function.
Background technology:
At present, phase-locked loop frequency integrator is widely used in electronic communication and wireless radio-frequency field, has become the indispensable module of Modern wireless communication.At the digital mobile system that requires to combine frequently quick lock in, modern twireless radio-frequency communication such as vehicle-mounted radio-frequency receiving system and frequency-hopping system the inside, the quick lock in of combining is a very important index frequently.Can provide big loop bandwidth because fractional phase locked loop is combined frequently when realizing narrow channel spacing, compare, have the fast advantage of loop-locking speed, take some other technologies simultaneously, phase noise and also comprehensive frequently poor unlike integer with reference to burr with the integer phase-locked loop.Just because of mark is combined frequently and had lock speed and wait these advantages soon, the modern radio-frequency radio communication adopts mark to combine frequently basically, and the locking time that traditional mark is combined frequently, the requirement for most systems was enough.But, development along with technology, many radio transceiver machines need a broadband to combine frequently and the local oscillations generator of a complexity comes to provide various local oscillation signals for Receiver And Transmitter, or system such as picture PHS etc. needs locking time faster, a conspicuous method increases the sensitivity of voltage controlled oscillator (VCO) exactly, but when the sensitivity of VCO increases, phase noise characteristic will worsen variation, frequently combine for low supply voltage, the deterioration of phase noise makes by increasing purpose that VCO sensitivity reaches quick lock in and makes that to combine frequently be impossible be applied in the system that low phase noise requires to go.Therefore, realize the quick lock in of frequency synthesizer, just must adopt other loop quick lock in technology, satisfy low phase noise simultaneously and, and guarantee loop stability with reference to the burr requirement.
Existing loop quick lock in technology mainly contains following two classes:
1, VCO preconditioning pattern (VCO pre-tuning).By selecting VCO inductance or switched capacitor array to change the VCO frequency of oscillation, also claim automatic frequency correction (AFC:adaptive frequency calibration), as shown in Figure 1; Or reach the purpose of loop quick lock in by the control voltage that DAC pre-sets VCO.Pertinent literature has: [1] Han-ilLee, Je-Kwang Cho, and Kun-Seok Lee, etc, " a sigma-delta fractinal-N FrequencySynthesizer Using a Wide-band Integrated VCO and a Fast AFC Technique forGSM/GPRS/WCDMA Applications " IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.39, NO.7, JULY 2004.[2]Chi-Wa?Lo?and?Howard?Cam?Luong，“a?1.5V?900-MHz?Monolithic?CMOSFast-Switching?Frequency?Synthesizer?for?Wireless?Application”IEEE?JOURNAL?OFSOLID-STATE?CIRCUITS，VOL.37，NO.4，APRIL?2004。AFC pattern deficiency is to equal AFC time and normal locking time of sum locking time, and AFC control circuit scale is bigger, has directly increased power consumption and complexity, is not inconsistent with modern low-power consumption, low cost; The deficiency that pre-sets by DAC is to need a DAC module, and the noise of DAC directly is added on the VCO control line, and the precision of DAC directly influences the locking time of loop.
2, aero mode (speed-up mode).Basic thought is exactly by the switching between different loop bandwidths or gain, low noise after realizing quick lock in and locking, frequency is combined in frequency switching locking process and is operated under the bigger aero mode state of loop bandwidth, and loop is by the normal mode operating state of big loop bandwidth aero mode state transformation to less loop bandwidth after locking or after the regular hour.As shown in Figure 2, pertinent literature has: [1] Kyoungho Woo, Yong Liu, Eunsoo Nam etc, " Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modesof Differing Bandwidths " IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.43, NO.2, FEBRUARY 2008.[2]KUO-Hsing?Cheng，Wei-Bin?Yang，and?Cheng-Ming?Ying，“ADual-Slope?Phase?Frequency?Detector?and?Charge?Pump?Architecture?to?Achieve?FastLocking?of?Phase-Locked?Loop”IEEE?TRANSACTIONS?ON?CIRCUITS?AND?SYSTENS-II：ANANLOG?AND?DIGITAL?SIGNAL?PROCESSING，VOL.50，NO.11，NOVEMBER?2003。[3]Ching-YuanYang，and?Shen-Iuan?Liu，“Fast-Switching?Frequancy?with?a?Discriminator-AidedPhase?Detector”IEEE?JOURNAL?OF?SOLID-STATE?CIRCUITS，VOL.35，NO.10，OCTOBER2000。The weak point of aero mode be exactly when loop by acceleration mode when the normal mode state switches, the voltage control line of VCO can be subjected to bigger disturbance, and because that loop gain under the aero mode state or zero, limit change is big inadequately, the loop-locking time is still limited.
Summary of the invention
The object of the present invention is to provide a kind of processing that can realize integer is combined frequently and mark is combined frequently quick lock in, simple in structure, low in energy consumption and quick lock in process charge pump high resistant elicit illness state promptly do not discharge do not deposit under the electricity condition yet finish, the impregnable phase-locked loop frequency integrator of loop stability with quick lock in function.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the phase-locked loop frequency integrator with quick lock in function, comprise phase-locked loop and quick lock in logical block, described phase-locked loop is by phase frequency detector, charge pump, voltage controlled oscillator, multi-modulus frequency divider able to programme, loop filter is formed, an input termination reference frequency signal of described phase frequency detector, the output of another input termination frequency divider, the input of the described charge pump of output termination of phase frequency detector, the electric charge delivery side of pump connects described loop filter input, the input of the described voltage controlled oscillator of output termination of loop filter, the input of the output termination frequency divider of voltage controlled oscillator.Described quick lock in logical block is by logic control circuit, the unit gain follower, the phase locking watch-dog is formed, the input of described phase locking watch-dog connects the output of reference frequency signal Fref and frequency divider respectively, an input of output signal termination logic control circuit, other two inputs of logic control circuit connect the output of phase frequency detector respectively, three outputs of logic control circuit are control switch sw respectively, sw and follower, switch sw is connected across between the input inp of a Vc and follower, and switch sw is connected across between the defeated output vo of an E and follower.
Described phase-locked loop also comprises adder, modulator and interface circuit, the output of the input termination frequency divider of described modulator, the output of modulator and after the adder addition, send into the pattern control end of frequency divider by the frequency dividing ratio integer part that interface circuit is sent into, realize integer frequency ratio or fraction division ratio, described data interface unit writes selection and the control that data are carried out frequency dividing ratio by the outside.
Owing to adopted above-mentioned structure, the present invention has realized the quick lock in of frequency synthesizer, and the quick lock in logical unit structure is simple, and is low in energy consumption.Be particularly suitable for requiring the low-power consumption twireless radio-frequency communication system of locking fast.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
Fig. 1 is the structured flowchart of the existing AFC of taking technology quick lock in frequency synthesizer;
Fig. 2 is the existing schematic diagram of taking aero mode technology quick lock in frequency synthesizer;
Fig. 3 is the structured flowchart that the present invention has the phase-locked loop frequency integrator of quick lock in function;
Fig. 4 is a quick lock in schematic diagram of the present invention;
The frequency of Fig. 5 the present invention and conventional method is combined locking process VCO control pressure-wire curve comparison diagram.
Embodiment
As shown in Figure 3, phase-locked loop frequency integrator with quick lock in function of the present invention, comprise phase-locked loop 101 and quick lock in logical block 102, described phase-locked loop 101 is by phase frequency detector 501, charge pump 502, voltage controlled oscillator 503, multi-modulus frequency divider 504 able to programme, the passive lead-lag loop filter 511 in three rank is formed, an input termination reference frequency signal of described phase frequency detector 501, the output of another input termination frequency divider 504, the input of the described charge pump 502 of output termination of phase frequency detector 501, described loop filter 511 inputs of the output termination of charge pump 502, the input of the described voltage controlled oscillator 503 of output termination of loop filter 511, the input of the output termination frequency divider 504 of voltage controlled oscillator 503;
Described quick lock in logical block 102 is by logic control circuit 508, unit gain follower 509, phase locking watch-dog 510 is formed, the input of described phase locking watch-dog 510 connects the output of reference frequency signal Fref and frequency divider 504 respectively, an input of output signal termination logic control circuit 508, other two inputs of logic control circuit 508 connect the output of phase frequency detector 501 respectively, three outputs of logic control circuit 508 are control switch sw1 respectively, sw2 and follower 509, switch sw2 is connected across between the input inp of a Vc and follower 509, and switch sw1 is connected across between the defeated output vo of an E and follower 509.
Described phase-locked loop 101 also comprises adder 505, three rank sgma-delta modulator 506 and interface circuits 507, the output of the input termination frequency divider 504 of described modulator 506, the output of modulator 506 and after adder 505 additions, send into the pattern control end of frequency divider 504 by the frequency dividing ratio integer part that interface circuit 507 is sent into, realize integer frequency ratio or fraction division ratio, described data interface unit 507 writes selection and the control that data are carried out frequency dividing ratio by the outside.
When frequently combining when starting working, hypothetical reference frequency signal Fref frequency is higher than frequency divider (504) output signal Fdiv frequency, then reference frequency signal Fref rising edge is prior to frequency divider (504) output signal Fdiv rising edge, the time difference that phase frequency detector (501) arrives by the rising edge of checking two input signals, and it is converted into output current by charge pump (502) is injected into loop filter (511) input Vc, loop filter (511) output is connected to voltage controlled oscillator (503) input raises the DC potential on the control line Vtune, thereby the output frequency of voltage controlled oscillator (503) raises, the output frequency of corresponding frequency divider (504) raises, its rising edge near the rising edge of reference frequency signal, is a loop-locking until coincidence gradually.
When not locking of loop, and during the work of quick lock in logical block, the phase locking watch-dog checks at first whether reference frequency signal Fref aligns with the phase place of output signal of frequency divider Fdiv, if the output ld that aligns is a high level, otherwise is low level.Logic control circuit is checked the output signal ld of phase locking watch-dog, the output signal up of PFD and dn, if ld is a low level, output signal ctr is always high level makes the unit gain source follower in running order, and up signal rising edge arrives logic control circuit prior to dn signal rising edge, output signal sw1 and sw2 were high level after then logic control circuit arrived from the rising edge of dn signal, remain to the arrival of up signal rising edge and become low level, output signal sw1 and sw2 high level make switch sw1 and the closed conducting of sw2, make charge pump E point current potential after entering the high resistant elicit illness state be pulled up to the current potential that equals Vc at once, thereby the current potential of Vc is remained unchanged, effectively raise the DC potential on the VCO input control voltage line Vtune, thereby reach the output frequency of quick raising VCO, make the output phase of frequency divider catch up with the phase place of reference frequency fast, it is poor to reach the input phase that dwindles fast between the two; If ld is a low level, and up signal rising edge lags behind dn signal rising edge and arrives logic control circuit, output signal sw1 and sw2 were high level after then logic control circuit arrived from the rising edge of up signal, remain to and become low level after dn signal rising edge arrives, output signal sw1 and sw2 high level make switch sw1 and the closed conducting of sw2, make charge pump E point current potential after entering the high resistant elicit illness state be pulled down to the current potential that equals Vc at once, thereby the current potential of Vc is remained unchanged, effectively reduced the DC potential on the VCO input control voltage line Vtune, thereby reach the output frequency of quick reduction VCO, make the phase place of reference frequency signal catch up with the output signal of frequency divider phase place fast, it is poor to reach the input phase that dwindles fast between the two; When the difference of the phase place of the phase place of frequency input signal and output signal of frequency divider is very little or when being zero, the phase locking watch-dog is output as high level, no matter this moment, which kind of state cp and dn were in, the output ctr of logic control circuit is that low level is not worked the shutoff of unit gain source follower, and sw1 and sw2 output signal are low level, switch sw1 and sw2 are disconnected, and the quick lock in logical block disconnects with the major loop of combining frequently like this, does not influence the work of major loop.
Aspect lock speed, fractional phase locked loop is better than the integer phase-locked loop, if noise characteristic allows, it is very wide that the loop bandwidth of fractional phase locked loop can reach, and generally can meet the demands locking time, but, for a lot of wireless communication systems, especially voice-transmission system is the comparison harshness to the requirement of phase noise, therefore, based on the consideration of noise, the bandwidth of fractional phase locked loop is still too narrow or still can not satisfy the requirement of system locking time for locking time.Quick lock in technology commonly used at present mainly contains aero mode and voltage controlled oscillator preconditioning pattern.The invention belongs to aero mode, but with traditional aero mode be distinct, its operation principle as shown in Figure 4:
Ordinate Vc representative ring path filter input terminal voltage is charge pump current is converted into voltage by loop filter a form.Fig. 4 (b) is that traditional aero mode loop filter input terminal voltage changes waveform, charge pump is during depositing electricity condition, main stored charge on integrating capacitor Cp, because integrating capacitor Cp is much smaller than minimum capacity C1, the Vc approximately linear rises during charge pump is deposited electricity, and the about Δ V=Icp* of last up voltage Δ t/Cp deposits electricity and finishes, charge pump enters and does not promptly deposit the high resistant elicit illness state that electricity does not also discharge, up to the one-period end of front PFD input.Electric charge will take place and shares in integrating capacitor Cp and minimum capacity C1 during elicit illness state, because the current potential on the Cp will be higher than the current potential on the C1, therefore, the electric charge on the Cp will flow to C1 by resistance R 1, current potential on the two equates or elicit illness state finishes, shown in Fig. 4 (b).Existing speed technology all is to inject more electric current by variety of way or various approach during charge pump is deposited electricity, make higher that the Vc that deposits during the electricity rises, thereby faster that voltage Vtune just rises effectively controlled in the input of VCO, but during depositing electricity condition, injects charge pump operations such as more electric current, certainly will consider the factors such as stability of whole loop, and it is shared at the electric charge of elicit illness state generation, in fact the electric charge of Zhu Ruing is on Cp and C1, because C1 is bigger usually, therefore Vc effectively rises still very little, in like manner, the charge pump discharge also is the same.The present invention is by carrying out the injection of electric current during the high-impedance state of charge pump elicit illness state, avoided the instability of loop, and inject more effective, make the speed of loop-locking faster, shown in Fig. 4 (a), also Δ V=Icp* Δ t/Cp during charge pump is deposited electricity, the charge pump current when but Icp is operate as normal here, finish when depositing electricity, charge pump enters the high resistant elicit illness state, at this moment electric charge will take place traditional structure shares Vc decline, and the present invention makes Vc keep constant by outside iunjected charge, therefore injects more effective, and injection is to take place in high configuration, therefore do not need to consider the stability of loop, when approach locking or through necessary injection of turn-offing elicit illness state after specific a period of time, otherwise loop stability is influenced.
Fig. 5 is the voltage waveform on the VCO input voltage control line and adopt the voltage waveform on the VCO input voltage control line in the phase-locked loop frequency integrator locking process of traditional quick lock in function in the phase-locked loop frequency integrator locking process with quick lock in function of the present invention, quick lock in as can be seen from the figure of the present invention is combined obviously rise very fast of voltage on the VCO input control line frequently, reached final stationary value soon, and traditional quick lock in is combined voltage on the VCO input control line frequently and is risen to final stationary value and want more than the late 10 μ S, because the influence of switching, finally settling out also needs one longer period.
In a word; though the present invention has exemplified above-mentioned preferred implementation, should illustrate, though those skilled in the art can carry out various variations and remodeling; unless such variation and remodeling have departed from scope of the present invention, otherwise all should be included in protection scope of the present invention.
Claims (2)
1. phase-locked loop frequency integrator with quick lock in function, comprise phase-locked loop (101) and quick lock in logic single (102), it is characterized in that: described phase-locked loop (101) is by phase frequency detector (501), charge pump (502), voltage controlled oscillator (503), multi-modulus frequency divider able to programme (504), loop filter (511) is formed, an input termination reference frequency signal of described phase frequency detector (501), the output of another input termination frequency divider (504), the input of the described charge pump of output termination (502) of phase frequency detector (501), the described loop filter of output termination (511) input of charge pump (502), the input of the described voltage controlled oscillator of output termination (503) of loop filter (511), the input of the output termination frequency divider (504) of voltage controlled oscillator (503);
Described quick lock in logical block (102) is by logic control circuit (508), unit gain follower (509), phase locking watch-dog (510) is formed, the input of described phase locking monitoring (510) connects the output of reference frequency signal Fref and frequency divider (504) respectively, an input of output signal termination logic control circuit (508), other two inputs of logic control circuit (508) connect the output of phase frequency detector (501) respectively, three outputs of logic control circuit (508) are control switch (sw1) respectively, (sw2) and follower (509), switch (sw2) is connected across between the input inp of a Vc and follower (509), and switch (sw1) is connected across between the defeated output vo of an E and follower (509).
2. according to the described phase-locked loop frequency integrator of claim 1 with quick lock in function, it is characterized in that: described phase-locked loop (101) also comprises adder (505), modulator (506) and interface circuit (507), the output of the input termination frequency divider (504) of described modulator (506), the output of modulator (506) and after adder (505) addition, send into the pattern control end of frequency divider (504) by the frequency dividing ratio integer part that interface circuit (507) is sent into, realize integer frequency ratio or fraction division ratio, described data interface unit (507) writes selection and the control that data are carried out frequency dividing ratio by the outside.
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Open date: 20091118 |