CN104967448A - Phase-locked loop quick lock circuit and control method thereof - Google Patents
Phase-locked loop quick lock circuit and control method thereof Download PDFInfo
- Publication number
- CN104967448A CN104967448A CN201510296475.4A CN201510296475A CN104967448A CN 104967448 A CN104967448 A CN 104967448A CN 201510296475 A CN201510296475 A CN 201510296475A CN 104967448 A CN104967448 A CN 104967448A
- Authority
- CN
- China
- Prior art keywords
- voltage
- frequency
- resistance
- circuit
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a phase-locked loop quick lock circuit and a control method thereof. The circuit comprises a main control chip, a reference frequency source, a phase discriminator, a loop filter circuit and a voltage-controlled oscillator; the voltage-controlled oscillator is connected with the phase discriminator and feeds back oscillation frequency to the phase discriminator; the reference frequency source outputs reference frequency to the phase discriminator; the phase discriminator processes the oscillation frequency and the reference frequency and outputs pump voltage to the loop filter circuit; the loop filter circuit processes the pump voltage and outputs voltage-controlled voltage to the voltage-controlled oscillator; and the voltage-controlled oscillator performs frequency conversion of the voltage-controlled voltage and outputs the oscillator frequency. The circuit further comprises a quick lock circuit connected with the main control chip and the loop filter circuit. The phase-locked loop quick lock circuit and the control method thereof can be used for quick and accurate lock of a phase-locked loop and significant decrease in the capture time at the initial stage of the lock of the phase-locked loop.
Description
Technical field
The present invention relates to radio-frequency communication module, particularly relate to a kind of phase locked loop fast lock circuit and control method thereof.
Background technology
Along with the development of the tdma communication systems such as GSM, TETRA, in RF system design process, require the locking time that PLL frequency synthesizer can provide more and more faster, meet multi-slot transmitting-receiving work, if complete frequency-hopped data transmission work.When raising PLL locking time, improving the locking time of phase-locked loop by adding fast lock circuit, by strengthening the method for pump electric current to improve locking time in prior art, but complicated TETRA communication system or frequency-hopping communication system application requirement can not be met.
In the PLL frequency hop mode of complexity, due to the restriction of pll low pass filter bandwidth, mutually restrict between the phase noise of frequency source and phase-locked loop speed, loop bandwidth is narrow, phase lock loop locks speed can be improved, reduce phase lock loop lock on time but phase noise can be made to strengthen.If strengthened by loop bandwidth, the phase noise position that can reduce frequency source can lengthen locking time.In TETRA communication system or frequency-hopping communication system application, realize from high frequency points frequency hopping to low frequency at same time slot, now, voltage-controlled voltage drop, now, phase-locked loop only can lean on the charge pump of self to discharge to loop filter circuit, therefore slower to the locking process of low frequency from high frequency points.
Fig. 1 is the oscillogram of phase lock loop locks in prior art, introduces the process of Frequency Locking below in conjunction with accompanying drawing 1.
1) T1 stage-acquisition phase: due to the switching of frequency, frequency is from being stabilized to unstable sharply change, and very greatly, phase-locked loop is in out-of-lock condition, needs a large amount of pump electric currents to carry out target acquisition frequency for frequency of oscillation and reference frequency phase difference.
2) T2 stage-tracking phase: frequency of oscillation and reference frequency phase difference less, phase-locked loop is followed the tracks of frequency of oscillation, belongs to the stage of loop self-regulation.
3) T3 stage-stabilization sub stage: frequency of oscillation and reference frequency phase difference very little, phase-locked loop is in the state of locking.Such as, in private network communication, when frequency departure be less than ± 100Hz time, phase-locked loop enters stable state.
As shown in Figure 1, in the three phases of locking process, mainly determined the locking time of target frequency by T1 and the T2 stage.And the time of T2 is mainly because the parameter of loop self determines.During T2, phase difference is smaller, and the adjustment by phase-locked loop self can enter T3 very soon.But, the time that T1 acquisition phase consumes, there is direct impact to the integral locking time.
Following several mode is adopted to realize phase-locked loop circuit quick lock in prior art:
(1) open within a bit of time that phase lock loop locks starts there is larger current fast lock pin to the discharge and recharge of low-pass loop filter circuit, then by register configuration switch add the requirement that less pump electric current meets narrow-band low-noise.The method can accelerate locking time to a certain extent, but due to the electric current of main control chip less, it is limited that it locks electric current that pin exports soon, and voltage-controlled voltage high frequency point needs longer locking time; And there is no quick discharging circuit, in phase-locked loop frequency hopping application scenario, when voltage-controlled voltage is from high frequency points frequency hopping to low frequency, loop filter circuit electric discharge is comparatively slow, and locking time is slower; In addition, when register configuration switches, in low-pass loop filter circuit, produce pulse, cause the frequency of voltage controlled oscillator unstable.
(2) number of patent application be CN201110080103.X, in the name circuit that is called phase locked loop fast lock and method, by arranging wide bandwidth loop filter circuit and narrow bandwidth loop filter circuit two loops, during beginning, wide bandwidth loop filter circuit is as the loop filter circuit in phase-locked loop, it is preset that preset voltage-controlled voltage carries out voltage to wide bandwidth loop filter circuit and narrow bandwidth loop filter circuit simultaneously, the frequency difference in the phase discriminator in phase-locked loop is made to be rapidly reduced to a smaller value, this process middle frequency difference is less, and acquisition phase T1 time used is also shorter.When wide bandwidth loop filter circuit voltage preset stable after, be that narrow bandwidth loop filter circuit carries out voltage by wide bandwidth loop filter circuit preset, thus narrow bandwidth loop filter circuit obtains accurate preset voltage-controlled voltage, by narrow bandwidth loop filter circuit as the loop filter circuit in phase-locked loop.Parameter by changing loop filter circuit in the method makes loop bandwidth strengthen, and then it is limited to reduce T1 phases-time; And repid discharge passage is not set, narrow band loop filter circuit is difficult to discharge at short notice, therefore longer to the locking time of low frequency from high frequency points; In addition, in circuit, use operational amplifier to carry out voltage compare, require higher to voltage controlled oscillator consistency and humidity stability.
Summary of the invention
The technical problem to be solved in the present invention is, for the defect of prior art, provides a kind of phase locked loop fast lock circuit and control method thereof.
The technical solution adopted for the present invention to solve the technical problems is: a kind of phase locked loop fast lock circuit, comprises main control chip, reference frequency source, phase discriminator, loop filter circuit and voltage controlled oscillator; Described voltage controlled oscillator is to described phase discriminator feedback oscillation frequency; Described reference frequency source exports reference frequency to described phase discriminator; Described phase discriminator processes described frequency of oscillation and described reference frequency and to described loop filter circuit rear pump voltage, described loop filter circuit processes described pump voltage and exports voltage-controlled voltage to described voltage controlled oscillator; Described voltage controlled oscillator carries out frequency conversion process to described voltage-controlled voltage and exports described frequency of oscillation; Also comprise the fast lock circuit be connected with described loop filter circuit with described main control chip respectively;
Described main control chip is used for described phase discriminator configuration initialization data and target frequency information, and calculate the target voltage corresponding with it according to described target frequency, control described fast lock circuit and electric discharge zero setting process is first carried out to the described voltage-controlled voltage that described loop filter circuit exports, carry out charging process again, the described voltage-controlled voltage exported to make described loop filter circuit is consistent with described target voltage.
Preferably, described fast lock circuit comprises for carrying out the discharge discharge circuit of zero setting process and the charging circuit for carrying out charging process to described voltage-controlled voltage to described voltage-controlled voltage.
Preferably, described discharge circuit comprises discharge resistance and the first switch for being connected described discharge resistance and described main control chip, a pin ground connection of described first switch; Described charging circuit comprises charging resistor and the second switch for being connected described charging resistor and described main control chip, and a pin of described second switch is connected with charge power supply.
Preferably, described loop filter circuit comprises the 3rd electric capacity being connected to the first resistance between described phase discriminator with described voltage controlled oscillator, being connected to the first electric capacity of described first resistance and one end ground connection between described voltage controlled oscillator, being connected to the second electric capacity of described first resistance and one end ground connection between described phase discriminator, being connected to one end ground connection that described first resistance is connected with the second resistance between described phase-locked loop circuit and the second resistance; Described charging resistor is connected between described second resistance and described 3rd electric capacity, and described discharge resistance is connected between described second resistance and described 3rd electric capacity.
Preferably, described main control chip calculates the target voltage Vt corresponding with it according to described target frequency, wherein, and Vt=(F
m-F
0)/K; F
mfor target frequency, K is the voltage-controlled sensitivity of voltage controlled oscillator, F
0for the frequency of oscillation that voltage controlled oscillator exports when voltage-controlled voltage is 0V, K, F
0for constant;
Described main control chip, by controlling the discharge time of described first switch ground connection, carries out electric discharge zero setting process with the described voltage-controlled voltage exported described loop filter circuit; Described discharge time passes through t1=R
1cLn [E/V
0] calculate, wherein, wherein R
1for the resistance value of discharge resistance, C is the capacitance of the 3rd electric capacity, and E is the maximum of voltage-controlled voltage, V
0for discharging into the magnitude of voltage of approximate 0V;
Described main control chip is again by the charging interval that the described second switch of control and charge power supply are energized, and to realize carrying out charging process to voltage-controlled voltage, the described charging interval passes through t2=R
2cLn [E/ (E-Vt)] calculates, wherein, and R
2for the resistance value of discharge resistance.
The present invention also provides a kind of control method of phase locked loop fast lock circuit, and described phase locked loop fast lock circuit comprises main control chip, reference frequency source, phase discriminator, loop filter circuit, voltage controlled oscillator, the fast lock circuit that is connected with described loop filter circuit with described main control chip respectively; Described voltage controlled oscillator is connected with described phase discriminator and to described phase discriminator feedback oscillation frequency; Described reference frequency source is used for exporting reference frequency to described phase discriminator; Described phase discriminator processes described frequency of oscillation and described reference frequency and to described loop filter circuit rear pump voltage; Described loop filter circuit processes described pump voltage and exports voltage-controlled voltage to described voltage controlled oscillator; Described voltage controlled oscillator carries out frequency conversion process to described voltage-controlled voltage and exports described frequency of oscillation; Described control method comprises the steps:
Described main control chip gives described phase discriminator configuration initialization data and target frequency information;
Described main control chip calculates the target voltage corresponding with it according to described target frequency;
Described main control chip controls described fast lock circuit and carries out electric discharge zero setting process to the described voltage-controlled voltage that described loop filter circuit exports;
Described main control chip controls described fast lock circuit and carries out charging process to the described voltage-controlled voltage that described loop filter circuit exports, and the described voltage-controlled voltage exported to make described loop filter circuit is consistent with described target voltage.
Preferably, described fast lock circuit comprises for carrying out the discharge discharge circuit of zero setting process and the charging circuit for carrying out charging process to described voltage-controlled voltage to described voltage-controlled voltage.
Preferably, described discharge circuit comprises discharge resistance and the first switch for being connected described discharge resistance and described main control chip, a pin ground connection of described first switch; Described charging circuit comprises charging resistor and the second switch for being connected described charging resistor and described main control chip, and a pin of described second switch is connected with charge power supply.
Preferably, described loop filter circuit comprises the 3rd electric capacity being connected to the first resistance between described phase discriminator with described voltage controlled oscillator, being connected to the first electric capacity of described first resistance and one end ground connection between described voltage controlled oscillator, being connected to the second electric capacity of described first resistance and one end ground connection between described phase discriminator, being connected to one end ground connection that described first resistance is connected with the second resistance between described phase-locked loop circuit and the second resistance; Described charging resistor is connected between described second resistance and described 3rd electric capacity, and described discharge resistance is connected between described second resistance and described 3rd electric capacity.
Preferably, described main control chip calculates the target voltage Vt corresponding with it according to described target frequency, wherein, and Vt=(F
m-F
0)/K; F
mfor target frequency, K is the voltage-controlled sensitivity of voltage controlled oscillator, F
0for the frequency of oscillation that voltage controlled oscillator exports when voltage-controlled voltage is 0V, K, F
0for constant;
Described main control chip, by controlling the discharge time of described first switch ground connection, carries out electric discharge zero setting process with the described voltage-controlled voltage exported described loop filter circuit; Described discharge time passes through t1=R
1cLn [E/V
0] calculate, wherein, wherein R
1for the resistance value of discharge resistance, C is the capacitance of the 3rd electric capacity, and E is the maximum of voltage-controlled voltage, V
0for discharging into the magnitude of voltage of approximate 0V;
Described main control chip is again by the charging interval that the described second switch of control and charge power supply are energized, and to realize carrying out charging process to voltage-controlled voltage, the described charging interval passes through t2=R
2cLn [E/ (E-Vt)] calculates, wherein, and R
2for the resistance value of discharge resistance.
The present invention compared with prior art tool has the following advantages: implement the present invention, by arranging fast lock circuit between main control chip and loop filter circuit, main control chip calculates the target voltage corresponding with it according to target frequency, and control fast lock circuit first electric discharge zero setting is carried out to the voltage-controlled voltage that loop filter circuit exports, then charging process is carried out, the described voltage-controlled voltage exported to make described loop filter circuit is consistent with described target voltage, to realize the object of quick accurate lock phase-locked loop in the short time, greatly shorten the capture time at phase lock loop locks initial stage.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the oscillogram of phase lock loop locks in prior art.
Fig. 2 is the theory diagram of phase locked loop fast lock circuit in the embodiment of the present invention 1.
Fig. 3 is the circuit diagram of the phase locked loop fast lock circuit in the embodiment of the present invention 1.
Fig. 4 is the flow chart of the control method of phase locked loop fast lock circuit in the embodiment of the present invention 2.
In figure: 10, main control chip; 20, reference frequency source; 30, phase discriminator; 40, loop filter circuit; 50, voltage controlled oscillator; 60, fast lock circuit; K1, the first switch; K2, second switch; R1, discharge resistance; R2, charging resistor; R3, the first resistance; R4, the second resistance; C1, the first electric capacity; C2, the second electric capacity; C3, the 3rd electric capacity; 70, charge power supply.
Embodiment
In order to there be understanding clearly to technical characteristic of the present invention, object and effect, now contrast accompanying drawing and describe the specific embodiment of the present invention in detail.
Embodiment 1
Fig. 2 illustrates the phase locked loop fast lock circuit in the present invention in an embodiment.This phase locked loop fast lock circuit comprises main control chip 10, for the fast lock circuit 60 exporting the reference frequency source 20 of reference frequency, the phase discriminator 30 be connected with reference frequency source 20 with main control chip 10 respectively, the loop filter circuit 40 be connected with phase discriminator 30, the voltage controlled oscillator 50 be connected with loop filter circuit 40 and be connected with loop filter circuit 40 with main control chip 10 respectively, voltage controlled oscillator 50 is connected with phase discriminator 30 and to phase discriminator 30 feedback oscillation frequency.
Frequency of oscillation after scaling down processing and reference frequency for carrying out scaling down processing to frequency of oscillation, and are carried out phase compare by phase discriminator 30, and to loop filter circuit 40 rear pump voltage.Understandably, the phase comparator that phase discriminator 30 comprises the scaling down processing device for carrying out scaling down processing to frequency of oscillation and is connected with reference frequency source 20 with scaling down processing device respectively, phase comparator compares through the frequency of oscillation of scaling down processing and the phase place of reference frequency, produces the pump voltage corresponding to two-phase potential difference.
Loop filter circuit 40, for carrying out integration and filtering process to pump voltage, with the radio-frequency component in filtering pump voltage and noise, thus ensures form stable voltage-controlled voltage and export voltage controlled oscillator 50 to.
Voltage controlled oscillator 50, for carrying out frequency inverted to voltage-controlled voltage, exports frequency of oscillation.Understandably, there is linear relationship in frequency of oscillation and voltage-controlled voltage, i.e. F
m=K*Vt+F
0, wherein, F
mfor the frequency of oscillation that voltage controlled oscillator 50 exports, Vt is the voltage-controlled voltage exporting voltage controlled oscillator 50 to, and K is voltage-controlled sensitivity or the gain coefficient of voltage controlled oscillator 50, F
0for the frequency of oscillation that voltage controlled oscillator 50 exports when voltage-controlled voltage is 0V, its size is determined by pierce circuit self character; K, F
0for constant.Understandably, according to linear relationship intrinsic between frequency of oscillation and voltage-controlled voltage, voltage-controlled voltage Vt=(F can be tried to achieve
m-F
0)/K.
Main control chip 10 configures initialization data and target frequency information for giving phase discriminator 30, and calculate the target voltage corresponding with it according to this target frequency, the discharge time controlling fast lock circuit 60 again carries out electric discharge zero setting process with the voltage-controlled voltage realized loop filter circuit 40 exports, the charging interval controlling fast lock circuit 60 again carries out charging process to loop filter circuit 40, the moment is turned off to make charging, the voltage-controlled voltage that loop filter circuit 40 exports is consistent with target voltage, the frequency of oscillation F exported after namely voltage controlled oscillator 50 carries out frequency conversion process
mbe stabilized on target frequency, make phase-locked loop lock onto target frequency when initial frequency difference is less, to reduce locking time.Understandably, after completing fast lock process, this phase locked loop fast lock circuit carries out the self-locking stage, namely carries out inching by phase discriminator 30, loop filter circuit 40 and voltage controlled oscillator 50.
Understandably, the initial loop of phase lock loop locks is always in out-of-lock condition, as start, change frequency (especially from high-end frequency to low side frequency) etc., if the phase difference of the voltage-controlled voltage and the target voltage that when locking initial, loop filter circuit 40 export is comparatively large, then it is slower that the pump voltage of phase discriminator 30 output carries out adjusting by loop filter circuit 40 locking process that the frequency of oscillation that voltage controlled oscillator 50 is exported is stabilized on target frequency.In this programme, fast lock circuit 60 is set between main control chip 10 and loop filter circuit 40, first the target voltage corresponding with it is calculated according to target frequency when locking initial, again electric discharge zero setting process is first carried out to the voltage-controlled voltage that loop filter circuit 40 exports, to make its charging process more accurate, avoid interference; And then charging process is carried out to the voltage-controlled voltage that loop filter circuit 40 exports, the voltage-controlled voltage that loop filter circuit 40 is exported is consistent with target voltage, namely make the frequency of oscillation of voltage-controlled voltage after frequency inverted exporting voltage controlled oscillator 50 to consistent with target frequency, thus reduce locking time, realize quick lock in object.
As shown in Figure 3, fast lock circuit 60 comprises for carrying out the discharge discharge circuit of zero setting process and the charging circuit for carrying out charging process to voltage-controlled voltage to voltage-controlled voltage.Discharge circuit comprises discharge resistance R1 and the pin ground connection for the first K switch 1, first K switch 1 of connecting discharge resistance R1 and main control chip 10.The pin that charging circuit comprises charging resistor R2 and the second switch K2 for connecting charging resistor R2 and main control chip 10, second switch K2 is connected with charge power supply 70.Understandably, choose resistance less discharge resistance R1 and charging resistor R2, for the control time reducing quick lock in He open as far as possible.As selection, the concrete components and parts arrangement of discharge circuit is not limited to upper type, as long as the function of voltage-controlled voltage being carried out to electric discharge zero setting process can be realized, and can in prior art, other can realize the circuit of correlation function.
As shown in Figure 3, loop filter circuit 40 comprises the 3rd electric capacity C3 being connected to the first resistance R3 between phase discriminator 30 with voltage controlled oscillator 50, being connected to the first electric capacity C1 of the first resistance R3 and one end ground connection between voltage controlled oscillator 50, being connected to the second electric capacity C2 of the first resistance R3 and one end ground connection between phase discriminator 30, being connected to one end ground connection that the first resistance R3 is connected with the second resistance R4 between phase-locked loop circuit and the second resistance R4; Charging resistor R2 is connected between the second resistance R4 and the 3rd electric capacity C3, and discharge resistance R1 is connected between the second resistance R4 and the 3rd electric capacity C3.
Below the operation principle of phase locked loop fast lock circuit in some embodiments of the invention is described.Particularly, in this phase locked loop fast lock circuit working process, main control chip 10 configures initialization data and target frequency information first to phase discriminator 30, and calculates the target voltage Vt corresponding with it according to target frequency, wherein, and Vt=(F
m-F
0)/K; F
mfor target frequency, K is the voltage-controlled sensitivity of voltage controlled oscillator 50, F
0for the frequency of oscillation that voltage controlled oscillator 50 exports when voltage-controlled voltage is 0V, K, F
0for constant.
Then, main control chip 10, by the discharge time of control first K switch 1 ground connection, carries out electric discharge zero setting process with the voltage-controlled voltage exported loop filter circuit 40; Discharge time passes through t1=R
1cLn [E/V
0] calculate, wherein, wherein R
1for the resistance value of discharge resistance R1, C is the capacitance of the 3rd electric capacity C3, and E is the maximum of voltage-controlled voltage, V
0for discharging into the magnitude of voltage of approximate 0V.Particularly, E is identical with the magnitude of voltage powering to phase discriminator 30 charge pump.
Finally, in the charging interval that main control chip 10 is energized by control second switch K2 and charge power supply 70, to realize carrying out charging process to voltage-controlled voltage, the charging interval passes through t2=R
2cLn [E/ (E-Vt)] calculates, wherein, and R
2for the resistance value of discharge resistance R1.
Understandably, main control chip 10 first calculates the target voltage corresponding with it according to target frequency, the charging interval is calculated again according to this target voltage, charging process is carried out with the voltage-controlled voltage completed loop filter circuit 40 exports, make to turn off the moment in charging, the voltage-controlled voltage that loop filter circuit 40 exports close to target voltage corresponding to target frequency, and then make phase-locked loop when an initial frequency difference is less lock onto target frequency to reduce locking time.
Implement the present invention, by opening sequential at main control chip 10 by the discharge circuit and charging circuit controlling fast lock circuit 60, and the discharge time of discharge circuit and the charging interval of charging circuit, first electric discharge zero setting is carried out with the voltage-controlled voltage completed loop filter circuit 40 exports, then charging process is carried out, the voltage-controlled voltage exported to make voltage controlled oscillator 50 is at target proximity corresponding to target frequency, namely the frequency of oscillation making voltage controlled oscillator 50 export is stabilized on target frequency, to realize the object of quick accurate lock phase-locked loop in the short time, greatly shorten the capture time at phase lock loop locks initial stage.
As selection, in further embodiments, phase locked loop fast lock circuit can comprise main control chip 10, reference frequency source 20, phase discriminator 30, loop filter circuit 40, voltage controlled oscillator 50 and the fast lock circuit 60 be connected with loop filter circuit 40 with main control chip 10 respectively.
Wherein, main control chip 10 configures initialization data and target frequency information for giving phase discriminator 30, and calculates the target voltage corresponding with it according to target frequency.As selection, main control chip 10 is not limited to the form in embodiment 1, as long as can realize corresponding configuration function and computing function.
Voltage controlled oscillator 50 is for phase discriminator 30 feedback oscillation frequency, and frequency conversion process output frequency of oscillation is carried out to voltage-controlled voltage, as selection, voltage controlled oscillator 50 is not limited to the form in embodiment 1, exports frequency of oscillation as long as can realize exporting frequency of oscillation and be sent to phase discriminator 30 and carry out frequency conversion process to voltage-controlled voltage.
Reference frequency source 20 is for exporting reference frequency to phase discriminator 30, and as selection, reference frequency source 20 is not limited to the form in embodiment 1, as long as can realize exporting reference frequency and being sent to phase discriminator 30.
Phase discriminator 30 pairs of frequencies of oscillation and reference frequency process and to loop filter circuit 40 rear pump voltage, as selection, phase discriminator 30 is not limited to the form in embodiment 1, as long as can realize process frequency of oscillation and reference frequency pump voltage is sent to loop filter circuit 40.
Loop filter circuit 40 pairs of pump voltages process and export voltage-controlled voltage to voltage controlled oscillator 50, as selection, loop filter circuit 40 is not limited to the form in embodiment 1, as long as can realize process pump voltage and voltage-controlled voltage is sent to voltage controlled oscillator 50.
Fast lock circuit 60 is under the control of governor circuit 10, and first carry out electric discharge zero setting process to the voltage-controlled voltage that loop filter circuit 40 exports, then carry out charging process, the voltage-controlled voltage exported to make loop filter circuit 40 is consistent with target voltage.As selection, fast lock circuit 60 is not limited to the form in embodiment 1, as long as can realize discharge accordingly zero setting process and charging process function.
Embodiment 2
The present invention also provides a kind of control method of phase locked loop fast lock circuit.As shown in Figure 2 and Figure 3, this phase locked loop fast lock circuit comprises main control chip 10, reference frequency source 20, phase discriminator 30, loop filter circuit 40, voltage controlled oscillator 50, the fast lock circuit 60 that is connected with loop filter circuit 40 with main control chip 10 respectively.Voltage controlled oscillator 50 is connected with phase discriminator 30 and to phase discriminator 30 feedback oscillation frequency; Reference frequency source 20 is for exporting reference frequency to phase discriminator 30; Phase discriminator 30 pairs of frequencies of oscillation and reference frequency process and to loop filter circuit 40 rear pump voltage; Loop filter circuit 40 pairs of pump voltages process and export voltage-controlled voltage to voltage controlled oscillator 50; Voltage controlled oscillator 50 carries out frequency conversion process to voltage-controlled voltage and exports frequency of oscillation.
As shown in Figure 3, fast lock circuit 60 comprises for carrying out the discharge discharge circuit of zero setting process and the charging circuit for carrying out charging process to voltage-controlled voltage to voltage-controlled voltage.Discharge circuit comprises discharge resistance R1 and the pin ground connection for the first K switch 1, first K switch 1 of connecting discharge resistance R1 and main control chip 10.The pin that charging circuit comprises charging resistor R2 and the second switch K2 for connecting charging resistor R2 and main control chip 10, second switch K2 is connected with charge power supply 70.Understandably, choose resistance less discharge resistance R1 and charging resistor R2, for the control time reducing quick lock in He open as far as possible.
As shown in Figure 3, loop filter circuit 40 comprises the 3rd electric capacity C3 being connected to the first resistance R3 between phase discriminator 30 with voltage controlled oscillator 50, being connected to the first electric capacity C1 of the first resistance R3 and one end ground connection between voltage controlled oscillator 50, being connected to the second electric capacity C2 of the first resistance R3 and one end ground connection between phase discriminator 30, being connected to one end ground connection that the first resistance R3 is connected with the second resistance R4 between phase-locked loop circuit and the second resistance R4; Charging resistor R2 is connected between the second resistance R4 and the 3rd electric capacity C3, and discharge resistance R1 is connected between the second resistance R4 and the 3rd electric capacity C3.
With reference to figure 4, composition graphs 2 and Fig. 3, the control method of this phase locked loop fast lock circuit comprises the steps:
S1: main control chip 10 configures initialization data and target frequency information to phase discriminator 30.
S2: main control chip 10 calculates the target voltage corresponding with it according to target frequency.Particularly, target voltage Vt can calculate according to the linear relationship of frequency of oscillation and voltage-controlled voltage and try to achieve, i.e. Vt=(F
m-F
0)/K; F
mfor target frequency, K is the voltage-controlled sensitivity of voltage controlled oscillator (50), F
0for the frequency of oscillation that voltage controlled oscillator (50) exports when voltage-controlled voltage is 0V, K, F
0for constant.
S3: the voltage-controlled voltage that main control chip 10 controls 60 pairs of loop filter circuit 40 outputs of fast lock circuit carries out electric discharge zero setting process.Particularly, main control chip 10, by the discharge time of control first K switch 1 ground connection, carries out electric discharge zero setting process with the voltage-controlled voltage exported loop filter circuit 40; Discharge time passes through t1=R
1cLn [E/V
0] calculate, wherein, wherein R
1for the resistance value of discharge resistance R1, C is the capacitance of the 3rd electric capacity C3, and E is the maximum of voltage-controlled voltage, V
0for discharging into the magnitude of voltage of approximate 0V.Particularly, E is identical with the magnitude of voltage powering to phase discriminator 30 charge pump.
S4: the voltage-controlled voltage that main control chip 10 controls 60 pairs of loop filter circuit 40 outputs of fast lock circuit carries out charging process, and the frequency of oscillation exported after carrying out frequency conversion process to make voltage controlled oscillator 50 is stabilized on target frequency.In the charging interval that main control chip 10 is energized by control second switch K2 and charge power supply 70, to realize carrying out charging process to voltage-controlled voltage, the charging interval passes through t2=R
2cLn [E/ (E-Vt)] calculates, wherein, and R
2for the resistance value of discharge resistance R1.
This control method opens the discharge time of sequential and discharge circuit and the charging interval of charging circuit by the discharge circuit and charging circuit controlling fast lock circuit 60, the voltage-controlled voltage exported to make loop filter circuit 40 is consistent with target voltage, namely the frequency of oscillation making the voltage-controlled voltage exporting voltage controlled oscillator 50 to obtain after frequency inverted is stabilized on target frequency, thus reduce locking time, to realize the object of quick accurate lock phase-locked loop in the short time, greatly shorten the capture time at phase lock loop locks initial stage.
Understandably, after completing fast lock process, this phase locked loop fast lock circuit carries out the self-locking stage, namely carries out inching by phase discriminator 30, loop filter circuit 40 and voltage controlled oscillator 50.Specifically comprise the steps: that phase discriminator 30 pairs of frequencies of oscillation are carried out scaling down processing and the frequency of oscillation after scaling down processing and reference frequency are carried out phase compare, to loop filter circuit 40 rear pump voltage; Loop filter circuit 40 pairs of pump voltages carry out integration and filtering process, with the radio-frequency component in filtering pump voltage and noise, thus ensure form stable voltage-controlled voltage and export voltage controlled oscillator 50 to; Voltage controlled oscillator 50 carries out frequency inverted to voltage-controlled voltage, exports frequency of oscillation.
In the control method of this phase locked loop fast lock circuit, locked soon by step S1-step S4, the frequency of oscillation that voltage controlled oscillator 50 is exported is stabilized on target frequency, to realize the object of quick accurate lock phase-locked loop in the short time, greatly shortens the capture time at phase lock loop locks initial stage.
Particularly, phase locked loop fast lock circuit provided by the present invention and control method thereof, fast lock circuit 60 is set, effectively can solve high frequency points to slow problem locking time during low frequency frequency hopping, and the voltage-controlled voltage caused by phase discriminator 30 under solving TETRA product low frequency low temperature overturns the problem causing EVM index to be deteriorated.The full frequency band of this programme is less than 2.5ms locking time, and existing scheme (namely not introducing the scheme of fast lock circuit 60) medium-high frequency point locking time is minimum is 4.8ms.The raising of locking time improves the transmitting EVM index of the high-end frequency of TETRA product, and the emission peak of the high-end frequency of existing scheme is 18%, and the emission peak EVM of the high-end frequency of this programme is 11%.This programme accelerates locking time, and then reduces the opening time of phase discriminator 30, thus improves product TMO stand-by time.For TETRA hand platform, the whole FGU of existing scheme high-end frequency 4.8ms needs 6ms in advance to open.This programme full frequency band to be less than 2.5mS locking time and only to need to carry 3.5ms and open, than the operating time (accounting for the time of 10% of the standby frame of TMO) of front saving 2.5ms, receiver FGU electric current is about 35mA (PLL chip+RXVCO+IFVCO, account for the 35/100mA of standby current, about 35%), generally speaking save stand-by time about: 10%*35%=3.5%, as standby in TETRA hand platform TMO about 20 hours, as then can improved the stand-by time of about 0.7 hour with new departure.
The present invention is described by several specific embodiment, it will be appreciated by those skilled in the art that, without departing from the present invention, can also carry out various conversion and be equal to substituting to the present invention.In addition, for particular condition or concrete condition, various amendment can be made to the present invention, and not depart from the scope of the present invention.Therefore, the present invention is not limited to disclosed specific embodiment, and should comprise the whole execution modes fallen within the scope of the claims in the present invention.
Claims (10)
1. a phase locked loop fast lock circuit, comprises main control chip (10), reference frequency source (20), phase discriminator (30), loop filter circuit (40) and voltage controlled oscillator (50); Described voltage controlled oscillator (50) is to described phase discriminator (30) feedback oscillation frequency; Described reference frequency source (20) exports reference frequency to described phase discriminator (30); Described phase discriminator (30) processes described frequency of oscillation and described reference frequency and to described loop filter circuit (40) rear pump voltage, described loop filter circuit (40) processes described pump voltage and exports voltage-controlled voltage to described voltage controlled oscillator (50); Described voltage controlled oscillator (50) carries out frequency conversion process to described voltage-controlled voltage and exports described frequency of oscillation; It is characterized in that: also comprise the fast lock circuit (60) be connected with described loop filter circuit (40) with described main control chip (10) respectively;
Described main control chip (10) is for giving described phase discriminator (30) configuration initialization data and target frequency information, and calculate the target voltage corresponding with it according to described target frequency, control described fast lock circuit (60) and electric discharge zero setting process is first carried out to the described voltage-controlled voltage that described loop filter circuit (40) exports, carry out charging process again, consistent with described target voltage with the described voltage-controlled voltage making described loop filter circuit (40) export.
2. phase locked loop fast lock circuit according to claim 1, is characterized in that: described fast lock circuit (60) comprises for carrying out the discharge discharge circuit of zero setting process and the charging circuit for carrying out charging process to described voltage-controlled voltage to described voltage-controlled voltage.
3. phase locked loop fast lock circuit according to claim 2, it is characterized in that: described discharge circuit comprises discharge resistance (R1) and the first switch (K1) for being connected described discharge resistance (R1) and described main control chip (10), a pin ground connection of described first switch (K1); Described charging circuit comprises charging resistor (R2) and the second switch (K2) for being connected described charging resistor (R2) and described main control chip (10), and a pin of described second switch (K2) is connected with charge power supply (70).
4. phase locked loop fast lock circuit according to claim 3, it is characterized in that: described loop filter circuit (40) comprises the first resistance (R3) be connected between described phase discriminator (30) and described voltage controlled oscillator (50), be connected to first electric capacity (C1) of one end ground connection between described first resistance (R3) and described voltage controlled oscillator (50), be connected to second electric capacity (C2) of one end ground connection between described first resistance (R3) and described phase discriminator (30), be connected to the second resistance (R4) between described first resistance (R3) and described phase-locked loop circuit, and the 3rd electric capacity (C3) of the connected one end ground connection of the second resistance (R4), described charging resistor (R2) is connected between described second resistance (R4) and described 3rd electric capacity (C3), and described discharge resistance (R1) is connected between described second resistance (R4) and described 3rd electric capacity (C3).
5. phase locked loop fast lock circuit according to claim 4, is characterized in that:
Described main control chip (10) calculates the target voltage Vt corresponding with it according to described target frequency, wherein, and Vt=(F
m-F
0)/K; F
mfor target frequency, K is the voltage-controlled sensitivity of voltage controlled oscillator (50), F
0for the frequency of oscillation that voltage controlled oscillator (50) exports when voltage-controlled voltage is 0V, K, F
0for constant;
Described main control chip (10), by controlling the discharge time of described first switch (K1) ground connection, carries out electric discharge zero setting process with the described voltage-controlled voltage exported described loop filter circuit (40); Described discharge time passes through t1=R
1cLn [E/V
0] calculate, wherein, wherein R
1for the resistance value of discharge resistance (R1), C is the capacitance of the 3rd electric capacity (C3), and E is the maximum of voltage-controlled voltage, V
0for discharging into the magnitude of voltage of approximate 0V;
Described main control chip (10) is again by controlling the charging interval that described second switch (K2) and charge power supply (70) are energized, and to realize carrying out charging process to voltage-controlled voltage, the described charging interval passes through t2=R
2cLn [E/ (E-Vt)] calculates, wherein, and R
2for the resistance value of discharge resistance (R1).
6. a control method for phase locked loop fast lock circuit, is characterized in that: described phase locked loop fast lock circuit comprises main control chip (10), reference frequency source (20), phase discriminator (30), loop filter circuit (40), voltage controlled oscillator (50), the fast lock circuit (60) that is connected with described loop filter circuit (40) with described main control chip (10) respectively; Described voltage controlled oscillator (50) is connected with described phase discriminator (30) and to described phase discriminator (30) feedback oscillation frequency; Described reference frequency source (20) is for exporting reference frequency to described phase discriminator (30); Described phase discriminator (30) processes described frequency of oscillation and described reference frequency and to described loop filter circuit (40) rear pump voltage; Described loop filter circuit (40) processes described pump voltage and exports voltage-controlled voltage to described voltage controlled oscillator (50); Described voltage controlled oscillator (50) carries out frequency conversion process to described voltage-controlled voltage and exports described frequency of oscillation; Described control method comprises the steps:
Described main control chip (10) is to described phase discriminator (30) configuration initialization data and target frequency information;
Described main control chip (10) calculates the target voltage corresponding with it according to described target frequency;
Described main control chip (10) controls described fast lock circuit (60) and carries out electric discharge zero setting process to the described voltage-controlled voltage that described loop filter circuit (40) exports;
Described main control chip (10) controls described fast lock circuit (60) and carries out charging process to the described voltage-controlled voltage that described loop filter circuit (40) exports, consistent with described target voltage with the described voltage-controlled voltage making described loop filter circuit (40) export.
7. the control method of phase locked loop fast lock circuit according to claim 6, is characterized in that: described fast lock circuit (60) comprises for carrying out the discharge discharge circuit of zero setting process and the charging circuit for carrying out charging process to described voltage-controlled voltage to described voltage-controlled voltage.
8. the control method of phase locked loop fast lock circuit according to claim 7, it is characterized in that: described discharge circuit comprises discharge resistance (R1) and the first switch (K1) for being connected described discharge resistance (R1) and described main control chip (10), a pin ground connection of described first switch (K1); Described charging circuit comprises charging resistor (R2) and the second switch (K2) for being connected described charging resistor (R2) and described main control chip (10), and a pin of described second switch (K2) is connected with charge power supply (70).
9. the control method of phase locked loop fast lock circuit according to claim 8, it is characterized in that: described loop filter circuit (40) comprises the first resistance (R3) be connected between described phase discriminator (30) and described voltage controlled oscillator (50), be connected to first electric capacity (C1) of one end ground connection between described first resistance (R3) and described voltage controlled oscillator (50), be connected to second electric capacity (C2) of one end ground connection between described first resistance (R3) and described phase discriminator (30), be connected to the second resistance (R4) between described first resistance (R3) and described phase-locked loop circuit, and the 3rd electric capacity (C3) of the connected one end ground connection of the second resistance (R4), described charging resistor (R2) is connected between described second resistance (R4) and described 3rd electric capacity (C3), and described discharge resistance (R1) is connected between described second resistance (R4) and described 3rd electric capacity (C3).
10. the control method of phase locked loop fast lock circuit according to claim 9, is characterized in that:
Described main control chip (10) calculates the target voltage Vt corresponding with it according to described target frequency, wherein, and Vt=(F
m-F
0)/K; F
mfor target frequency, K is the voltage-controlled sensitivity of voltage controlled oscillator (50), F
0for the frequency of oscillation that voltage controlled oscillator (50) exports when voltage-controlled voltage is 0V, K, F
0for constant;
Described main control chip (10), by controlling the discharge time of described first switch (K1) ground connection, carries out electric discharge zero setting process with the described voltage-controlled voltage exported described loop filter circuit (40); Described discharge time passes through t1=R
1cLn [E/V
0] calculate, wherein, wherein R
1for the resistance value of discharge resistance (R1), C is the capacitance of the 3rd electric capacity (C3), and E is the maximum of voltage-controlled voltage, V
0for discharging into the magnitude of voltage of approximate 0V;
Described main control chip (10) is again by controlling the charging interval that described second switch (K2) and charge power supply (70) are energized, and to realize carrying out charging process to voltage-controlled voltage, the described charging interval passes through t2=R
2cLn [E/ (E-Vt)] calculates, wherein, and R
2for the resistance value of discharge resistance (R1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510296475.4A CN104967448A (en) | 2015-06-02 | 2015-06-02 | Phase-locked loop quick lock circuit and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510296475.4A CN104967448A (en) | 2015-06-02 | 2015-06-02 | Phase-locked loop quick lock circuit and control method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104967448A true CN104967448A (en) | 2015-10-07 |
Family
ID=54221409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510296475.4A Pending CN104967448A (en) | 2015-06-02 | 2015-06-02 | Phase-locked loop quick lock circuit and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104967448A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995256A (en) * | 2019-12-25 | 2020-04-10 | 深圳市和宏实业股份有限公司 | Phase-locked loop device for reducing frequency locking time and implementation method |
| CN113114239A (en) * | 2021-04-19 | 2021-07-13 | 南京中科神光科技有限公司 | Method and system for expanding frequency difference locking dynamic range of optical phase-locked loop |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1080446A (en) * | 1992-06-12 | 1994-01-05 | 莫托罗拉公司 | Radio device with quick lock in phase-locked loop |
| CN101582695A (en) * | 2009-06-19 | 2009-11-18 | 广州润芯信息技术有限公司 | Phase lock loop frequency synthesizer with quick lock function |
| CN101783677A (en) * | 2010-03-26 | 2010-07-21 | 海能达通信股份有限公司 | Locking method of phase-locked loop and locking circuit thereof |
| CN102545836A (en) * | 2011-12-30 | 2012-07-04 | 海能达通信股份有限公司 | Frequency generating unit and frequency fast locking method thereof |
| CN103618548A (en) * | 2013-12-06 | 2014-03-05 | 海能达通信股份有限公司 | Frequency synthesis method and circuit based on rapid frequency locking of phase-locked loop |
-
2015
- 2015-06-02 CN CN201510296475.4A patent/CN104967448A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1080446A (en) * | 1992-06-12 | 1994-01-05 | 莫托罗拉公司 | Radio device with quick lock in phase-locked loop |
| CN101582695A (en) * | 2009-06-19 | 2009-11-18 | 广州润芯信息技术有限公司 | Phase lock loop frequency synthesizer with quick lock function |
| CN101783677A (en) * | 2010-03-26 | 2010-07-21 | 海能达通信股份有限公司 | Locking method of phase-locked loop and locking circuit thereof |
| CN102545836A (en) * | 2011-12-30 | 2012-07-04 | 海能达通信股份有限公司 | Frequency generating unit and frequency fast locking method thereof |
| CN103618548A (en) * | 2013-12-06 | 2014-03-05 | 海能达通信股份有限公司 | Frequency synthesis method and circuit based on rapid frequency locking of phase-locked loop |
Non-Patent Citations (1)
| Title |
|---|
| 魏廷存等: "《模拟CMOS集成电路设计》", 31 March 2010, 清华大学出版社 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995256A (en) * | 2019-12-25 | 2020-04-10 | 深圳市和宏实业股份有限公司 | Phase-locked loop device for reducing frequency locking time and implementation method |
| CN110995256B (en) * | 2019-12-25 | 2023-05-12 | 深圳市和宏实业股份有限公司 | Phase-locked loop device for reducing frequency locking time and implementation method |
| CN113114239A (en) * | 2021-04-19 | 2021-07-13 | 南京中科神光科技有限公司 | Method and system for expanding frequency difference locking dynamic range of optical phase-locked loop |
| CN113114239B (en) * | 2021-04-19 | 2024-02-27 | 南京先进激光技术研究院 | Method and system for expanding frequency difference locking dynamic range of optical phase-locked loop |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Chiu et al. | A dynamic phase error compensation technique for fast-locking phase-locked loops | |
| EP0272938B1 (en) | Frequency synthesizer | |
| US7215936B2 (en) | Super-regenerative receiver including phase-locked loop | |
| CN101931399B (en) | Phase-locked loop frequency synthesizer | |
| JP2748676B2 (en) | PLL circuit | |
| US7443254B2 (en) | Relaxation oscillator with propagation delay compensation for improving the linearity and maximum frequency | |
| CN101436859A (en) | Rapidly-locked frequency generator | |
| CA1219640A (en) | Circuit arrangement comprising a voltage-controlled oscillator operable with different sensitivities | |
| CN102684685B (en) | Phase locked loop and method thereof | |
| CN102545836B (en) | Frequency generating unit and frequency fast locking method thereof | |
| CN101188420A (en) | Loop system for automatically correcting surge frequency range and its related method | |
| CN107623521A (en) | A kind of pll clock generator | |
| CN110445491B (en) | Phase-locked loop based on preset frequency and dynamic loop bandwidth | |
| US6864729B2 (en) | Mode switching method for PLL circuit and mode control circuit for PLL circuit | |
| US8112054B2 (en) | Tri-stating a phase locked loop to conserve power | |
| CN104967448A (en) | Phase-locked loop quick lock circuit and control method thereof | |
| CN112234981B (en) | Data and clock recovery circuit | |
| CN203457137U (en) | Switch-controlled filter circuit applied to phase-locked loop | |
| US7283801B2 (en) | Circuit arrangement for phase locked loop, and phase locked loop based method to be used in cellular network terminals | |
| KR20020029900A (en) | A frequency synthesizer having a phase-locked loop with circuit for reducing power-on switching transients | |
| CN104967447A (en) | Phase-locked loop frequency modulation circuit capable of achieving continuous modulation | |
| CN205407759U (en) | Clock duty cycle adjusting device | |
| CN101557230B (en) | System and method for self calibration of phase-locked loop | |
| CN110855291B (en) | Phase-locked acceleration circuit applied to phase-locked loop system and phase-locked loop system | |
| US20030189463A1 (en) | Current saving technique for charge pump based phase locked loops |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151007 |