CN110995256A - Phase-locked loop device for reducing frequency locking time and implementation method - Google Patents
Phase-locked loop device for reducing frequency locking time and implementation method Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention discloses a phase-locked loop device for reducing frequency locking time, which comprises: the device comprises a phase discriminator unit, a frequency dividing unit, a feedback signal frequency dividing unit, a loop low-pass filter, a voltage-controlled oscillator, a feedback amplifier, a micro-processing unit, a charging control unit and a discharging control unit, wherein the charging control unit and the discharging control unit are connected with the micro-processing unit, and the micro-processing unit is used for controlling the charging control unit or the discharging control unit to charge and discharge the loop low-pass filter during frequency switching so as to realize quick locking. The invention also discloses a corresponding implementation method. The invention can reduce the voltage change time of the phase-identifying voltage during frequency hopping or time slot switching, thereby reducing the frequency locking time and meeting the professional application requirement of high phase noise.
Description
Technical Field
The present invention relates to the field of phase-locked loop technology, and in particular, to a phase-locked loop device and an implementation method for reducing frequency locking time in a TDMA (time division multiple access) or fast frequency hopping communication system.
Background
With the rapid development of wireless communication technology, the requirement for the channel resource utilization rate of wireless radio frequency is higher and higher, the channel resource is more and more tense, meanwhile, the requirement for phase noise is also higher for high-performance radio frequency signals in professional application, the locking time of a high-performance phase-locked loop of the existing frequency hopping and TDMA radio frequency system is longer, generally more than 3ms, and the channel or time slot switching time is not greatly improved all the time, so that the channel utilization rate cannot be improved.
Disclosure of Invention
The present invention provides a phase-locked loop device and a method for reducing frequency locking time. The voltage change time of the phase-identifying voltage during frequency hopping or time slot switching can be reduced, so that the frequency locking time is reduced, and the professional application requirement of high phase noise is met.
In order to solve the above technical problem, an aspect of the present invention provides a phase locked loop apparatus for reducing a frequency locking time in a TDMA or fast frequency hopping communication system, comprising:
the phase-locked loop chip comprises a phase discriminator unit, a frequency division unit connected with the phase discriminator unit and a feedback signal frequency division unit; the phase discriminator unit is used for comparing the phase of the reference signal generated by the reference signal unit with the phase of the signal output by the feedback signal frequency division unit to form a phase difference signal;
the loop low-pass filter is connected with the phase discriminator unit and is used for performing low-pass filtering on the phase difference signal;
the voltage-controlled oscillator is connected with the loop low-pass filter, receives the control voltage from the loop low-pass filter, performs frequency control, outputs a local oscillation signal and outputs a feedback signal to the feedback amplifier;
the feedback amplifier is used for receiving a feedback signal of the voltage-controlled oscillator and carrying out amplification processing;
the feedback signal frequency division unit is used for receiving the amplified feedback signal of the feedback amplifier, dividing the frequency and transmitting the frequency divided feedback signal to the phase discriminator unit;
the device is characterized by further comprising a micro-processing unit, and a charging control unit and a discharging control unit which are connected with the micro-processing unit, wherein:
the micro-processing unit is used for determining the charging and discharging type of the loop low-pass filter during frequency switching according to the frequency-voltage corresponding relation of the voltage-controlled oscillator and generating a corresponding charging control instruction and a corresponding discharging control instruction;
the charging control unit is connected with the loop low-pass filter and used for receiving a charging control instruction from the micro-processing unit and charging the loop low-pass filter;
and the discharge control unit is connected with the loop low-pass filter and used for receiving a discharge control instruction from the micro-processing unit and performing discharge processing on the loop low-pass filter.
Preferably, the micro-processing unit further comprises:
the storage unit is used for a preset switching parameter table, and the switching parameter table comprises a charging and discharging capacitance value, a charging and discharging resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charging judgment mark, a discharging judgment mark and charging and discharging speed information;
the charging and discharging judgment unit is used for acquiring a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching from the storage unit according to the current frequency switching, and judging the charging and discharging type of the loop filter, wherein the charging and discharging type comprises charging and discharging;
the charging and discharging time calculation unit is used for calculating and obtaining the charging and discharging time according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charging and discharging capacitance value and the charging and discharging resistance value which are obtained in the storage unit and correspond to the current frequency switching;
and the charge and discharge instruction generating unit is used for generating a charge control instruction or a discharge control instruction according to the charge and discharge type determined by the charge and discharge judging unit and the charge and discharge time calculated by the charge and discharge time calculating unit, and the charge control instruction or the discharge control instruction carries the charge and discharge speed.
Preferably, the micro-processing unit further comprises:
the device comprises a setting unit, a storage unit and a switching parameter table, wherein the setting unit is used for setting the switching parameter table and sending the switching parameter table to the storage unit for storage according to calculation or experimental calibration, and the switching parameter table contains a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each switched channel of the voltage-controlled oscillator, a phase discrimination voltage corresponding to each switched channel, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
Preferably, the charge and discharge time calculation unit calculates the charge and discharge time t by the following equation:
t＝RCLn[V2/(V2-V1)]；
wherein, R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a switched channel, and V1 is a phase discrimination voltage corresponding to a switched channel.
Preferably, the charge and discharge instruction generating unit is specifically configured to:
when the charging and discharging judgment unit determines that the charging is carried out, generating a charging control instruction by combining the charging time calculated by the charging and discharging time calculation unit, and sending the charging control instruction to the charging control unit; or
And when the charging and discharging judgment unit determines that the charging and discharging control unit is discharging, generating a discharging control instruction and sending the discharging control instruction to the discharging control unit by combining the discharging time calculated by the charging and discharging time calculation unit.
As another aspect of the present invention, a method for implementing a phase-locked loop to reduce frequency locking time is further provided, which is implemented by using the previous apparatus, and the method includes the following steps:
step S10, when the phase-locked loop device switches frequency, the micro-processing unit determines to carry out charging action or discharging action on the loop low-pass filter according to the frequency-voltage corresponding relation of the voltage-controlled oscillator, and generates corresponding charging control instruction, discharging control instruction and charging and discharging time;
step S20, the charging control unit receives a charging control instruction from the micro-processing unit and performs charging processing on the loop low-pass filter; or the discharging control unit receives a charging control instruction from the micro-processing unit and performs discharging processing on the loop low-pass filter; thereby achieving a reduction in lock time.
Preferably, the step S10 further includes:
step S100, according to the current frequency switching, obtaining a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching from a storage unit to judge the charging and discharging types of the loop filter, wherein the charging and discharging types comprise charging and discharging;
step S101, calculating and obtaining the charging and discharging time according to the phase discrimination voltage corresponding to the channel before switching and the phase discrimination voltage corresponding to the channel after switching, the charging and discharging capacitance value and the charging and discharging resistance value which are obtained from the storage unit and correspond to the current frequency switching;
step S102, generating a charging control instruction or a discharging control instruction according to the charging and discharging type determined by the charging and discharging judging unit and the charging and discharging time calculated by the charging and discharging time calculating unit.
Preferably, further comprising:
and S000, setting and storing a switching parameter table according to calculation or experimental calibration, wherein the switching parameter table comprises a charging and discharging capacitance value, a charging and discharging resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charging judgment mark, a discharging judgment mark and charging and discharging speed information.
Preferably, the step S101 specifically includes:
the charge and discharge time calculation unit calculates the charge and discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein, R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a switched channel, and V1 is a phase discrimination voltage corresponding to a switched channel.
Preferably, the step S102 specifically includes:
when the charging and discharging judgment unit determines that the charging is carried out, generating a charging control instruction by combining the charging time calculated by the charging and discharging time calculation unit, and sending the charging control instruction to the charging control unit, wherein the charging instruction carries the charging speed; or
And when the charging and discharging judgment unit determines that the charging and discharging control unit is discharging, generating a discharging control instruction by combining the discharging time calculated by the charging and discharging time calculation unit, and sending the discharging control instruction to the discharging control unit, wherein the discharging control instruction carries the discharging speed.
By implementing the embodiment of the invention, the invention has the following beneficial effects:
the invention provides a phase-locked loop device for reducing frequency locking time and a realization method, wherein a charging control unit and a discharging control unit controlled by a microprocessing unit are added on a loop low-pass filter of the existing phase-locked loop device (PLL), and the microprocessing unit can determine to carry out charging action or discharging action on the loop low-pass filter when a system switches channels according to a switching parameter table, so that the time gap of charging and discharging can be adjusted, the switching time is controlled to reduce the conversion time of phase discrimination voltage, and the locking time of the phase-locked loop is greatly reduced;
the invention can greatly reduce the locking time (reaching within 100 us) on the basis of not reducing the output phase noise of the original voltage control oscillator, and the switching data table can carry out higher-precision continuity optimization, so that the locking time is shorter;
the device and the implementation method provided by the invention can be applied to a phase-locked loop circuit in a time division multiple access communication system (TDMA) or a rapid frequency hopping radio frequency system with high phase noise performance requirement, rapid locking can adapt to faster channel switching, time slot switching and frequency hopping with wider bandwidth, and the application prospect is very good.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a phase-locked loop apparatus for reducing frequency locking time according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of one embodiment of the micro-processing unit of FIG. 1;
fig. 3 is a main flow diagram illustrating an implementation method of a phase-locked loop for reducing a frequency locking time according to an embodiment of the present invention;
fig. 4 is a more detailed structural diagram of step S10 in fig. 3.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, a schematic structural diagram of a phase-locked loop apparatus for reducing frequency locking time according to an embodiment of the present invention is shown; referring to fig. 2 together, in this embodiment, the phase-locked loop apparatus for reducing frequency locking time is used in a TDMA or fast frequency hopping communication system, and includes:
the phase-locked loop chip 1 comprises a phase detector unit 10, a frequency division unit 11 and a feedback signal frequency division unit 12, wherein the frequency division unit 11 and the feedback signal frequency division unit 12 are connected with the phase detector unit 10; the phase discriminator unit 10 is configured to perform phase comparison between the reference signal generated by the reference signal unit 2 and the signal output by the feedback signal frequency dividing unit 12 to form a phase difference signal;
the loop low-pass filter 3 is connected with the phase discriminator unit 10 and is used for performing low-pass filtering on the phase difference signal;
the voltage-controlled oscillator 4 is connected with the loop low-pass filter 3, receives the control voltage from the loop low-pass filter 3, performs frequency control, outputs a local oscillation signal required by a radio frequency system, and outputs a feedback signal to the feedback amplifier 5;
the feedback amplifier 5 is used for receiving the feedback signal of the voltage-controlled oscillator 4 and carrying out amplification processing;
the feedback signal frequency dividing unit 12 is configured to receive the amplified feedback signal of the feedback amplifier 5, divide the frequency, and transmit the divided feedback signal to the phase detector unit 10, so that the phase detector unit 10 can implement closed-loop phase locking;
it is understood that the reference signal unit 2, the phase detector unit 10, the frequency dividing unit 11, the feedback signal frequency dividing unit 12, the loop low-pass filter 3, the voltage-controlled oscillator 4 and the feedback amplifier 5 are well known and can be implemented by those skilled in the art, and will not be described in detail herein.
In the phase-locked loop device for reducing the frequency locking time provided by the invention, the phase-locked loop device further comprises a micro-processing unit 6, and a charging control unit 7 and a discharging control unit 8 which are connected with the micro-processing unit 6, wherein:
the micro-processing unit 6 is used for determining the charging action or the discharging action of the loop low-pass filter 3 during frequency switching according to the frequency-voltage corresponding relation of the voltage-controlled oscillator 4 and generating a corresponding charging control instruction and a corresponding discharging control instruction; it can be understood that the charging control command carries information such as charging speed, charging time, and the like; the discharge control instruction carries information such as discharge speed, discharge time and the like;
the charging control unit 7 is connected with the loop low-pass filter 3 and used for receiving a charging control instruction from the micro-processing unit 6 and performing charging processing on the loop low-pass filter 3;
and the discharge control unit 8 is connected with the loop low-pass filter 3 and used for receiving a discharge control instruction from the micro-processing unit 6 and performing discharge processing on the loop low-pass filter 3.
More specifically, in one example, the micro-processing unit 6 further includes:
the setting unit 64 is configured to set a switching parameter table according to calculation or experimental calibration, and send the switching parameter table to the storage unit for storage, where the switching parameter table includes a charge/discharge capacitance value, a charge/discharge resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charge determination flag, a discharge determination flag, and charge/discharge speed information; as shown in table one below, an example handover parameter table is shown:
table-switching parameter table
The data of frequency, phase discrimination voltage and the like in the table are from specification parameters given by hardware design or experimental data. The information of frequency, phase discrimination voltage, charging judgment mark, discharging judgment mark, charging and discharging current and the like when two channels are switched is shown; for example, in one example, the channel needs to be switched from the CH1 channel to the CH6 channel, and the charging process is required because the corresponding charging determination flag is T; the table above only lists the corresponding data for two switching situations, it being understood that in the practical example, the data for all switching situations of the pll device need to be listed.
A storage unit 60, configured to use a preset switching parameter table, where the switching parameter table includes a charge/discharge capacitance value, a charge/discharge resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charge judgment flag, a discharge judgment flag, and charge/discharge speed information;
the charge and discharge judging unit 61 is used for acquiring a charge judging mark and a discharge judging mark corresponding to the current frequency switching from the storage unit according to the current frequency switching, and judging the charge and discharge type of the loop filter, wherein the charge and discharge type comprises charge and discharge;
the charge and discharge time calculation unit 62 is configured to calculate, according to the phase discrimination voltage corresponding to the channel before switching and corresponding to the current frequency switching obtained in the storage unit, the phase discrimination voltage corresponding to the channel after switching, a charge and discharge capacitance value, and a charge and discharge resistance value, so as to obtain the current charge and discharge time;
for example, corresponding to table one, the system including the pll device needs to switch from 905MHz to 934MHz, i.e., from CH1 channel to CH6 channel, and it can be known from table one that the phase-detected voltage is changed from V1 (0.8V) to V2(3.2V), since V2 is greater than V1 and the charging determination flag is T, it is determined that charging is required; the charging time t can be calculated according to the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein, R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a switched channel, and V1 is a phase discrimination voltage corresponding to a switched channel.
Similarly, in the second case of the table, i.e. switching from channel CH15 to channel CH3, it can be seen that the discharge process (discharge determination flag is T) is required, and the discharge time T can be calculated according to the above formula.
A charge and discharge command generating unit 63, configured to generate a charge control command or a discharge control command according to the charge and discharge type determined by the charge and discharge determining unit and according to the charge and discharge time calculated by the charge and discharge time calculating unit, where the charge control command or the discharge control command carries a charge and discharge speed; the method specifically comprises the following steps:
when the charging and discharging judgment unit determines that the charging is carried out, generating a charging control instruction by combining the charging time calculated by the charging and discharging time calculation unit, and sending the charging control instruction to the charging control unit; or
And when the charging and discharging judgment unit determines that the charging and discharging control unit is discharging, generating a discharging control instruction and sending the discharging control instruction to the discharging control unit by combining the discharging time calculated by the charging and discharging time calculation unit.
More specifically, in the embodiment of the present invention, among others, the charge and discharge determination unit, the charge and discharge time calculation unit, the charge and discharge instruction generation unit, and the like included in the micro-processing unit 6 may be implemented by software.
While controlling the charging or discharging of the loop low-pass filter 3, the loop pump current can be instantaneously increased and outputted to the loop low-pass filter 3.
In the embodiment of the invention, a charging control unit and a discharging control unit controlled by a microprocessing unit are added on a loop low-pass filter of the existing phase-locked loop device (PLL), and a switching parameter table operated by software is matched at the same time, so that the time gap of charging and discharging can be adjusted, and the aim of rapidly locking a Voltage Controlled Oscillator (VCO) is achieved.
As another aspect of the present invention, a method for implementing a phase-locked loop to reduce frequency locking time is further provided, which is implemented by using the previous apparatus, and the method includes the following steps:
and step S10, when the phase-locked loop device switches the frequency, the micro-processing unit determines to perform charging action or discharging action on the loop low-pass filter according to the frequency-voltage corresponding relation of the voltage-controlled oscillator and generates a corresponding charging control command or a corresponding discharging control command.
Step S20, the charging control unit receives a charging control instruction from the micro-processing unit and performs charging processing on the loop low-pass filter; or the discharging control unit receives a charging control instruction from the micro-processing unit and performs discharging processing on the loop low-pass filter; thereby achieving a reduction in lock time.
Preferably, the step S10 further includes:
step S100, according to the current frequency switching, obtaining a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching from a storage unit to judge the charging and discharging types of the loop filter, wherein the charging and discharging types comprise charging and discharging;
step S101, calculating and obtaining the charging and discharging time according to the phase discrimination voltage corresponding to the channel before switching and the phase discrimination voltage corresponding to the channel after switching, the charging and discharging capacitance value and the charging and discharging resistance value which are obtained from the storage unit and correspond to the current frequency switching;
step S102, generating a charge control command or a discharge control command according to the charge and discharge type determined by the charge and discharge determination unit and according to the charge and discharge time calculated by the charge and discharge time calculation unit.
Preferably, further comprising:
and S000, setting and storing a switching parameter table according to calculation or experimental calibration, wherein the switching parameter table comprises a charging and discharging capacitance value, a charging and discharging resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charging judgment mark, a discharging judgment mark and charging and discharging speed information.
Preferably, the step S101 specifically includes:
the charge and discharge time calculation unit calculates the charge and discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein, R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a switched channel, and V1 is a phase discrimination voltage corresponding to a switched channel.
Preferably, the step S102 specifically includes:
when the charging and discharging judgment unit determines that the charging is carried out, generating a charging control instruction by combining the charging time calculated by the charging and discharging time calculation unit, and sending the charging control instruction to the charging control unit, wherein the charging instruction carries the charging speed; or
And when the charging and discharging judgment unit determines that the charging and discharging control unit is discharging, generating a discharging control instruction by combining the discharging time calculated by the charging and discharging time calculation unit, and sending the discharging control instruction to the discharging control unit, wherein the discharging control instruction carries the discharging speed.
It will be appreciated that further details of the present embodiment may be found in relation to the foregoing description of fig. 1 and 2 and will not be described in detail herein.
By implementing the embodiment of the invention, the invention has the following beneficial effects:
the invention provides a phase-locked loop device for reducing frequency locking time and a realization method, wherein a charging control unit and a discharging control unit controlled by a microprocessing unit are added on a loop low-pass filter of the existing phase-locked loop device (PLL), and the microprocessing unit can determine to carry out charging action or discharging action on the loop low-pass filter when a system switches channels according to a switching parameter table, so that the time gap of charging and discharging can be adjusted, the switching time is controlled to reduce the conversion time of phase discrimination voltage, and the locking time of the phase-locked loop is greatly reduced;
the invention can greatly reduce the locking time (reaching within 100 us) on the basis of not reducing the output phase noise of the original voltage control oscillator, and the switching data table can carry out higher-precision continuity optimization, so that the locking time is shorter;
the device and the implementation method provided by the invention can be applied to a phase-locked loop circuit in a time division multiple access communication system (TDMA) or a rapid frequency hopping radio frequency system with high phase noise performance requirement, rapid locking can adapt to faster channel switching, time slot switching and frequency hopping with wider bandwidth, and the application prospect is very good.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (10)
1. A phase locked loop device for reducing frequency lock time in a TDMA or fast frequency hopping communication system, comprising:
the phase-locked loop chip comprises a phase discriminator unit, a frequency division unit connected with the phase discriminator unit and a feedback signal frequency division unit; the phase discriminator unit is used for comparing the phase of the reference signal generated by the reference signal unit with the phase of the signal output by the feedback signal frequency division unit to form a phase difference signal;
the loop low-pass filter is connected with the phase discriminator unit and is used for performing low-pass filtering on the phase difference signal;
the voltage-controlled oscillator is connected with the loop low-pass filter, receives the control voltage from the loop low-pass filter, performs frequency control, outputs a local oscillation signal and outputs a feedback signal to the feedback amplifier;
the feedback amplifier is used for receiving a feedback signal of the voltage-controlled oscillator and carrying out amplification processing;
the feedback signal frequency division unit is used for receiving the amplified feedback signal of the feedback amplifier, dividing the frequency and transmitting the frequency divided feedback signal to the phase discriminator unit;
the device is characterized by further comprising a micro-processing unit, and a charging control unit and a discharging control unit which are connected with the micro-processing unit, wherein:
the micro-processing unit is used for determining the charging and discharging type of the loop low-pass filter during frequency switching according to the frequency-voltage corresponding relation of the voltage-controlled oscillator and generating a corresponding charging control instruction and a corresponding discharging control instruction;
the charging control unit is connected with the loop low-pass filter and used for receiving a charging control instruction from the micro-processing unit and charging the loop low-pass filter;
and the discharge control unit is connected with the loop low-pass filter and used for receiving a discharge control instruction from the micro-processing unit and performing discharge processing on the loop low-pass filter.
2. The apparatus of claim 1, wherein the micro-processing unit further comprises:
the storage unit is used for a preset switching parameter table, and the switching parameter table comprises a charging and discharging capacitance value, a charging and discharging resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charging judgment mark, a discharging judgment mark and charging and discharging speed information;
the charging and discharging judgment unit is used for acquiring a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching from the storage unit according to the current frequency switching, and judging the charging and discharging type of the loop filter, wherein the charging and discharging type comprises charging and discharging;
the charging and discharging time calculation unit is used for calculating and obtaining the charging and discharging time according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charging and discharging capacitance value and the charging and discharging resistance value which are obtained in the storage unit and correspond to the current frequency switching;
and the charge and discharge instruction generating unit is used for generating a charge control instruction or a discharge control instruction according to the charge and discharge type determined by the charge and discharge judging unit and the charge and discharge time calculated by the charge and discharge time calculating unit, and the charge control instruction or the discharge control instruction carries the charge and discharge speed.
3. The apparatus of claim 2, wherein the micro-processing unit further comprises:
the device comprises a setting unit, a storage unit and a switching parameter table, wherein the setting unit is used for setting the switching parameter table and sending the switching parameter table to the storage unit for storage according to calculation or experimental calibration, and the switching parameter table contains a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each switched channel of the voltage-controlled oscillator, a phase discrimination voltage corresponding to each switched channel, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
4. The apparatus according to claim 2 or 3, wherein the charge and discharge time calculation unit calculates the charge and discharge time t by the following equation:
t＝RCLn[V2/(V2-V1)]；
wherein, R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a switched channel, and V1 is a phase discrimination voltage corresponding to a switched channel.
5. The apparatus according to claim 4, wherein the charge-discharge instruction generation unit is specifically configured to:
when the charging and discharging judgment unit determines that the charging is carried out, generating a charging control instruction by combining the charging time calculated by the charging and discharging time calculation unit, and sending the charging control instruction to the charging control unit; or
And when the charging and discharging judgment unit determines that the charging and discharging control unit is discharging, generating a discharging control instruction and sending the discharging control instruction to the discharging control unit by combining the discharging time calculated by the charging and discharging time calculation unit.
6. A method for implementing a phase locked loop with reduced frequency lock time, implemented using the apparatus of any of claims 1-5, said method comprising the steps of:
step S10, when the phase-locked loop device switches frequency, the micro-processing unit determines to carry out charging action or discharging action on the loop low-pass filter according to the frequency-voltage corresponding relation of the voltage-controlled oscillator, and generates corresponding charging control instruction, discharging control instruction and charging and discharging time;
step S20, the charging control unit receives a charging control instruction from the micro-processing unit and performs charging processing on the loop low-pass filter; or the discharging control unit receives a charging control instruction from the micro-processing unit and performs discharging processing on the loop low-pass filter; thereby achieving a reduction in lock time.
7. The method of claim 6, wherein the step S10 further comprises:
step S100, according to the current frequency switching, obtaining a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching from a storage unit to judge the charging and discharging types of the loop filter, wherein the charging and discharging types comprise charging and discharging;
step S101, calculating and obtaining the charging and discharging time according to the phase discrimination voltage corresponding to the channel before switching and the phase discrimination voltage corresponding to the channel after switching, the charging and discharging capacitance value and the charging and discharging resistance value which are obtained from the storage unit and correspond to the current frequency switching;
step S102, generating a charging control instruction or a discharging control instruction according to the charging and discharging type determined by the charging and discharging judging unit and the charging and discharging time calculated by the charging and discharging time calculating unit.
8. The method of claim 7, further comprising:
and S000, setting and storing a switching parameter table according to calculation or experimental calibration, wherein the switching parameter table comprises a charging and discharging capacitance value, a charging and discharging resistance value, a phase discrimination voltage corresponding to each channel of the voltage-controlled oscillator before switching, a phase discrimination voltage corresponding to a channel after switching, a charging judgment mark, a discharging judgment mark and charging and discharging speed information.
9. The method according to claim 7 or 8, wherein the step S101 specifically comprises:
the charge and discharge time calculation unit calculates the charge and discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein, R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a switched channel, and V1 is a phase discrimination voltage corresponding to a switched channel.
10. The method according to claim 9, wherein the step S102 specifically includes:
when the charging and discharging judgment unit determines that the charging is carried out, generating a charging control instruction by combining the charging time calculated by the charging and discharging time calculation unit, and sending the charging control instruction to the charging control unit, wherein the charging instruction carries the charging speed; or
And when the charging and discharging judgment unit determines that the charging and discharging control unit is discharging, generating a discharging control instruction by combining the discharging time calculated by the charging and discharging time calculation unit, and sending the discharging control instruction to the discharging control unit, wherein the discharging control instruction carries the discharging speed.
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| CN116405058A (en) * | 2023-06-09 | 2023-07-07 | 中星联华科技（北京）有限公司 | Fast frequency hopping locking circuit and operation method thereof |
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| CN102983860A (en) * | 2012-11-22 | 2013-03-20 | 深圳市森虎科技有限公司 | Method for reducing phase-locked loop (PLL) circuit locking time, PLL circuit and applications of circuit |
| WO2015081564A1 (en) * | 2013-12-06 | 2015-06-11 | 海能达通信股份有限公司 | Frequency synthesis method of fast locking based on phase-locked loop frequency and circuit thereof |
| CN104967448A (en) * | 2015-06-02 | 2015-10-07 | 海能达通信股份有限公司 | Phase-locked loop quick lock circuit and control method thereof |
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| CN102983860A (en) * | 2012-11-22 | 2013-03-20 | 深圳市森虎科技有限公司 | Method for reducing phase-locked loop (PLL) circuit locking time, PLL circuit and applications of circuit |
| WO2015081564A1 (en) * | 2013-12-06 | 2015-06-11 | 海能达通信股份有限公司 | Frequency synthesis method of fast locking based on phase-locked loop frequency and circuit thereof |
| CN104967448A (en) * | 2015-06-02 | 2015-10-07 | 海能达通信股份有限公司 | Phase-locked loop quick lock circuit and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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