CN110995256B - Phase-locked loop device for reducing frequency locking time and implementation method - Google Patents
Phase-locked loop device for reducing frequency locking time and implementation method Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The utility model discloses a phase-locked loop device for reducing frequency locking time, which comprises: the micro-processing unit is used for controlling the charge control unit or the discharge control unit to charge and discharge the loop low-pass filter when the frequency is switched so as to realize quick locking. The utility model also discloses a corresponding implementation method. By implementing the utility model, the voltage change time of the phase discrimination voltage during frequency hopping or time slot switching can be reduced, so that the frequency locking time is reduced, and the professional application requirement of high phase noise is met.
Description
Technical Field
The utility model relates to the technical field of phase-locked loops, in particular to a phase-locked loop device for reducing frequency locking time in a TDMA (time division multiplexing addressing) or quick frequency hopping communication system and an implementation method thereof.
Background
With the rapid development of wireless communication technology, the requirement on the channel resource utilization rate of wireless radio frequency is higher and higher, the channel resource is more and more intense, meanwhile, the requirement on phase noise is also higher for high-performance radio frequency signals in professional application, the locking time of the high-performance phase-locked loop of the existing frequency hopping and TDMA radio frequency system is longer, and is generally more than 3ms, so that the channel or time slot switching time is not improved greatly, and the channel utilization rate cannot be improved.
Disclosure of Invention
The utility model aims to provide a phase-locked loop device for reducing frequency locking time and an implementation method thereof. The voltage change time of the phase discrimination voltage during frequency hopping or time slot switching can be reduced, so that the frequency locking time is reduced, and the professional application requirement of high phase noise is met.
To solve the above technical problem, an aspect of the present utility model provides a phase-locked loop device for reducing frequency locking time, which is used in a TDMA or fast frequency hopping communication system, and includes:
the phase-locked loop chip comprises a phase discriminator unit, a frequency dividing unit and a feedback signal frequency dividing unit, wherein the frequency dividing unit and the feedback signal frequency dividing unit are connected with the phase discriminator unit; the phase discriminator unit is used for comparing the phase of the reference signal generated by the reference signal unit with the phase of the signal output by the feedback signal frequency division unit to form a phase difference signal;
the loop low-pass filter is connected with the phase discriminator unit and is used for carrying out low-pass filtering on the phase difference signals;
the voltage-controlled oscillator is connected with the loop low-pass filter, receives the control voltage from the loop low-pass filter, performs frequency control, outputs a local oscillation signal and outputs a feedback signal to the feedback amplifier;
the feedback amplifier is used for receiving the feedback signal of the voltage-controlled oscillator and amplifying the feedback signal;
the feedback signal frequency dividing unit is used for receiving the amplified feedback signal of the feedback amplifier, dividing the frequency and transmitting the feedback signal to the phase discriminator unit;
the device is characterized by further comprising a micro-processing unit, and a charging control unit and a discharging control unit which are connected with the micro-processing unit, wherein:
the micro-processing unit is used for determining the charge and discharge type of the loop low-pass filter and generating corresponding charge control instructions and discharge control instructions during frequency switching according to the frequency-voltage correspondence of the voltage-controlled oscillator;
the charging control unit is connected with the loop low-pass filter and is used for receiving a charging control instruction from the micro-processing unit and carrying out charging treatment on the loop low-pass filter;
and the discharging control unit is connected with the loop low-pass filter and is used for receiving the discharging control instruction from the micro-processing unit and performing discharging processing on the loop low-pass filter.
Preferably, the micro-processing unit further comprises:
the storage unit is used for a preset switching parameter table, and the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information;
the charge and discharge judging unit is used for obtaining a charge judging mark and a discharge judging mark corresponding to the current frequency switching from the storage unit according to the current frequency switching, and judging the charge and discharge type of the loop filter, wherein the charge and discharge type comprises charge and discharge;
the charge-discharge time calculation unit is used for obtaining the charge-discharge time according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charge-discharge capacitance value and the charge-discharge resistance value which are corresponding to the current frequency switching;
and the charge and discharge instruction generation unit is used for generating a charge control instruction or a discharge control instruction according to the charge and discharge type determined by the charge and discharge judgment unit and the charge and discharge time calculated by the charge and discharge time calculation unit, wherein the charge control instruction or the discharge control instruction carries the charge and discharge speed.
Preferably, the micro-processing unit further comprises:
the setting unit is used for setting a switching parameter table according to calculation or experimental calibration and sending the switching parameter table to the storage unit for storage, wherein the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
Preferably, the charge-discharge time calculation unit calculates the charge-discharge time t with the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a channel after switching, and V1 is a phase discrimination voltage corresponding to a channel before switching.
Preferably, the charge and discharge instruction generation unit is specifically configured to:
when the charge and discharge judging unit determines to charge, generating a charge control instruction by combining the charge time calculated by the charge and discharge time calculating unit and sending the charge control instruction to the charge control unit; or (b)
When the charge and discharge judging unit determines to discharge, a discharge control instruction is generated and sent to the discharge control unit by combining the discharge time calculated by the charge and discharge time calculating unit.
As another aspect of the present utility model, there is also provided a method for implementing a phase locked loop for reducing a frequency locking time, implemented by a device before the implementation, the method including the steps of:
step S10, when the phase-locked loop device switches the frequency, the micro-processing unit determines to carry out charging action or discharging action on the loop low-pass filter according to the frequency-voltage correspondence of the voltage-controlled oscillator, and generates a corresponding charging control instruction, a corresponding discharging control instruction and a corresponding charging and discharging time;
step S20, a charging control unit receives a charging control instruction from a micro-processing unit and performs charging treatment on the loop low-pass filter; or the discharging control unit receives a charging control instruction from the micro-processing unit and performs discharging treatment on the loop low-pass filter; thereby achieving a reduced locking time.
Preferably, the step S10 further includes:
step S100, according to the current frequency switching, a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching are obtained from a storage unit, and the charging and discharging type of the loop filter is judged, wherein the charging and discharging type comprises charging and discharging;
step S101, according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charge-discharge capacitance value and the charge-discharge resistance value which are corresponding to the current frequency switching are obtained in the storage unit, the charge-discharge time is obtained through calculation;
step S102, according to the charge and discharge type determined by the charge and discharge judging unit, and according to the charge and discharge time calculated by the charge and discharge time calculating unit, a charge control instruction or a discharge control instruction is generated.
Preferably, the method further comprises:
step S000, setting and storing a switching parameter table according to calculation or experimental calibration, wherein the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
Preferably, the step S101 specifically includes:
the charge-discharge time calculation unit calculates the charge-discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a channel after switching, and V1 is a phase discrimination voltage corresponding to a channel before switching.
Preferably, the step S102 specifically includes:
when the charging and discharging judging unit determines that charging is performed, generating a charging control instruction according to the charging time calculated by the charging and discharging time calculating unit, and sending the charging control instruction to the charging control unit, wherein the charging instruction carries a charging speed; or (b)
When the charge and discharge judging unit determines to discharge, a discharge control instruction is generated and sent to the discharge control unit in combination with the discharge time calculated by the charge and discharge time calculating unit, wherein the discharge control instruction carries a discharge speed.
By implementing the embodiment of the utility model, the utility model has the following beneficial effects:
the utility model provides a phase-locked loop device for reducing frequency locking time and an implementation method thereof, wherein a charging control unit and a discharging control unit controlled by a micro-processing unit are added on a loop low-pass filter of the existing phase-locked loop device (PLL), the micro-processing unit can determine to carry out charging action or discharging action on the loop low-pass filter according to a switching parameter table when a system carries out channel switching, so that the time gap between charging and discharging can be adjusted, the switching time is controlled to reduce the switching time of phase discrimination voltage, and the locking time of the phase-locked loop is greatly reduced;
the utility model can greatly reduce the locking time (reaching within 100 us) on the basis of not reducing the output phase noise of the original voltage control oscillator, and can perform higher-precision continuous optimization by switching the data table, so that the locking time is shorter;
the device and the implementation method provided by the utility model can be applied to a phase-locked loop circuit in a time division multiple access communication system (TDMA) or a rapid frequency hopping radio frequency system with high phase noise performance requirements, and the rapid locking can adapt to faster channel switching, time slot switching and wider frequency hopping, thereby having good application prospect.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an embodiment of a phase-locked loop device for reducing frequency locking time according to the present utility model;
FIG. 2 is a schematic diagram of one embodiment of the microprocessor unit of FIG. 1;
FIG. 3 is a schematic diagram illustrating a main process of an embodiment of a method for implementing a PLL with reduced frequency lock time according to the present utility model;
fig. 4 is a more detailed schematic diagram of step S10 in fig. 3.
Detailed Description
In order that the above objects, features and advantages of the utility model will be readily understood, a more particular description of the utility model will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model. The utility model may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit or scope of the utility model, which is therefore not limited to the specific embodiments disclosed below.
Referring to fig. 1, a schematic diagram of an embodiment of a pll device for reducing frequency locking time according to the present utility model is shown; as shown in fig. 2, in this embodiment, the phase-locked loop device for reducing the frequency locking time is used in a TDMA or fast frequency hopping communication system, and includes:
the phase-locked loop chip 1 comprises a phase detector unit 10, a frequency division unit 11 and a feedback signal frequency division unit 12, wherein the frequency division unit 11 and the feedback signal frequency division unit 12 are connected with the phase detector unit 10; the phase discriminator unit 10 is configured to perform phase comparison between the reference signal generated by the reference signal unit 2 and the signal output by the feedback signal frequency division unit 12, so as to form a phase difference signal;
a loop low-pass filter 3 connected to the phase detector unit 10 for low-pass filtering the phase difference signal;
the voltage-controlled oscillator 4 is connected with the loop low-pass filter 3, receives the control voltage from the loop low-pass filter 3, performs frequency control, outputs a local oscillator signal required by a radio frequency system, and outputs a feedback signal to the feedback amplifier 5;
a feedback amplifier 5 for receiving the feedback signal of the voltage-controlled oscillator 4 and amplifying the feedback signal;
the feedback signal frequency dividing unit 12 is configured to receive the amplified feedback signal of the feedback amplifier 5, divide the frequency, and transmit the feedback signal to the phase detector unit 10, so that the phase detector unit 10 realizes closed-loop locking of the phase;
it is understood that the reference signal unit 2, the phase detector unit 10, the frequency dividing unit 11, the feedback signal frequency dividing unit 12, the loop low-pass filter 3, the voltage controlled oscillator 4 and the feedback amplifier 5 are well known and can be implemented by those skilled in the art, and will not be described in detail here.
In the phase-locked loop device for reducing frequency locking time provided by the utility model, the phase-locked loop device further comprises a micro-processing unit 6, and a charging control unit 7 and a discharging control unit 8 which are connected with the micro-processing unit 6, wherein:
the micro-processing unit 6 is configured to determine, during frequency switching, to perform a charging operation or a discharging operation on the loop low-pass filter 3 according to the frequency-voltage correspondence of the voltage-controlled oscillator 4, and generate a corresponding charging control instruction and a corresponding discharging control instruction; it can be understood that the charging control instruction carries information such as charging speed, charging time and the like; the discharge control instruction carries the information such as discharge speed, discharge time and the like;
a charging control unit 7, connected to the loop low-pass filter 3, for receiving a charging control instruction from the microprocessor 6, and performing charging processing on the loop low-pass filter 3;
and a discharge control unit 8 connected to the loop low-pass filter 3 for receiving a discharge control instruction from the microprocessor 6 and performing a discharge process on the loop low-pass filter 3.
More specifically, in one example, the micro-processing unit 6 further includes:
the setting unit 64 is configured to set a switching parameter table according to calculation or experimental calibration, and send the switching parameter table to the storage unit for storage, where the switching parameter table includes a charge-discharge capacitance value, a charge-discharge resistance value, a phase-discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase-discrimination voltage corresponding to a channel after switching, a charge judgment flag, a discharge judgment flag, and charge-discharge speed information; as shown in table one below, an example of a handoff parameter table is shown:
list one switching parameter list
The data of the frequency, the phase discrimination voltage and the like in the table come from specification parameters given by hardware design or experimental data. The information such as frequency, phase discrimination voltage, charge judgment mark, discharge judgment mark, charge and discharge current and the like when two channels are switched is shown; for example, in one example, when it is necessary to switch from CH1 channel to CH6 channel, since the corresponding charge determination flag is T, it indicates that the charging process is necessary; the table above only lists the corresponding data of the two types of switching, and it is understood that in practical examples, the data corresponding to all switching situations of the phase-locked loop device need to be listed.
A storage unit 60, configured to preset a switching parameter table, where the switching parameter table includes a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to a channel after switching, a charge judgment flag, a discharge judgment flag, and charge-discharge speed information;
a charge-discharge judging unit 61, configured to obtain, from the storage unit, a charge judgment flag and a discharge judgment flag corresponding to the current frequency switch according to the current frequency switch, and judge a charge-discharge type of the loop filter, where the charge-discharge type includes charge and discharge;
the charge-discharge time calculation unit 62 is configured to calculate a current charge-discharge time according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charge-discharge capacitance value, and the charge-discharge resistance value, which are obtained in the storage unit;
for example, as shown in table one, the system including the pll device needs to switch from 905MHz to 934MHz, i.e. from CH1 channel to CH6 channel, and as can be seen from table one, the phase discrimination voltage changes from V1 (0.8V) to V2 (3.2V), because V2> V1 and the charging determination flag is T, it is determined that charging is needed; the charging time t may be calculated according to the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a channel after switching, and V1 is a phase discrimination voltage corresponding to a channel before switching.
Similarly, in the second case of the table, i.e., switching from the channel CH15 to CH3, it is known from the table that the discharge processing (the discharge judgment flag is T) is required, and the discharge time T can be calculated from the above formula.
A charge-discharge instruction generating unit 63, configured to generate a charge control instruction or a discharge control instruction according to the charge-discharge type determined by the charge-discharge determining unit and the charge-discharge time calculated by the charge-discharge time calculating unit, where the charge control instruction or the discharge control instruction carries a charge-discharge speed; specifically comprising:
when the charge and discharge judging unit determines to charge, generating a charge control instruction by combining the charge time calculated by the charge and discharge time calculating unit and sending the charge control instruction to the charge control unit; or (b)
When the charge and discharge judging unit determines to discharge, a discharge control instruction is generated and sent to the discharge control unit by combining the discharge time calculated by the charge and discharge time calculating unit.
More specifically, in the embodiment of the present utility model, among others, the charge and discharge judgment unit, the charge and discharge time calculation unit, the charge and discharge instruction generation unit, and the like included in the micro-processing unit 6 may be implemented by software.
While the charging or discharging of the loop low-pass filter 3 is controlled, the loop pump current can be instantaneously increased and output to the loop low-pass filter 3.
In the embodiment of the utility model, a charge control unit and a discharge control unit controlled by a micro-processing unit are added on a loop low-pass filter of the existing phase-locked loop device (PLL), and meanwhile, a switching parameter table operated by software is matched, so that the time gap between charge and discharge can be adjusted, the purpose of rapidly locking a voltage-controlled oscillator (VCO) is achieved.
As another aspect of the present utility model, there is also provided a method for implementing a phase locked loop for reducing a frequency locking time, implemented by a device before the implementation, the method including the steps of:
step S10, when the phase-locked loop device switches the frequency, the micro-processing unit determines to charge or discharge the loop low-pass filter according to the frequency-voltage correspondence of the voltage-controlled oscillator, and generates a corresponding charge control instruction or discharge control instruction.
Step S20, a charging control unit receives a charging control instruction from a micro-processing unit and performs charging treatment on the loop low-pass filter; or the discharging control unit receives a charging control instruction from the micro-processing unit and performs discharging treatment on the loop low-pass filter; thereby achieving a reduced locking time.
Preferably, the step S10 further includes:
step S100, according to the current frequency switching, a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching are obtained from a storage unit, and the charging and discharging type of the loop filter is judged, wherein the charging and discharging type comprises charging and discharging;
step S101, according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charge-discharge capacitance value and the charge-discharge resistance value which are corresponding to the current frequency switching are obtained in the storage unit, the charge-discharge time is obtained through calculation;
step S102, a charge control instruction or a discharge control instruction is generated according to the charge and discharge type determined by the charge and discharge judging unit and the charge and discharge time calculated by the charge and discharge time calculating unit.
Preferably, the method further comprises:
step S000, setting and storing a switching parameter table according to calculation or experimental calibration, wherein the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
Preferably, the step S101 specifically includes:
the charge-discharge time calculation unit calculates the charge-discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a channel after switching, and V1 is a phase discrimination voltage corresponding to a channel before switching.
Preferably, the step S102 specifically includes:
when the charging and discharging judging unit determines that charging is performed, generating a charging control instruction according to the charging time calculated by the charging and discharging time calculating unit, and sending the charging control instruction to the charging control unit, wherein the charging instruction carries a charging speed; or (b)
When the charge and discharge judging unit determines to discharge, a discharge control instruction is generated and sent to the discharge control unit in combination with the discharge time calculated by the charge and discharge time calculating unit, wherein the discharge control instruction carries a discharge speed.
It will be appreciated that for more details of this embodiment reference is made to the foregoing description of fig. 1 and 2, and will not be described in detail herein.
By implementing the embodiment of the utility model, the utility model has the following beneficial effects:
the utility model provides a phase-locked loop device for reducing frequency locking time and an implementation method thereof, wherein a charging control unit and a discharging control unit controlled by a micro-processing unit are added on a loop low-pass filter of the existing phase-locked loop device (PLL), the micro-processing unit can determine to carry out charging action or discharging action on the loop low-pass filter according to a switching parameter table when a system carries out channel switching, so that the time gap between charging and discharging can be adjusted, the switching time is controlled to reduce the switching time of phase discrimination voltage, and the locking time of the phase-locked loop is greatly reduced;
the utility model can greatly reduce the locking time (reaching within 100 us) on the basis of not reducing the output phase noise of the original voltage control oscillator, and can perform higher-precision continuous optimization by switching the data table, so that the locking time is shorter;
the device and the implementation method provided by the utility model can be applied to a phase-locked loop circuit in a time division multiple access communication system (TDMA) or a rapid frequency hopping radio frequency system with high phase noise performance requirements, and the rapid locking can adapt to faster channel switching, time slot switching and wider frequency hopping, thereby having good application prospect.
The foregoing is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any person skilled in the art, who is within the scope of the present utility model, should make equivalent substitutions or modifications according to the technical scheme of the present utility model and the inventive concept thereof, and should be covered by the scope of the present utility model.
Claims (10)
1. A phase locked loop apparatus for reducing frequency lock time for use in a TDMA or fast frequency hopping communication system, comprising:
the phase-locked loop chip comprises a phase discriminator unit, a frequency dividing unit and a feedback signal frequency dividing unit, wherein the frequency dividing unit and the feedback signal frequency dividing unit are connected with the phase discriminator unit; the phase discriminator unit is used for comparing the phase of the reference signal generated by the reference signal unit with the phase of the signal output by the feedback signal frequency division unit to form a phase difference signal;
the loop low-pass filter is connected with the phase discriminator unit and is used for carrying out low-pass filtering on the phase difference signals;
the voltage-controlled oscillator is connected with the loop low-pass filter, receives the control voltage from the loop low-pass filter, performs frequency control, outputs a local oscillation signal and outputs a feedback signal to the feedback amplifier;
the feedback amplifier is used for receiving the feedback signal of the voltage-controlled oscillator and amplifying the feedback signal;
the feedback signal frequency dividing unit is used for receiving the amplified feedback signal of the feedback amplifier, dividing the frequency and transmitting the feedback signal to the phase discriminator unit;
the device is characterized by further comprising a micro-processing unit, and a charging control unit and a discharging control unit which are connected with the micro-processing unit, wherein:
the micro-processing unit is used for determining the charge and discharge type of the loop low-pass filter and generating corresponding charge control instructions and discharge control instructions during frequency switching according to the frequency-voltage correspondence of the voltage-controlled oscillator;
the charging control unit is connected with the loop low-pass filter and is used for receiving a charging control instruction from the micro-processing unit and carrying out charging treatment on the loop low-pass filter;
and the discharging control unit is connected with the loop low-pass filter and is used for receiving the discharging control instruction from the micro-processing unit and performing discharging processing on the loop low-pass filter.
2. The apparatus of claim 1, wherein the microprocessor unit further comprises:
the storage unit is used for a preset switching parameter table, and the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information;
the charge and discharge judging unit is used for obtaining a charge judging mark and a discharge judging mark corresponding to the current frequency switching from the storage unit according to the current frequency switching, and judging the charge and discharge type of the loop filter, wherein the charge and discharge type comprises charge and discharge;
the charge-discharge time calculation unit is used for obtaining the charge-discharge time according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charge-discharge capacitance value and the charge-discharge resistance value which are corresponding to the current frequency switching;
and the charge and discharge instruction generation unit is used for generating a charge control instruction or a discharge control instruction according to the charge and discharge type determined by the charge and discharge judgment unit and the charge and discharge time calculated by the charge and discharge time calculation unit, wherein the charge control instruction or the discharge control instruction carries the charge and discharge speed.
3. The apparatus of claim 2, wherein the micro-processing unit further comprises:
the setting unit is used for setting a switching parameter table according to calculation or experimental calibration and sending the switching parameter table to the storage unit for storage, wherein the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
4. A device according to claim 2 or 3, wherein the charge-discharge time calculation unit calculates the charge-discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a channel after switching, and V1 is a phase discrimination voltage corresponding to a channel before switching.
5. The apparatus of claim 4, wherein the charge-discharge instruction generation unit is specifically configured to:
when the charge and discharge judging unit determines to charge, generating a charge control instruction by combining the charge time calculated by the charge and discharge time calculating unit and sending the charge control instruction to the charge control unit; or (b)
When the charge and discharge judging unit determines to discharge, a discharge control instruction is generated and sent to the discharge control unit by combining the discharge time calculated by the charge and discharge time calculating unit.
6. A method of implementing a phase locked loop with reduced frequency lock time, implemented with an apparatus as claimed in any one of claims 1 to 5, the method comprising the steps of:
step S10, when the phase-locked loop device switches the frequency, the micro-processing unit determines to carry out charging action or discharging action on the loop low-pass filter according to the frequency-voltage correspondence of the voltage-controlled oscillator, and generates a corresponding charging control instruction, a corresponding discharging control instruction and a corresponding charging and discharging time;
step S20, a charging control unit receives a charging control instruction from a micro-processing unit and performs charging treatment on the loop low-pass filter; or the discharging control unit receives a charging control instruction from the micro-processing unit and performs discharging treatment on the loop low-pass filter; thereby achieving a reduced locking time.
7. The method of claim 6, wherein said step S10 further comprises:
step S100, according to the current frequency switching, a charging judgment mark and a discharging judgment mark corresponding to the current frequency switching are obtained from a storage unit, and the charging and discharging type of the loop filter is judged, wherein the charging and discharging type comprises charging and discharging;
step S101, according to the phase discrimination voltage corresponding to the channel before switching, the phase discrimination voltage corresponding to the channel after switching, the charge-discharge capacitance value and the charge-discharge resistance value which are corresponding to the current frequency switching are obtained in the storage unit, the charge-discharge time is obtained through calculation;
step S102, according to the charge and discharge type determined by the charge and discharge judging unit, and according to the charge and discharge time calculated by the charge and discharge time calculating unit, a charge control instruction or a discharge control instruction is generated.
8. The method as recited in claim 7, further comprising:
step S000, setting and storing a switching parameter table according to calculation or experimental calibration, wherein the switching parameter table comprises a charge-discharge capacitance value, a charge-discharge resistance value, a phase discrimination voltage corresponding to each channel before switching of the voltage-controlled oscillator, a phase discrimination voltage corresponding to the channel after switching, a charge judgment mark, a discharge judgment mark and charge-discharge speed information.
9. The method according to claim 7 or 8, wherein the step S101 specifically comprises:
the charge-discharge time calculation unit calculates the charge-discharge time t by the following formula:
t＝RCLn[V2/(V2-V1)]；
wherein R is a charge-discharge resistance value, C is a charge-discharge capacitance value, V2 is a phase discrimination voltage corresponding to a channel after switching, and V1 is a phase discrimination voltage corresponding to a channel before switching.
10. The method as set forth in claim 9, wherein the step S102 specifically includes:
when the charging and discharging judging unit determines that charging is performed, generating a charging control instruction according to the charging time calculated by the charging and discharging time calculating unit, and sending the charging control instruction to the charging control unit, wherein the charging control instruction carries a charging speed; or (b)
When the charge and discharge judging unit determines to discharge, a discharge control instruction is generated and sent to the discharge control unit in combination with the discharge time calculated by the charge and discharge time calculating unit, wherein the discharge control instruction carries a discharge speed.
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| CN102983860A (en) * | 2012-11-22 | 2013-03-20 | 深圳市森虎科技有限公司 | Method for reducing phase-locked loop (PLL) circuit locking time, PLL circuit and applications of circuit |
| WO2015081564A1 (en) * | 2013-12-06 | 2015-06-11 | 海能达通信股份有限公司 | Frequency synthesis method of fast locking based on phase-locked loop frequency and circuit thereof |
| CN104967448A (en) * | 2015-06-02 | 2015-10-07 | 海能达通信股份有限公司 | Phase-locked loop quick lock circuit and control method thereof |
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| CN102983860A (en) * | 2012-11-22 | 2013-03-20 | 深圳市森虎科技有限公司 | Method for reducing phase-locked loop (PLL) circuit locking time, PLL circuit and applications of circuit |
| WO2015081564A1 (en) * | 2013-12-06 | 2015-06-11 | 海能达通信股份有限公司 | Frequency synthesis method of fast locking based on phase-locked loop frequency and circuit thereof |
| CN104967448A (en) * | 2015-06-02 | 2015-10-07 | 海能达通信股份有限公司 | Phase-locked loop quick lock circuit and control method thereof |
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