JP2010200064A - Pll circuit, pll circuit radio communication device, and method of detecting lock of the pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit configurable with a digital circuit, and capable of suppressing occurrence of an error or loss of lock detection and reducing a detection time, a radio communication device, and a method of detecting a lock. <P>SOLUTION: Detection is carried out using detection results by a plurality of lock detection parts 6b-1 to 6b-n different in window width. A lock determination part 7 detects a lock state based on the detection results by the plurality of lock detection parts 6b-1 to 6b-n. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present application relates to a PLL circuit, a wireless communication device, and a lock state detection method for the PLL circuit.

Currently, wireless communication is used in various fields from cellular phones to car key locks, but a PLL circuit is usually used for a wireless device that performs wireless communication.
The use of a PLL circuit for a radio has been performed for a long time, and various proposals have been made for that purpose. For example, Patent Document 1 discloses a synchronous detection type PLL circuit including a synchronous detection circuit in which the synchronous detection circuit is configured not to perform asynchronous detection due to jitter or noise.

  Since a small wireless device is operated by a battery or a battery, it is necessary to reduce power consumption even in a PLL circuit in order to extend the life of these power sources. Therefore, in the PLL circuit, if it can be detected as soon as possible that the oscillation frequency is in a stable locked state at the start of operation, communication is performed after lock detection, so that power consumption can be reduced.

Conventional lock detection of a PLL circuit has used a method of counting output pulses (XUP / DOWN) of a phase comparator or a method of detecting fluctuations in the control voltage of the VCO.
Among these, the method of counting the output pulses of the phase comparator detects the lock state by equalizing the number of the two types of output pulses XUP / DOWN of the phase comparator when the pull-in of the PLL circuit converges.

JP 63-035039 A

  The above-described method for counting the output pulses of the phase comparator requires about several thousand pulses with the reference clock as the detection time in order to reliably detect the lock. If the detection time is shortened, there is a problem that the lock state is erroneously detected before the pull-in is completed.

Further, the conventional method has a problem that a so-called lost occurs, in which it is determined that the lock is released again after detecting the lock state.
It is an object of the present invention to provide a PLL circuit, a wireless communication device, and a lock detection method that can be configured by a digital circuit, can suppress the occurrence of lock detection errors and lost, and can reduce the detection time. And

  The PLL circuit according to the present invention includes a phase comparison unit that compares a phase difference between a fundamental frequency signal and a feedback signal of the PLL circuit, and a sensitivity that detects phase difference information output from the phase comparison unit based on the phase difference. And a lock determination unit that determines a lock state of the PLL circuit based on detection results by the plurality of lock detection units.

  The PLL circuit wireless communication apparatus according to the present invention includes a PLL circuit and an amplification unit that amplifies the output of the PLL circuit and outputs the amplified signal to an antenna. The PLL circuit includes a fundamental frequency signal and a feedback signal of the PLL circuit. A phase comparison unit that compares the phase difference between the phase detection unit, a plurality of lock detection units having different sensitivities for detecting phase difference information output from the phase comparison unit based on the phase difference, and detection results by the plurality of lock detection units And a lock determination unit that determines a lock state of the PLL circuit based on the PLL circuit wireless communication device.

  The PLL circuit lock detection method according to the present invention detects a pulse in two signals output as a comparison result from a phase comparison unit constituting the PLL circuit with a plurality of sensitivities, and a detection result based on the plurality of sensitivities. Based on the above, lock detection is performed.

  The present invention can suppress the occurrence of lock detection errors and the occurrence of lost, and can shorten the detection time.

It is a principle block diagram of a general PLL circuit provided with a lock detector of an output pulse count method of a phase comparator. It is a block diagram which shows the structure of the PLL circuit of this embodiment. It is a figure which shows the structure of a lock | rock detection part. It is a figure which shows the time chart of the lock | rock detection by the lock | rock detection part of FIG. It is a figure which shows the state transition of a lock | rock detection part. It is a figure which shows each signal at the time of simulating operation | movement of a lock | rock detection part. It is a figure which shows the PLL circuit provided with two lock | rock detection parts. 8 is a time chart showing the operation of the PLL circuit of FIG. It is a figure which shows the structure of the lock determination part which performs lock determination with the change rate of the signal CDTC output from a correlation part. It is a figure which shows the lock | rock detection result by the PLL circuit using the lock | rock determination part of FIG. It is a figure which shows the 2nd form of a lock | rock detection part. It is a time chart which shows the timing of the signal in the lock | rock detection part of a 2nd form, and the signal input / output. It is a figure which shows the structure of the lock | rock detection part of 3rd Embodiment. It is a block diagram which shows the structure of the communication apparatus using the PLL circuit in this embodiment.

An embodiment of the present invention will be described below with reference to the drawings.
In the following example, the PLL circuit according to the present embodiment is not an Integer-PLL (IPLL) that sets an oscillation frequency with an integer ratio of a reference clock, but a Fractional-N PLL (FPLL) that sets an oscillation frequency in a fixed-point format. The case where it is applied will be described as an example.

  The FPLL can set the oscillation frequency with high resolution without dividing the reference clock (Refclk). Therefore, the feedback loop responds faster than IPLL that divides the reference clock.

  FPLL is characterized by high resolution of oscillation frequency and fast loop response. Therefore, since convergence is quick and the speed from start to lock is high, the effect of making lock detection early is great. For example, in a configuration in which lock detection is used as a trigger for activation in a communication device or the like, the operation recovery time from power down can be shortened by detecting the lock state immediately after the pull-in is completed.

FIG. 1 is a principle block diagram of a general PLL circuit including a lock detector of an output pulse count method of a phase comparator.
The PLL circuit 10a shown in FIG. 1 includes a phase comparator (PFD) 1, a charge pump (CP) 2, a loop filter (LPF) 3, a voltage controlled oscillator (VCO) 4, a frequency divider 5, and a lock detector 6a. Have.

  The phase comparator 1 compares a reference clock signal (Ref clock) having a natural frequency based on oscillation of a crystal resonator input from a basic clock oscillator (not shown) and a feedback signal divided by the frequency divider 5, A pulse signal (XUP / DOWN signal) based on the frequency difference and phase difference between the two signals is output to the charge pump 2. The phase comparator 2 pulses the XUP signal when the feedback signal is delayed with respect to the reference clock signal, and conversely outputs the DOWN signal when the feedback signal is advanced with respect to the reference clock signal.

  The charge pump 2 converts the phase difference detected by the phase comparator 1 into a control signal (control voltage) for the voltage controlled oscillator 4. The charge pump 2 outputs a control signal based on the two pulse signals (XUP / DOWN signal) output from the phase comparator 1 to the loop filter 3. The output signal of the charge pump 2 is a direct current component including a pulse component, and the direct current component changes with the frequency variation of the pulse signal, and the pulse component changes based on the phase difference of the pulse signal. .

  The loop filter 3 outputs an output signal obtained by smoothing the output signal of the charge pump 2 and removing a high-frequency component to the voltage controlled oscillator 4 as a control voltage. The voltage controlled oscillating unit 4 outputs an output signal fout having a frequency corresponding to the control voltage input from the loop filter 3 to an external circuit and also outputs it to the frequency dividing unit 5.

  The frequency divider 5 is a circuit that divides the output fout of the voltage controlled oscillator 4 and outputs it to the phase comparator 2. The frequency divider 5 can freely switch the frequency division ratio based on an instruction from the outside, and the oscillation frequency of the output signal fout can be controlled by changing the frequency division ratio. When the PLL circuit 10a is an FPLL, the frequency dividing ratio by the frequency dividing unit 5 is a fractional frequency dividing ratio whose ratio to the reference frequency is not an integer. In the case of the FPLL PLL circuit 10a, the frequency divider 5 can be realized by substantially performing fractional frequency division by finely changing the frequency division ratio. For example, the frequency division by 2.5 can be substantially realized by repeating the frequency division by 2 and the frequency division by 3.

  The lock detection unit 6a counts the pulse signal (XUP / DOWN signal) output from the phase comparator 1 and, if the number of pulses of the two signals coincides within a specific period, outputs an LCDT signal indicating lock detection. Output.

  The PLL circuit of this embodiment includes a plurality of lock detection units that perform pulse counting of signals output from the phase comparator. Each lock detection unit has a different detection time (hereinafter referred to as a window) for detecting a pulse.

  If the window width of the lock detection unit is increased, the frequency of lost decreases, but the detection time increases. Conversely, if the window width is reduced, the detection time is reduced, but the frequency of errors is increased.

In the PLL circuit of this embodiment, lock detection is performed using detection results from a plurality of lock detection units having different window widths.
FIG. 2 is a block diagram showing the configuration of the PLL circuit of this embodiment.

  When the PLL circuit 10b of FIG. 2 is compared with the PLL circuit 10a of FIG. 1, the phase comparator 1, the charge pump 2, the loop filter 3, the voltage controlled oscillator (VCO) 4, and the frequency divider 5 are basically shown. Since it is substantially the same as that of the first PLL circuit 10a, the same reference numerals are given and description thereof is omitted.

Comparing the PLL circuit 10a of FIG. 1 with the PLL circuit 10b of FIG. 2, the PLL circuit 10b further includes a plurality of lock detection units 6b-1 to 6b-n and a lock determination unit 7.
The plurality of lock detection units 6b-1 to 6b-n have different window widths. The lock determination unit 7 detects that the PLL circuit 10b is locked based on the detection results of the lock detection units 6b-1 to 6b-n.

FIG. 3 is a diagram illustrating a configuration of the lock detection unit 6b.
In the figure, the lock detection unit 6b receives the XUP / DOWN signal output from the phase comparator 1, and performs lock detection by counting the rising edges of each XUP / DOWN signal.

  In the figure, a lock detection unit 6b outputs an XUP counter (xupcnt) 11 that counts the number of pulses of the XUP signal, a DOWN counter (downcnt) 12 that counts the number of pulses of the DOWN signal, and outputs of the XUP counter 11 and the DOWN counter 12. An AND circuit 13 that takes a logical product, a control logic (Control Logic) that changes the window width of the lock detection unit 6b and controls the output based on a set value WDTC [2: 0] given from the outside and a signal ENDTC 14 and a flip-flop 15 for generating a lock detection output LCDT.

  The XUP counter 11 and the XDOWN counter 12 are counters that count the number of pulses of the XUP signal and the DOWN signal output from the phase comparator 1. When the count number reaches a specified value (for example, 3 for a 2-bit counter), “1” is set. Output. When the CLR signal is input from the control logic 14, the count value is cleared and the count is restarted from the beginning. The AND circuit 13 normally outputs “0” (CLR of the flip-flop 15) to the flip-flop 15, and “1” (SET of the flip-flop 15) when both the UP counter 11 and the DOWN counter 12 count the specified value. Is output to the flip-flop 15.

  The control logic 14 is a controller that operates in synchronization with the reference clock Refclk, and outputs a CLR signal to the UP counter 11 and the DOWN counter 12 at a cycle based on a preset value of the window width WDTC. Further, when “1” is input as an enable signal (ENDTC) from the outside to the lock detection unit 6b, the control logic 14 outputs an UPDATE signal to the flip-flop 15 to update the flip-flop 15 and enable it. When “0” is input as a signal, the input of the UPDATE signal to the flip-flop 15 is stopped, and the lock detecting unit 6b is disabled.

  The flip-flop 15 is a flip-flop that operates in synchronization with the reference clock Refclk. When the signal from the AND circuit 13 is “0” (CLR), the flip-flop 15 does not detect the lock, so the lock detection output LCDT is “0”, and the signal from the AND circuit 13 is “1”. In the case of (SET), since the number of pulses of the XUP signal and the DOWN signal is the same, and lock is detected, “1” is output as the lock detection output LCDT.

  In this way, the lock detection unit 6b counts the number of pulses of the XUP / DOWN signal output from the phase comparator 1 with the window width of the set value WDTC, and if the two match, the lock detection output LCDT is set to '1. 'Make it.

Further, all of the PLL circuit 10b of FIG. 2 may be a digital circuit.
In the configuration of FIG. 2, the lock detection unit 6b sets the lock detection output LCDT to “1” when the number of pulses of the XUP signal and the number of pulses of the DOWN signal completely match. The output LCDT may be set to “1”.

FIG. 4 is a diagram showing a time chart of lock detection by the lock detector 6b of FIG.
The figure shows an example where the lock detection unit 6b is designated with a reference clock Refclk of 10 clocks as the window width value WDTC, and the UP counter 11 and the DOWN counter 12 are counters capable of counting up to 4. ing.

  In the figure, when the XUP signal indicating that the feedback signal is delayed is input as (1), (2),..., The value (UPCNT) of the XUP counter 11 is 1, 2,.・ ・ It will be counted as. Similarly, when the DOWN signal indicating that the feedback signal is advanced is input as (1), (2),..., The value (UPCNT) of the DOWN counter 12 is 1, 2,. Will be counted. Since the UP counter 11 and the DOWN counter 12 can only count up to 4, even if (5) and (6) are input as the UP signal and the DOWN signal, the values of the UP counter 11 and the DOWN counter 12 remain at 4. is there.

  Since the window width is equal to the reference clock Refclk 10 clocks, the lock detection unit 6b determines lock detection in ST10. In this example, since the two counter values are both 4, the lock is detected and the lock detection output LCDT becomes “1”.

FIG. 5 is a diagram illustrating a state transition of the lock detection unit 6b.
In the figure, when both XRST, which is a reset signal for the entire PLL circuit 10b, and ENDTC, which is an enable signal for the lock detector 6b, are both “0”, the initial state (ST = 0) remains unchanged. When both XRST and ENDTC are '1', the lock detection unit 6b operates, the state transitions to ST1, ST2, ..., and the value set as WDTC is the count number of the reference clock Refclk. When they match, the state transitions to PLL lock determination. In the figure, the values of WDTC are 8, 14, and 15, and the state transits to the PLL lock determination at ST8, ST14, and ST15, respectively.

FIG. 6 is a diagram illustrating each signal when the operation of the lock detection unit 6b is simulated.
In the figure, the reference clock (REFCLK), the XUP signal / DOWN signal input from the phase comparator 1, the control voltage VCTRL signal input to the voltage controlled oscillator 4, and the LDTC signal output from the lock detector 6b are shown. It is displayed.

  As shown in the figure, when the VCTRL signal is rising, the XUP signal is output, and when it is falling, a lot of the DOWN signal is output, and when it is in a constant state, the XUP signal and the DOWN signal are output almost uniformly. I understand that.

  The output LDTC signal of the lock detection unit 6b generated by counting the XUP / DOWN signal causes a false detection of the lock state or a so-called lost that is canceled once the lock state is detected.

When the window width is narrowed in this way, the lock detection unit 6b performs erroneous detection of the locked state or causes loss.
Therefore, in the PLL circuit 10b in the present embodiment, lock detection is performed using detection results obtained by the plurality of lock detection units 6b having different window widths.

FIG. 7 is a diagram illustrating a PLL circuit 10c including two lock detection units 6c-1 and 6c-2.
In the figure, the outputs of the lock detection unit 6c-1 in which a narrow window width is set and the lock detection unit 6c-2 in which a wide window width is set are input to the lock determination unit 7c.

  The lock determination unit 7c includes a shift register (SFRN) 21 to which an output of the lock detection unit 6c-1 having a narrow window width is input, and a shift register (SFRW) to which an output of the lock detection unit 6c-2 having a wide window width is input. 22 and the outputs of the two shift registers 21 and 22 are input, the correlation unit 23 that calculates the moving average addition of these inputs, and the value obtained by the moving average addition output from the correlation unit 23 and the threshold value RFLVL are compared. When the output of the unit 23 becomes equal to or greater than the threshold value RFLVL, a comparison / determination unit 24 that sets the Lock signal indicating lock detection to “1” is provided.

The operation of the PLL circuit 10c of FIG. 7 will be described with reference to the time chart of FIG.
The time chart of FIG. 8 discloses the output LCDTN-out of the lock detector 6c-1 having a narrow window width, the output LCDTW-out of the lock detector 6c-2 having a wide window width, and the output CDTC of the correlator 23. ing.

  In LCDTN-out indicating the result of lock detection performed with a narrow window width, the lock state is detected relatively early. However, it is relatively easy to cause a false detection, and there is a high possibility that a so-called lost will occur after the locked state is detected and the locked state is released.

  On the other hand, in the LCDTW-out indicating the result of performing lock detection with a wide window width, the lock state is relatively slowly detected. However, it is relatively unlikely to be erroneously detected or lost.

  The narrow window width and the wide window width are appropriately set according to the period of the swell of the oscillation output fout until the PLL circuit 10c is locked, the usage environment, and the like. The period of this undulation is determined by the characteristics of the loop of the PLL circuit 10c (determined by the gain of the charge pump 2 and the voltage controlled oscillator 4, the transfer function of the loop filter 3, etc.).

  In the following description, the narrow window width set in the lock detection unit 6c-1 is 1/10 of the swell cycle, and the wide window width set in the lock detection unit 6c-2 is 1/0 of the swell cycle. 4 is set.

In the PLL circuit 10c in the present embodiment, the lock determination unit 7c determines whether or not the PLL circuit 10c is locked using the detection results based on these two types of window widths.
In the lock determination unit 7c, the output LCDTN-out from the lock detection unit 6c-1 with a narrow window width is output to the shift register 21, and the output LCDTW- from the lock detection unit 6c-2 with a wide window width is set. out is stored in the shift register 22. The correlator 23 performs a moving average addition on the values accumulated in the two shift registers 21 and 22, converts the added value into a voltage value, and outputs a signal CDTC.

An example of the signal CDTC is shown in the time chart of FIG.
The output LCDTN-out from the lock detector 6c-1 and the output LCDTW-out from the lock detector 6c-2 are stored in the shift registers 21 and 22 in FIG. The correlation unit 23 obtains a moving average addition value of the values of LCDTN-out and LCDTW-out using the value accumulated in the shift register. For example, if the shift registers 21 and 22 are 4-bit shift registers and '1100' is stored in the shift register 21 and '0101' is stored in the shift register 22, the correlation unit 23 is {(1 + 1 + 0 + 0) + (0 + 1 + 0 + 1). )} / 8 = 0.5, and a signal having this voltage value is output to the comparison / determination unit 24 as an output signal CDTL.

FIG. 8 shows the states of LCDTN-out, LCDTW-out, and CDTL.
When LCDTN-out and LCDTW-out continue to indicate lock detection, the value of the signal CDTL increases. The comparison / determination unit 24 monitors the value of the signal CDTL, and when the value becomes equal to or greater than the threshold value RFLVL, sets the Lock signal indicating that the lock has been detected to “1”.

As described above, in the PLL circuit 10c according to the present embodiment, lock detection is performed using detection results obtained by a plurality of lock detection units 6c having different window widths.
As a result, lock detection can be performed earlier than when the window width is widened, and the possibility of erroneous detection or lost is less than when the window width is narrowed.

Next, the lock determination unit 7d that can detect the lock earlier than the lock determination unit 7c shown in FIG. 7 will be described.
The lock determination unit 7d performs lock determination based on the rate of change (slope) of the signal CDTC, not the magnitude of the signal CDTC output from the correlation unit 23.

  FIG. 9 is a diagram illustrating a configuration of the lock determination unit 7d that performs lock determination based on the change rate (slope) of the signal CDTC output from the correlation unit 23. In FIG. 9, the configurations of the shift registers 21, 22 and the correlation unit 23 are basically the same as those described with reference to FIG. The lock determination unit 7d performs digital processing by sampling the input signal CDTC, but a circuit for this sampling is also omitted in FIG.

9 includes a first delay circuit (Z ⁻¹ ) 31, a second delay circuit (Z ⁻ⁿ ) 32, a subtraction circuit 33, a second delay circuit 33, and a second delay circuit 33 c. 3 delay circuits (Z ⁻¹ ) 34, a shifter 35, and a fourth delay circuit (Z ⁻¹ ) 36.

Among these components, the first delay circuit 31, the third delay circuit 34, and the first delay circuit 31 are delay circuits that delay input data by one sampling cycle. The second delay circuit 32 is a circuit that accumulates input data for n sampling cycles. The value of n is an arbitrary value and is an appropriate value obtained in advance from the output state of the fourth delay circuit 36. The subtraction circuit 33 subtracts the output value of the first delay circuit 31 from the output value of the second delay circuit 32. The shifter 35 shifts the output value of the third delay circuit 34 to the right by n bits to make the value 1/2 ⁿ . The right shift by the shifter 35 suppresses erroneous determination by shortening the bit length of the data handled by the determination unit 24 except for the lower bits.

  The determination unit 24 compares the value output from the fourth delay circuit 36 with a preset threshold value RFLVL, and outputs a Lock signal indicating lock detection when both match or nearly match.

  In the configuration of FIG. 9, the output signal CDTC of the correlation unit 23 is differentiated, but the output signal CDTC is evaluated using a value based on the differential value of the signal CDTC for the threshold value RFLVL given to the determination unit 24. Thus, the threshold value RFLVL may be dynamically changed.

FIG. 10 is a diagram illustrating a lock detection result by the PLL circuit 10d using the lock determination unit 7d of FIG.
In the figure, the lock detection signal LCDT41 when lock detection is performed by one lock detection unit 6a shown in FIG. 1, the output LCDTN-out42 of the lock detection unit 6c-1 with a narrow window width, the window The output LCDTW-out43 of the lock detection unit 6c-2, the output value 44 of the correlation unit 23d, the differential value 45 of the output value 44, and the output value 46 of the lock determination unit 7d are set.

  As shown in the figure, the output value 46 of the lock determination unit 7d shows a value simulating the differential value 45. At a time point 47 when the output value 46 becomes equal to or greater than a specific value, the lock determination unit 7d determines that a lock has been detected, and outputs a Lock signal.

As a result, the PLL circuit 10d according to the present embodiment can perform lock detection in a shorter time and can suppress the occurrence of lock detection errors and lost.
Next, a second form of the lock detection circuit 6 will be described.

FIG. 11 is a diagram illustrating a second form of the lock detection unit.
The lock detection unit 6e of the second embodiment does not detect the lock by counting the number of pulses of the XUP / DOWN signal as in the lock detection unit 6b of FIG. 3, but increases the pulse width of the XUP / DOWN signal. Count and perform lock detection.

  In addition to the XUP / DOWN signal from the phase comparator 2, the lock detection unit 6 e in FIG. 11 receives the output fout of the voltage controlled oscillation unit 4. Then, using this fout, the pulse width of the XUP / DOWN signal is converted into the number of pulses of fout, and the number of pulses is counted.

  In the figure, the lock detection unit 6e includes a NOT circuit 51, an AND circuit 52, an AND circuit 53, an XUP counter (xupcnt) 54, a DOWN counter (xdwncnt) 55, a first comparator (Comparator 1) 56, and a second comparison. A comparator (Comparator 2) 57, an AND circuit 58, a control logic (Control Logic) 59, and a flip-flop (F / F) 60 are provided.

  The NOT circuit 51 inverts the XUP signal, which is a negative logic signal. The AND circuits 52 and 53 convert the pulse width of the XUP / DOWN signal into the number of pulses of fout. The XUP counter 54 is a counter that counts the number of pulses of the pulse signal output from the AND circuit 52. The DOWN counter 55 is a counter that counts the number of pulses of the pulse signal output from the AND circuit 53. The first comparator 56 compares the pulse width count value (PXUPnum) output from the XUP counter 54 with the pulse width determination value (Pwdth), and if the pulse width count value is larger, the first comparator 56 sets the AND circuit 58 to “1”. Is output. The second comparator 57 compares the pulse width count value (PDWNum) output from the DOWN counter 55 with the pulse width determination value (Pwdth), and if the pulse width count value is larger, the AND circuit 58 receives “1”. 'Is output. The AND circuit 58 takes an AND of the results of comparison by the first comparator 56 and the second comparator 57. The control logic 59 controls the lock detection unit 6e as a whole, and changes the window width of the lock detection unit 6b and controls the output based on a set value (pulse width determination value Pwdth) given from the outside and the signal ENDTC. To do. The flip-flop 60 generates a lock detection output LCDT based on the output of the AND circuit 58.

  The pulse width of the XUP / DOWN signal output from the phase comparator 2 is counted using the high-frequency signal fout output from the voltage controlled oscillator 4 as a clock, and the count value is integrated.

  Since the XUP signal is negative logic, after being input to the NOT circuit 51, the DOWN signal is directly input to the AND circuits 52 and 53 and ANDed with the signal fout to convert the pulse width into the number of pulses. The number of pulses output from the AND circuit 52 is counted by the XUP counter 54, and the number of pulses output from the AND circuit 53 is counted by the DOWN counter 55. The XUP counter 54 and the XDOWN counter 55 are counters that output the count number as it is, and their output values are input to the first comparator 56 and the second comparator 57.

  The control logic 59 outputs a CLR signal to the XUP counter 54, the DOWN counter 55, and the flip-flop 60 at a cycle based on a preset ENDTC value. When the CLR signal is input from the control logic 59, the XUP counter 54 and the XDOWN counter 55 clear the count value and start counting again from the beginning.

  The first comparator 56 and the second comparator 57 compare the preset pulse width determination value Pwdth with the count values obtained by the UP counter 54 and the DOWN counter 55, and generally count value integration result pulses. When it coincides with the width judgment value Pwdth, “1” is output. The AND circuit 58 receives the outputs of the first comparator 56 and the second comparator 57 as inputs, and when both the outputs of the first comparator 56 and the second comparator 57 become “1”, the flip-flop A signal '1' for setting 60 is output.

  When the LCDT, which is the output of the flip-flop 60, becomes “1”, “1” is output from the AND circuit 58. At this time, when the count values of the UP counter 54 and the DOWN counter 55 reach the pulse width determination value, that is, the pulse widths of the UP signal and the DOWN signal output from the phase comparator 1 are both specified values (pulse width determination). When the value Pwdth) is reached. Therefore, the lock detection unit 6e counts the pulse width of the UP / DOWN signal in the window width set as the ENDTC value, and detects that the PLL circuit 10e is locked when the integration result exceeds a specific value. The LCDT signal is set to “1”.

  In the configuration of FIG. 11, when the integrated value of the number of pulses corresponding to the pulse width of the XUP signal completely matches the integrated value of the number of pulses corresponding to the pulse width of the DOWN signal, the lock detection unit 6e outputs the lock detection output. Although the LCDT is set to “1”, the lock detection output LCDT may be set to “1” when the two substantially match.

FIG. 12 is a time chart showing the timing of the signals in the lock detection unit 6e in FIG.
As shown in the figure, the XUP / DOWN signal is output in synchronization with the reference clock (Refclk). In the lock detection unit 6e, the pulse width when the XUP signal is “0” and the DOWN signal is “1”. The pulse width at this time is counted by the number of pulses of the output signal fout of the PLL circuit 10e using the lock detector 6e.

In FIG. 12, until the first XUP signal pulse, the output of the XUP counter 54 outputs the value n ₀ counted so far, and after the first XUP signal pulse, the pulse width of the first XUP signal is set to n _0. n ₀ + n ₁ plus the value n ₁ the corresponding is outputted from the XUP counter 54 until the next pulse, the value n is subsequent pulse plus a value n ₂ corresponding to the pulse width n ₀ + n _{1 0} + n ₁ + n ₂ is output. Similarly, the DOWN counter 55 outputs the value m ₀ counted until then until the first DOWN signal pulse, and the value m ₁ corresponding to the pulse width of the first DOWN signal at m ₀ after the first DOWN signal pulse. the m ₀ + m ₁ plus is outputted from between DOWN counter 55 until the next pulse, the value m ₀ + m ₁ + m ₂ plus the value m ₂ since the next pulse corresponding to the pulse width m ₀ + m ₁ Is output.

  As described above, the lock detection unit 6e detects the lock state not from the number of pulses of the UP / DOWN signal but from the pulse width, so that the lock detection can be performed more accurately than the detection by the number of pulses.

Next, the lock detection part of 3rd Embodiment is demonstrated.
FIG. 13 is a diagram illustrating a configuration of the lock detection unit 6f of the third embodiment.
The lock detection unit 6f of the third embodiment can set two window widths (W_WDTC, N_WDTC), and can change the window width in the middle to change the lock detection sensitivity. ing.

  13 includes a first counter (W_xupcnt) 71 and a third counter (W_dwncnt) 73 that count the XUP signal and the DOWN signal when W_WDTC is set as the window width setting value. A second counter (N_xupcnt) 72 and a fourth counter (N_dwncnt) 74 for counting the XUP signal and the DOWN signal when N_WDTC is set as the setting value of the width, the first selector (Selector) 75, the second A selector 76, an AND (and) circuit 77, a control logic 78, and a flip-flop (F / F) 79 are included.

  As described above, the lock detection unit 6f of the third embodiment includes two sets of counters 71 and 73 and 72 and 74, and pulses of the UP / DOWN signal output from the phase comparator 1 with different window widths. Count the number. Then, the first to fourth counters 71, 72, 73, 74 output “1” when the count number reaches a specified value. The first to fourth counters 71, 72, 73, 74 clear the count value when the control logic 78 receives a W_CLR signal based on the value of W_WDTC or an N_CLR signal based on the value of N_WDTC. Start counting again.

  The first selector 75 selects the output of the first counter 71 or the output of the second counter 72 based on the WINDOW_SEL signal input from the outside, and outputs it to the AND circuit 77. Similarly, the second selector 76 selects the output of the third counter 73 or the output of the fourth counter 74 based on the WINDOW_SEL signal and outputs the selected output to the AND circuit 77. The window width of the lock detection unit 6f is switched by the selection of the selectors 75 and 76 by the WINDOW_SEL signal. In this switching, when the WINDOW_SEL signal selects the value by the W_WDTC as the window width, the outputs of the first and third counters 71 and 73 are selected, and the WINDOW_SEL signal selects the value by the N_WDTC as the window width. The outputs of the second and fourth counters 72 and 74 are selected.

  The AND circuit 77 takes an AND of the values selected and output by the first selector 75 and the second selector 76. The AND circuit 77 outputs ‘1’ (set) to the Philip flop 79 when the two inputs are both 1, that is, when the count values of the UP signal and the DOWN signal both exceed the specified value. In synchronization with the reference clock (REFCLK), the flip-flop outputs “1” when the input from the AND circuit 77 is “1” (set), and “0” when it is “0” (reset). Output as.

  In the PLL circuit 10f in which the lock detection unit 6f having such a configuration is used, lock detection is first performed with a narrow window width setting (N_WDTC), and after it is determined that the lock state is established, FIG. As shown, the sensitivity is made dull by changing to a wide window width setting (W_WDTC). As a result, it is possible to prevent the occurrence of lost after detecting the lock.

  The configuration of the lock detector 6f shown in FIG. 13 is an example, and two sets of counters are provided in order to make the purpose of the lock detector 6f easier to understand. However, the configuration of the lock detection unit 6f according to the third embodiment is not limited to this, and includes a set of counters. When these counters have a window width based on W_WDTC and the window width based on N_WDTC, In both cases, the number of pulses or the pulse width may be counted.

Next, a communication device using the PLL circuit in this embodiment will be described.
FIG. 14 is a block diagram showing a configuration of a communication device using a PLL circuit in the present embodiment.

  In the figure, a communication device 80 includes a power amplifier 82, a VCO control unit (VCO CAL) 83, a clock generator (CLK GEN) 84, and a clock driver 85 in addition to the PLL circuit 81 in the present embodiment described above. is doing. The PLL circuit 81 includes a phase comparator 91, a charge pump 92, a loop filter 93, a voltage control oscillation unit (VCO) 94, a frequency division unit 95, a lock detection unit 96, and a lock determination unit 97. Among these, the voltage control oscillation unit 94 is connected to a power source and an inductor 87 from the outside, and the charge pump 92 is connected to a power source.

  The power amplifier 82 amplifies the output fout of the PLL circuit 81 and outputs a transmission wave from the transmission antenna 86 connected to the outside. Further, the power amplifier 82 turns ON / OFF the output to the transmission antenna 86 based on the Lock signal output from the lock determination unit 97 in the PLL circuit 81. The VCO control unit 83 performs control such as initial setting of the oscillation frequency of the voltage controlled oscillation unit 94 in the PLL circuit 81. The VCO control unit 83 includes a plurality of internal registers and operates based on these settings. The internal register includes a CALEN register for setting whether to operate the VCO control unit 83, a PHEF register for setting the maximum value of the oscillation frequency of the voltage control oscillation unit 94, and the oscillation frequency of the voltage control oscillation unit 94. There are a PHEL register for setting a minimum value, a DSPP register for setting a default value of the oscillation frequency of the voltage controlled oscillator 94, and the like. These internal registers are set by a control circuit outside the communication device 80. The clock generator 84 branches the clock signal output from the clock driver 85 into a plurality or divides the frequency. The clock driver 85 applies a voltage to a crystal resonator connected to the communication device 80 to oscillate a clock signal.

  In the communication device 80 having such a configuration, when the power is turned on, the signal fout is oscillated from the PLL circuit 81. However, the lock signal becomes “0” until the frequency of fout is stabilized and lock is detected. ing. While the Lock signal is “0”, the power amplifier 82 stops the output to the transmission antenna 86. When the Lock signal becomes ‘1’ and the lock state is detected, the power amplifier 82 outputs a transmission wave to the transmission antenna 86.

  As described above, the communication device using the PLL circuit 81 according to the present embodiment outputs a transmission wave when the Lock signal becomes “1”, but the PLL circuit 81 according to the present embodiment locks the moment of the transient response. Therefore, the communicator 80 can shorten the time from power-on to transmission wave oscillation. Therefore, the power required for transmission can be reduced, and the usage time of a power source such as a battery can be extended.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
A PLL circuit comprising:
A phase comparator that compares the phase difference between the fundamental frequency signal and the feedback signal of the PLL circuit;
A plurality of lock detection units having different sensitivities for detecting phase difference information output from the phase comparison unit based on the phase difference;
A lock determination unit that determines a lock state of the PLL circuit based on detection results by the plurality of lock detection units;
A PLL circuit comprising:
(Appendix 2)
The PLL circuit according to claim 1, wherein the sensitivity is a count period of a pulse output from the phase comparator based on the phase difference.
(Appendix 3)
The lock determination unit performs moving average addition of output values from the plurality of lock detection units, and detects the lock state by comparing a determination value obtained from the result of the moving average addition with a threshold value. The PLL circuit according to appendix 1, wherein:
(Appendix 4)
The lock determination unit further includes a shift register unit that stores output values from each of the plurality of lock detection units, and the moving average addition is realized by performing an addition average of values in the shift register units. The PLL circuit according to appendix 3, characterized by:
(Appendix 5)
The PLL circuit according to appendix 3, wherein the determination value is a result of the moving average addition.
(Appendix 6)
The PLL circuit according to appendix 3, wherein the determination value is a temporal change value as a result of the moving average addition.
(Appendix 7)
The PLL circuit according to appendix 3, wherein the threshold value is obtained by time differentiation of the result of the moving average addition.
(Appendix 8)
The PLL circuit according to appendix 1, wherein the lock detection unit can change the sensitivity.
(Appendix 9)
The PLL circuit according to appendix 8, wherein when the lock determination unit determines the detection of the locked state, the plurality of lock detection units reduce the sensitivity.
(Appendix 10)
The phase comparator includes, as the phase difference information, a first pulse corresponding to a case where the phase of the fundamental frequency signal is ahead of the phase of the feedback signal, and the phase of the fundamental frequency signal is the phase of the feedback signal. Outputs a second pulse corresponding to the case where it is later than
The PLL circuit according to appendix 2, wherein the lock detection unit performs the lock detection based on counting the number of pulses of the first pulse and the number of pulses of the second pulse in the counting period.
(Appendix 11)
The phase comparator includes, as the phase difference information, a first pulse corresponding to a case where the phase of the fundamental frequency signal is ahead of the phase of the feedback signal, and the phase of the fundamental frequency signal is the phase of the feedback signal. Outputs a second pulse corresponding to the case where it is later than
The PLL circuit according to appendix 1, wherein the lock detection unit performs the lock detection based on a pulse width of the first pulse and a pulse width of the second pulse.
(Appendix 12)
The PLL circuit according to appendix 1, wherein the PLL circuit is a fractional-N PLL.
(Appendix 13)
A PLL circuit;
An amplification unit that amplifies the output of the PLL circuit and outputs the amplified output to the antenna;
The PLL circuit includes:
A phase comparator that compares the phase difference between the fundamental frequency signal and the feedback signal of the PLL circuit;
A plurality of lock detection units having different sensitivities for detecting phase difference information output from the phase comparison unit based on the phase difference;
A PLL circuit wireless communication apparatus, comprising: a lock determination unit that determines a lock state of the PLL circuit based on detection results of the plurality of lock detection units.
(Appendix 14)
Also, the PLL circuit lock detection method according to the present invention uses the phase difference information output from the phase comparator included in the PLL circuit based on the phase difference between the reference frequency signal and the feedback signal of the PLL circuit with a plurality of sensitivities. And detecting lock based on the detection results of the plurality of sensitivities.

1, 91 Phase comparator 2, 92 Charge pump 3, 93 Loop filter 4, 94 Voltage controlled oscillator 5, 95 Divider 6a, 6b, 6e, 96 Lock detector 7, 7c, 97 Lock determiner 10a, 10b 10f, 81 PLL circuit 11, 54 XUP counter 12, 55 DOWN counter 13, 52, 53, 58, 77 AND circuit 14, 59 Control logic 15, 60 Flip-flop 21, 22 Shift register 23 Correlation unit 24 Comparison determination unit 51 NOT circuit 56 1st comparator 57 2nd comparator 71 1st counter 72 2nd counter 73 3rd counter 74 4th counter 75 1st selector 76 2nd selector 80 Communication device 82 Power amplifier 83 VCO control unit 84 Clock generator 85 Driver 86 Transmission Antenna 87 inductor 88 crystal oscillator

Claims (5)

A PLL circuit comprising:
A phase comparator that compares the phase difference between the fundamental frequency signal and the feedback signal of the PLL circuit;
A plurality of lock detection units having different sensitivities for detecting phase difference information output from the phase comparison unit based on the phase difference;
A lock determination unit that determines a lock state of the PLL circuit based on detection results by the plurality of lock detection units;
A PLL circuit comprising:   The PLL circuit according to claim 1, wherein the sensitivity is a count period of a pulse output from the phase comparator based on the phase difference.   The PLL circuit according to claim 1, wherein the lock detection unit can change the sensitivity. A PLL circuit;
An amplification unit that amplifies the output of the PLL circuit and outputs the amplified output to the antenna;
The PLL circuit includes:
A phase comparator that compares the phase difference between the fundamental frequency signal and the feedback signal of the PLL circuit;
A plurality of lock detection units having different sensitivities for detecting phase difference information output from the phase comparison unit based on the phase difference;
A PLL circuit wireless communication apparatus, comprising: a lock determination unit that determines a lock state of the PLL circuit based on detection results of the plurality of lock detection units. A lock detection method for a PLL circuit,
Detecting phase difference information output from a phase comparator included in the PLL circuit based on a phase difference between a reference frequency signal and a feedback signal of the PLL circuit with a plurality of sensitivities;
A lock detection method for a PLL circuit, wherein lock detection is performed based on detection results of the plurality of sensitivities.