JP2009515488A - Nonlinear feedback control loop as a spread spectrum clock generator. - Google Patents

Abstract

This patent disclosure relates to generating random spread for a clock signal that provides the maximum possible power density reduction due to spurious radiation generated from the clock signal and its harmonics. Figure 1 illustrates a circuit, system and method for spreading a clock signal.
These novel inventions use a non-linear feedback control loop 116 for assistance in generating a spread spectrum clock, and without using expensive shielding or other EMI suppression methods, An electronic product is obtained that can pass FCC requirements for spurious radiation generated by harmonics.
[Selection] Figure 5

Description

  The present invention relates to the field of digital signal processing, and in particular, the present invention relates to methods, circuits, and systems for improving a spread spectrum clock generator.

  Spread spectrum clock generators have become very popular in electronic products, especially PCs, in the last decade. This technique effectively reduces the peak intensity of the spurious emission of the clock signal and its harmonics, allowing the PC to be assembled with fewer RF shields. In other words, it passes the electromagnetic interference (EMI) requirements set by the FCC of the electronic product while reducing cost, weight and time. The principle of this technique is to evenly spread the frequency of the clock signal over a fraction of the bandwidth of the clock frequency so that the radiated clock signal energy does not always stay at one fixed frequency. As a result, the peak intensity of spurious emissions from the clock frequency and its harmonic clock signal is diffused and greatly reduced. The amount of reduction in peak spurious radiation is determined by how the clock signal is spread. The most common method of spreading the frequency of the clock signal uses a triangular modulation signal with a linear increase and decrease to spread the clock signal frequency evenly by a small percentage of the clock frequency. That is. A typical reaction of clock spreading with a triangular modulation signal is as shown in FIG. Spreading effectively reduces the peak intensity of the clock signal radiation by a spreading loss 102 of typically only 8 to 14 db in current technology. Unfortunately, spreading with triangular modulation spends more time on the clock signal staying at both ends of the spread, so the energy spectrum of the clock signal always peaks at both ends of the clock spectrum. While many techniques have been developed over the past decade to improve the spread waveform and the clock energy can be spread more uniformly, all current techniques are overkill. This is because all the spreading functions used today are deterministic while random noise is required to spread the clock signal truly uniformly as shown in FIG. Unfortunately, it is very difficult to implement a spread signal system inside an IC to spread a clock signal with random noise using current technology. Therefore, a better and simpler method of spreading the clock signal more uniformly with random noise is highly desirable to further reduce the peak intensity of spurious radiation and its harmonics.

  Currently, there are many ways to spread the clock signal, the simplest way is to dither the PLL programmable divider to produce the modulated clock signal, the most complex The method is to use a lookup table to store the spreading function for the modulation of the clock signal. Both methods produce a smooth modulated signal to spread the frequency of the VCO. US Pat. No. 5,610,955 shows the first method and US Pat. No. 6,377,646 B1 shows the second approach. As explained earlier, these methods provide a smooth deterministic function for the modulation of the VCO so that the energy level of the spurious clock radiation signal is still very concentrated. As a result, current technology reduces the spurious clock radiant energy peak by 8-14 db, depending on the spreading factor. US Pat. No. 5,506,545 provides an analog solution that uses a noise source to spread the VCO. While this solution provides true random broadband spreading to the clock signal, it is very difficult to incorporate this analog design into an integrated circuit.

  Four novel methods and systems are disclosed. They use a non-linear feedback control loop to generate a spread spectrum clock signal, mostly having a digital design, suitable for implementation in an IC.

  The principle behind these techniques is to destabilize the nonlinear feedback control loop and create a vibration at a specific frequency. On the other hand, the broadband noise specific to the loop also controls the modulation of the feedback module of the loop. Broadband noise modulation can provide a higher spreading loss 161, with much the same amount of frequency spreading as the triangular modulation 102 shown in FIG. 1, lowering the peak energy of spurious clock radiation much more than that. The energy spectrum of the clock signal modulated by broadband random noise is also much smoother than the energy spectrum of the clock signal modulated by triangular modulation. For clock signals that are modulated by broadband random noise, the energy of the spurious clock radiation signal is reduced to the minimum possible because the clock signal does not stay regularly at one frequency or phase. As a result, random noise modulation can greatly improve diffusion loss compared to conventional triangular modulation under the same spreading factor.

  By using the inherent noise of the non-linear feedback control loop to modulate the oscillation of the clock signal, the spread spectrum is easily modulated with random broadband noise inside the IC with minimal hardware because the noise is already in the loop A clock generator can be built. These functions of the present invention will be described in detail with reference to the drawings.

(Cross-reference with related applications)
This application is filed with US provisional application 60 / 734,222 filed November 7, 2005, US provisional application 60 / 737,592 filed November 17, 2005, and US provisional application filed December 6, 2005. Application 60 / 742,764, US provisional application 60 / 756,040 filed January 4, 2006, US provisional application 60 / 757,645 filed January 10, 2006, June 27, 2006. US provisional application 60 / 805,900, US provisional application 60 / 806,639 filed July 6, 2006, US provisional application 60 / 823,339 filed August 23, 2006, and 2006 PCT / US05 / 26842 filed July 28, 2005 and PCT / US0 filed May 4, 2006 in relation to US provisional application 60 / 827,288 filed September 23, / 17856 also relates to, the entire contents of which are incorporated herein by reference.

Best Mode for Carrying Out the Invention The present invention relates to systems, methods and circuits, and uses a non-linear feedback control loop to evenly spread the energy of the clock signal over a fraction of the bandwidth of the clock frequency. There are four different nonlinear feedback control loops in this disclosure: nonlinear arrival time locked loops 150, 152, nonlinear frequency locked loops 196, 213, nonlinear phase locked loops 171, 166, and nonlinear amplitude locked loop 135 output. is there. Nonlinear feedback control loops are quite different from normal linear feedback control loops, such as linear phase locked loops or linear frequency locked loops. For the linear feedback control loop 100 shown in FIG. 2, the output signal of the loop—which is the final error correction output 115 for the feedback module 105—is a linear function of the error input signal 114 shown in FIG. The feedback module 105 is linearly corrected by the polarity and amplitude of the error input signal 114 to produce a feedback signal 112 that always tracks the reference signal 110. If a low-pass filter is used as the forward module 163, this low-pass filter prevents the feedback signal 112 from changing rapidly and following the reference signal 110 too close. As a result, this filter helps to remove unwanted fluctuations in the reference input signal 110 and can provide a clean and stable feedback output signal 112 generated from the noisy reference input signal 110.

  The conversion characteristics of the final error correction output 115 of the linear feedback control loop 100 shown in FIG. 3 was obtained by comparing single events from both inputs to the error detector 101 when the loop was opened. Ideally, the final error correction output 115 remains at a fixed constant bias when there is no error between the two input signals, such that the zero error input signal 114 produces a zero final error correction output 115. There must be. The final error correction output 115 is larger or smaller from a constant bias point depending on the polarity of the error input signal 114. The amount of final error correction output 115 generated for a fixed constant bias point depends linearly on the absolute value of the error input signal 114. As a result, the larger the error input signal 114, the more final error correction output 115 is generated from the feedback module 105 to correct the feedback signal 112, and there is no error between the two input signals. The feedback signal 112 can always track the reference input signal 110 until is zero.

  In order to implement the linear feedback control loop 100, a linear error detector 101 that generates an error output signal 117 from an error between two input signals linearly is required. The error detector 101 can be conceptually divided into two blocks, a difference block 103 and a gain block 107. The difference block 103 provides the conceptual error input signal 114 to the feedback control loop 100 and the gain block 107 that generate the actual error output signal 117 for driving the forward module 163. This technique of conceptually dividing the error detector 101 into two blocks extracts the gain for the feedback control loop 100 and helps to easily understand the operation of the loop 100.

  Traditionally, the error input signal 114 was considered to be the output signal of the feedback control loop 104 and the reference input signal 110 was merely an input signal to the feedback control loop system 104, as shown in FIG. This definition seems very logical to define all signals associated with the feedback signal 112 as output signals; however, under this definition it is very difficult to analyze the loop 104. First, the reference input signal 110 is just one of the input signals to the error detector 101 that is a node of the loop (not part of the loop). As shown in FIG. 2, the linear feedback control loop 100 includes only three modules: the error detector 101, the forward module 163, and the feedback module 105, but does not directly include the reference input signal 110. The feedback control loop 104 is not actually directly connected to the reference input signal 110, and treating the reference input signal 110 as an input to the feedback control loop system 104 is a critical mistake. Second, since there is no start and end in the feedback control loop 104, there is really no way to analyze the feedback control loop 104 alone. The only way to solve these problems is to conceptually divide the error detector 101 into two blocks and define the error input signal 114 as an input to the feedback control loop 100, as shown in FIG. Defining the final error correction output 115 of the forward module 163 as the only output of the control loop 100, the purpose of the feedback module 105 is feedback to track the reference signal 110 for the final error correction output signal 115. The output signal 112 is generated and the error input signal 114 is finally generated for the feedback control loop 100.

  With this new definition, the function of each block of the loop 100 is clearly understood. By taking a derivative of the final error correction output 115 versus a derivative of the error input signal 114, the gain of the feedback control loop 100 is easily known. In the definition of the conventional feedback control loop 104 shown in FIG. 4, two loop gains are used: an open loop gain and a closed loop gain. The open loop gain 113 (A) is defined as a combination of the gains of the error detector 101 and the forward module 163, and the closed loop gain is a product of the open loop gain 113 (A) and the feedback module 105 (β) (multiplication product). Defined. The big problem with this definition is that it is very difficult to combine the gain of the error detector 101 with the gain of the forward module 163 because they are completely different devices, and measure it directly. It is also very difficult to characterize the combined open loop gain 113. Even when the combined open loop gain 113 is measured, some small important details of the open loop gain 113, such as the singularities caused by the discontinuities in the conversion characteristics, are easily overlooked and neglected. It will be. Second, depending on the type of loop, the closed loop gain has a different physical meaning, and the loop gain is no longer an appropriate term to describe the product of the open loop gain 113 and the feedback module 105. Nevertheless, these two names are used in this disclosure because they have been used for a long time.

  Using a technique that conceptually divides the error detector 101, the error detector 101 must be characterized separately from the rest of the loop 100. The error detector 101 can be characterized simply by theory or by measuring the device itself. When there are a plurality of loops 100, it is usually not difficult to find discontinuities in the conversion characteristics of the error detector 101 in which the loops 100 gradually become independent. Once the error detector 101 is characterized, the conversion characteristics of the final error correction output 115 and the loop gain can be easily found.

  As shown in FIG. 2, for a first-order linear feedback control loop 100 that tracks only one variable, eg, an AGC loop or an AFC loop, the product of open loop gain 113 (A) and feedback module 105 (β) is Determine how closely the feedback signal 112 tracks the reference input signal 110. As a classical analysis of the conventional feedback control loop 104, the linear feedback control loop 100 can be analyzed as follows. Since the open loop gain 113 (A) is contributed by both the gain of the error detector 107 and the gain of the forward module 163, the feedback signal 112 is multiplied by the open loop gain 113 (A) and the feedback module (β) 105. Equal to error input signal 114.

  The feedback signal 112 is expressed as follows.

V _f = (V _ref −V _f ) * A * β Equation 1
The feedback signal can be solved from Equation 1 as follows:

V _f = V _ref * Aβ / (1 + Aβ) Equation 2
Thus, the feedback signal 112 is equal to the reference signal 110 only if Aβ is infinite. To ensure that the feedback signal 112 is truly fixed to the reference signal 110, the closed loop gain must be infinite, regardless of what the polarity of the closed loop gain is when the closed loop gain is infinite. Since there are two solutions to the linear linear equation, the irrelevance of the polarity of the closed loop gain indicates the unstable nature of Equation 2.

  As shown in FIG. 6, by using the linear error detector 101 to generate a linear error output 117 followed by an amplifier with infinite gain 130 to convert the linear error output 117 to a bipolar decision output 123, or As shown in FIG. 5, there are two ways of generating an infinite closed loop gain for the feedback control loop by using a non-linear error comparator 118 to directly generate a bipolar decision output 123. OPAMP is typically used as an amplifier with infinite gain 130. This is because OPAMP is configured as an active integrator that can easily generate infinite DC. However, OPAMP is a linear device that requires a lot of circuitry and consumes more current. As the design of FIG. 5 is a preferred design for a non-linear feedback control loop, a solution using non-linear error comparator 118 is therefore usually a simpler and better option that provides infinite gain. .

  Non-linear error comparator 118 can only generate decision output 123 in two digital states, H or L, regardless of the amount of error input 114. Even when the amplitude of the error input 114 grows linearly from 0 to infinity, since the decision output 123 of the nonlinear error comparator 118 remains constant, the effective gain of the nonlinear error comparator 118 maintains a constant output. Therefore, it must be generated in proportion to 1 / (error input). As a result, the gain of the nonlinear error comparator 118 approaches infinity when the error input 114 is zero.

  If the non-linear feedback control loop completely locks the local feedback signal 112 to the reference input signal 110, the final error correction output 115 is always maintained at a constant DC to produce a stable feedback signal 112 equal to the reference input signal 110. No further corrections to the feedback module 105 are needed anymore, two input signals to the non-linear error comparator 118 or linear error detector 101 (from the reference input 110 and from the feedback output 112). ) Is fixed and always equal, the error input signal 114 is always zero. As a result, for example, using a non-linear error comparator 118 to provide an infinite loop gain to the loop when the error input 114 is zero, or from the zero error input 114 using, for example, an OPAMP configured as an active filter. By providing an infinite DC gain to the loop to produce a finite final error correction output 115 at a constant DC, the loop can be kept stationary. The linear error detector 101 with the nonlinear error comparator 118 used in FIG. 5 and the amplifier with the infinite gain 130 used in FIG. 6 is required to support the nonlinear feedback control loops 116 and 120. Can provide.

  The linear feedback control loop 100 with infinite closed loop gain becomes the non-linear feedback control loops 116 and 120 shown in FIGS. The reason it becomes a non-linear feedback control loop is that the final error correction output 115 for the feedback module 105 has only two stable digital states, H or L, as shown in FIG. The conversion characteristics of the final error correction output 115 for the feedback module 105 shown in FIG. 7 shows that a single event from each two input signals to the nonlinear error comparator 118 or linear error detector 101 when the nonlinear feedback control loop is opened. Obtained by comparing (single event). For the design of the non-linear feedback control loop 116 using the non-linear error comparator 118 shown in FIG. 5, the non-linear error comparator 118 is in the current state forever until the polarity of the error input signal 114 is changed. The decision output 123 of the error comparator 118 remains H when the error input signal 114 is positive, and remains L when the error input signal 114 is negative, regardless of the strength of the error input signal 114. When the nonlinear error comparator 118 compares single events from both inputs, the decision output 123 of the nonlinear error comparator 118 remains in either the H or L state forever, so the nonlinear error comparator 118 There is nothing in the feedback control loop 116 so that the final error correction output 115 is driven to the rail of the power supply and the loop 116 does not become a non-linear feedback control loop. For the design of the non-linear feedback control loop 120 using the linear error detector 101 with an amplifier with infinite gain 130 shown in FIG. 6, the decision output 123 of the amplifier 130 is forever when the error input signal 114 is positive. Since it remains H and remains forever when the error input signal 114 is negative, the output of the final error correction output 115 is like the final error correction output 115 generated from the non-linear error comparator 118. It is.

  As described above, the conversion characteristic of the final error correction output 115 of the linear feedback control loop 100 is linear, so that the final error correction output 115 can be generated according to the polarity and magnitude of the error input 114. The conversion characteristics of the final error correction output 115 of the non-linear feedback control loops 116 and 120 are binary and are generated by the polarity of the error input signal 114 in the two digital states. The conversion characteristics of the linear feedback control loop shown in FIG. 3 and the non-linear feedback control loop shown in FIG. 7 are obtained from each two inputs to the non-linear error comparator 118 and the linear error detector 101 when the loop is open. Obtained by comparing a single event, which theoretically simply provides a single input signal to both the reference input 110 and the feedback input 112 and examines the final error correction output 115. It is possible to specify whether the feedback control loop is linear or nonlinear. If the final error correction output 115 simply stays on either the positive or negative power rail, the loop must be a non-linear feedback control loop, and if the final error output 115 stays on a level other than the positive or negative power rail, It must be a linear feedback control loop. In essence, the final error correction output 115 of the linear feedback control loop 100 never reaches the positive or negative power rail to either the positive or negative rail. Unfortunately, if there is leakage current around the loop filter that generates and maintains the final error correction output signal 115, or the linear dynamic range of the linear error detector 101 is too small, the linear error detector 101 If even the large error input 114 saturates easily, the leakage current will reach any one of the plurality of power rails, regardless of the leakage current weakness, if sufficient time is reached. Can be pushed. As a result, if sufficient time or a sufficiently large error input signal 114 is provided, the linear feedback control loop 100 can actually be a non-linear feedback control loop. On the other hand, if the operating frequency of the nonlinear feedback control is too high and the decision output 123 and the final error correction output 115 never reach the rails of the power supply due to device slew rate limiting, the nonlinear feedback control loop is It becomes a linear feedback control loop. Therefore, if sufficient time and a sufficiently large error input signal 114 are provided, the linear feedback control loop can become a nonlinear feedback control loop, and if less time is provided, the nonlinear feedback control can also be applied to the linear feedback control loop. Can be. As a result, for the feedback control loop, a time limit should be applied as well as a limit on the error input signal 114 when reviewing and generating the conversion characteristics in FIGS. The time limit must be adapted to the actual operating frequency of the loop, and the error input signal 114 must be the actual maximum error input signal that can occur in the system. Unless an appropriate time limit and a limit on the error input signal 114 are used to perform the measurement of the final error correction output 115, the type of feedback control loop is never determined correctly.

  When operating or designing a feedback control loop, it is important to determine whether the feedback control loop is linear or non-linear because the feedback control loop works quite differently in each situation. It is particularly important for linear feedback control loops that use small capacitors for loop filters and operate at low comparison frequencies. Because the small capacitor cannot maintain the charge in the loop filter for a very long time, the final error correction voltage 115 is quickly charged or discharged after the error correction is finished, and is non-linear before the linear feedback control loop knows. This is because it can be a feedback loop.

  The non-linear feedback control loop shown in FIG. 5 includes three modules, a non-linear error comparator 118, a forward module 163, and a feedback module 105. Based on the difference between the reference input signal 110 and the feedback signal 112 from the feedback module 105, the non-linear error comparator 118 generates a decision output signal 123 in one of two digital states, H or L. Two digital states at the decision output 123 of the non-linear error comparator 118 can be described as positive or negative output in two polarities. The polarity of the decision output signal 123 is determined by the polarity of the error input signal 114 that is also a difference signal between the reference input signal 110 and the feedback signal 112 from the feedback module 105. When error input 114 is positive, decision output 123 of nonlinear error comparator 118 is H, and when error input 114 is negative, decision output 123 of nonlinear error comparator 118 is L. The decision output 123 of the error comparator 118 can only be influenced by the polarity of the error input signal 114, not the amplitude of the error input signal 114. The non-linear error comparator 118 is very different from the linear error detector 101. For the linear error detector 101 shown in FIG. 6, the polarity and amplitude of the error output signal 117 at the output of the linear error detector 101 are affected by the polarity and amplitude of the error input signal 114. As a result, an amplifier with infinite gain 130 is required to convert the linear error output signal 117 from the linear error detector 101 into a bipolar digital decision output 123. Thus, linear error detector 101 having an amplifier with infinite gain 130 effectively becomes a non-linear error comparator 118. As a result, the non-linear feedback control loop 120 is also formed from the four components shown in FIG. 6, namely the linear error detector 101, the amplifier with infinite gain 130, the forward module 163 and the feedback module 105.

  After passing through the forward module 163, the decision output 123 becomes the final error correction output 115 for controlling the feedback module 105. The feedback module 105 then generates a corrected feedback output signal 112 to the non-linear error comparator 118 and the linear error detector 101 to close the loop. If the reference signal 110 is greater than the feedback signal 112, the nonlinear error comparator 118 and the linear error detector 101 cause the feedback module 105 to increase the feedback signal 112 to reduce the difference between the reference input signal 110 and the feedback signal 112. In addition, a positive decision output 123 is generated. If the reference signal 110 is less than the feedback signal 112, the non-linear error comparator 118 and the linear error detector 101 cause the feedback module 105 to reduce the feedback signal 112 to reduce the difference between the reference input signal 110 and the feedback signal 112. In addition, a negative decision output 123 is generated. Since the two input signals to the non-linear error comparator 118 and the linear error detector 101 are equivalent and due to inherent noise, and the decision output 123 can only stop in either the H or L state, the error input signal 114 is Even at zero, feedback correction of the non-linear feedback control loop continues continuously. As a result, the feedback signal 112 of the nonlinear feedback control loops 116 and 120 is not exactly equal to the reference input signal 110. Instead, the feedback signal 112 always oscillates randomly around the reference input signal 110 due to inherent broadband noise. In contrast, the error input signal 114 of the first order linear feedback control loop 100 is very small when the loop is locked. Since a finite error input signal 114 is required to generate the feedback signal 112, the two input signals to the linear error detector 101 are never exactly equivalent to a first order linear feedback control loop.

  If the closed loop gain is infinite, it is very difficult to understand the fact that the polarity of the closed loop gain is irrelevant. How big is it? The reason why the polarity of the closed loop gain is irrelevant is as follows. The feedback control loop becomes a non-linear feedback control loop 120 and 116 when the closed-loop gain is infinite and has a unique loop delay that encompasses both the propagation delay time and the latency delay time from all configurations of the non-linear feedback control loop. It is because of shaking. Knowing why the nonlinear feedback control loop sways, it is necessary to understand the acquisition operation of the nonlinear feedback control loops 116 and 120 as shown in FIG. In this figure, the horizontal axis indicates time, the first vertical axis indicated by the solid line indicates the error input signal 114 indicating the difference between the reference input signal 110 and the feedback signal 112, and the second vertical axis indicated by the dotted line. Indicates the binary decision output 123.

In initiating the acquisition process, the nonlinear feedback control loops 116 and 120 are not locked and the difference between the two input signals is large. For example, at the beginning of the acquisition process, the reference input signal 110 is much larger than the feedback signal 112 so that the feedback module 105 increases the feedback signal 112 to reduce the difference between the reference input 110 and the feedback input signal 112. Assume that the decision output 123 is positive. The difference between the two input signals is reduced and gradually the two input signals become identical at time t = T ₀ 552. Ideally, immediately after the time t = T ₀ 552, the correction to the feedback module 105 should be stopped immediately, however, the decision outputs 123 of the nonlinear feedback control loops 116 and 120 are in two digital states. The decision output 123 remains in the H state even after the time t = T ₀ 552 because the propagation delay time and waiting time delay time inherent to the loop configuration are limited to either H or L. And the feedback module 105 continues to increase the feedback signal 112 to make the difference between the reference signal 110 and the feedback signal 112 negative after time t = T ₀ 552. As a result, the decision output 123, but would quickly become negative, however, due to the inherent loop delay time, after a loop delay time exceeds the time t = T A _554, the decision output 123 is negative It made it possible, until after the total loop delay time t = T a _554, the loop continues always to act feedback module 105 in the wrong direction. At time t = T _A 554, the decision output 123 is finally switched negative in order to cause the feedback module 105 to reduce the feedback signal 112. The loop begins to correct errors that occur during the period between T ₀ 552 and T _A 554 at T = 0. Assuming the non-linear error comparator 118 and the amplifier with infinite gain 130 pump up and down the final error correction output 115 at the same rate, the loop corrects errors already made during the loop delay period. It required only to _T a 554 with the same degree of time for. After the error is corrected at a time around T ₁ 560 that is approximately twice T _A 554, the error input signal 114 is now near the decision threshold 164 of approximately zero, and the nonlinear error comparator 118 and linear error The detector 101 can make a new decision to switch its output polarity at any time, and the new decision can easily be affected by noise. Again, due to the loop delay time, the decision output 123 does not immediately change the instruction to correct the feedback signal 112, even after a new decision is made at t = T ₁ 560, instead the decision output 123 continues to decrease the feedback signal 112 until T _C 562 where the loop delay time eventually ends. As a result, during the loop delay period T ₁ 560 to T _C 562, the feedback signal 112 continues to decrease during t = T ₁ 560 to T _C 562 causing the loop to operate in the wrong direction for the feedback module 105. . The same operation is then repeated. As a result, the decision output 123 for the nonlinear feedback control loops 116 and 120 always swings between positive and negative, and the time to switch the polarity of the decision output 123 is determined by the nonlinear error comparator 118 and the linear error detector 101. The time for switching the polarity of the decision output 123 is determined by noise around the threshold value 164, and is different in each cycle of the shaking motion.

  The forward module 163 of the non-linear feedback control loops 116 and 120 typically provides a low pass filter that reduces the noisy digital decision output 123 from the non-linear error comparator 118 and a linear final error correction output 115 for the feedback module 105. And an amplifier with an infinite gain 130. As a result, the swaying decision output 123 causes the final error correction output signal 115 to be linearly strengthened or weakened. Increasing the final error correction output 115 changes the direction randomly determined by the noise around the decision threshold value 164 of the non-linear error comparator 118 and the linear error detector 101, and changes the final error correction output 115. Intensifying changes the direction at different times in every swing motion cycle so that the nonlinear feedback control loops 116 and 120 generate the feedback output signal 112 depending on the strength of the final error correction output 115. The feedback output signal 112 then rises and falls around the reference input signal 110 randomly, resulting in the desired spread spectrum clock output signal 109.

  The inherent loop delay time causes the non-linear error comparator 118 and the linear error detector 101 to make a mistake in strengthening or weakening the final error correction output 115 in the wrong direction during half the swing period. Thus, the other half of the swing period is needed to correct errors that occurred during the loop delay period. As a result, the total swinging cycle of the modulation signal due to the strength of the final error correction output 115 is approximately equal to two due to an incorrect decision output 123 during the loop delay time and a correct decision output 123 when the loop delay time is over. Contributed by part. If the polarity of the closed loop gain is reversed, the non-linear error comparator 118 and the linear error detector 101 will still make an error during half the swing motion period. However, during the loop delay period in which nonlinear error comparator 118 and detector 101 are generating errors, nonlinear error comparator 118 and linear error detector 101 actually move wrong final error correction output 115 in the right direction. The non-linear error comparator 118 or linear error detector 101 may begin making correction decisions that move the final error correction output 115 in the wrong direction. As a result, when the closed loop gain is infinite, the polarity of the closed loop gain is irrelevant. The non-linear feedback control loop produces a correct final error correction output 115 for half the time of the swing motion period and an incorrect final error correction output 115 for the remaining half time.

  The swing motion of the first order nonlinear feedback loops 116 and 120 is increased or decreased to adjust the feedback module 105, as shown in FIG. 8, and the feedback output signal 112 is adjusted by the swing motion of the loop. The acquisition operation of the first-order nonlinear feedback control loops 120 and 116 shown in FIG. 8 can be divided into two phases, an acquisition phase 542 and a vibration phase 564. Once the error input signal 114 is zero for the first time, the loop enters the oscillation phase 564. When the non-linear feedback control loops 120 and 116 are activated during the oscillation phase 564, the closed-loop gain polarity is not related to the non-linear feedback control loops 120 and 116 during the acquisition phase 542 even though the polarity of the closed-loop gain is irrelevant to the non-linear feedback control loops 120 and 116. It must still be correct. Otherwise, the non-linear feedback control loops 120 and 116 will never enter the oscillation phase 564 and will remain in either the H or L state forever.

  Non-linear feedback control loops 120 and 116 always require a reference input signal 110 to initiate oscillation, and loops 120 and 116 generate a conditioned feedback output signal 112 from the reference input signal 110. Without the reference input signal 110, the final error correction output 115 of the nonlinear feedback control loops 116 and 120 remains in the L state forever. When the reference signal input 110 arrives, the nonlinear feedback control loops 116 and 120 begin to oscillate and the oscillation period is determined by the total loop delay time, and the oscillation signals of the loops 116 and 120 are detected by the nonlinear error comparator 118 and the linear error detection. Around the decision threshold 164 of the device 101, the loops 116 and 120 are affected by internal broadband noise, so the start and end of each cycle of the modulation signal are determined by the noise and are different. In contrast, oscillation of the linear feedback control loop 100 occurs only for frequencies that produce exactly -1 closed loop gain when the linear feedback control loop 100 oscillates, and -1 closed loop over a wide bandwidth. Since it is not impossible to maintain the gain but is usually very difficult, no reference input signal 110 is required and the vibration is narrowband.

  The vibrations of the non-linear feedback control loops 116 and 120 are broadband in nature. This is because the increase or decrease in the final error correction output 115 changes the direction for randomly adjusting the feedback module 105 due to the inherent noise of the nonlinear feedback control loops 116 and 120. Increasing or decreasing the final error correction output 115 will change direction at different times for every cycle of the modulation signal. The bandwidth of the vibrations of the nonlinear feedback control loops 116 and 120 is determined by the bandwidth of the loop filter. Even though the vibration frequency of the non-linear feedback control loops 116 and 120 is determined by the total delay time around the loops 116 and 120, the vibration spread is mainly determined by the loop filter.

  The oscillating behavior of nonlinear feedback control loops 116 and 120 is also determined by the characteristics of decision threshold 164 of nonlinear error comparator 118 and linear error detector 101. If the decision threshold 164 between the non-linear error comparator 118 and the linear error detector 101 is unambiguous and accurate, the final error correction output 115 increases or decreases when the feedback signal 112 sets the decision threshold 164 to the error input signal 114. After being exceeded, the polarity of decision output 123 can only be changed by nonlinear error comparator 118 and linear error detector 101. This occurs during the previous loop delay period because the error input signal 114 must exceed the decision threshold 164 of the non-linear error comparator 118 and the linear error detector 101 to trigger a change in the decision output 123. As the increase or decrease during the previous loop delay period for correcting the feedback signal 112 by at least the same amount as the error, the final error correction output 115 must be increased or decreased by the same amount of time or more. As a result, the second increase / decrease period of the final error correction output 115 is very likely to last longer than the first increase / decrease, and the third increase / decrease period of the final error correction output 115 is also the second increase / decrease period. Is very likely to last longer. Similarly, every successive increase / decrease is likely to continue longer than the previous increase / decrease, so that the increase / decrease period of the final error correction output 115 is always highly likely to grow longer with each cycle.

  If the non-linear error comparator 118 and the linear error detector 101 are not accurate and have a large uncertainty window, and whenever the error input signal 114 falls within that uncertainty window, the nonlinear error comparator 118 and The decision output 123 from the linear error detector 101 can suddenly change polarity. The outputs of the nonlinear error comparator 118 and the linear error detector 101 can be H even if the error input signal 114 is still negative, and can be L even if the error input signal 114 is positive. Wrong decisions such as these are usually very short lived and the error input signal 114 is not good because the next decision output 123 from the nonlinear error comparator 118 and the linear error detector 101 is unlikely to be in error. When within the certain time frame, the outputs from the nonlinear error comparator 118 and the linear error detector 101 can quickly alternate between H and L. As a result, the non-linear error comparator 118 and the linear error detector 101 with uncertainty decision time frame can produce many hasty and noisy wrong decision outputs 123, and these wrong decisions Since each increase / decrease in the final error correction output 115 does not have to last longer than the previous increase / decrease causing the nonlinear error comparator 118 and the linear error detector 101 to switch the decision output 123, the final error correction output 115 is simply I can't grow. Whenever the error input signal 114 is within the uncertainty window, the non-linear error comparator 118 and the linear error detector 101 can switch the decision output 123. In contrast, for an accurate non-linear error comparator 118 and linear error detector 101 with unambiguous decisions, the error input signal 114 switches the decision output 123 to the non-linear error comparator 118 and the linear error detector 101. In order to do so, the decision threshold 164 must always be exceeded. As a result, it is very difficult for the nonlinear error comparator 118 and the linear error detector 101 with a large uncertainty window to grow the final error correction output 115 to adjust the feedback module 105.

  The spreading effect of the spread spectrum clock output 109 depends entirely on the modulation waveform of the final error correction output 115 that adjusts the feedback module 105. Ideally, the modulation waveform on the final error correction output 115 should be random in amplitude, frequency and phase. Only modulated signals with random amplitude, frequency and phase can produce the most spreadable loss due to the spread spectrum clock output. This ideal modulation waveform is currently very difficult to generate. Another best practice is to generate a modulated signal with random amplitude, frequency and phase on the deterministic modulated signal on the signal of the final error correction output 115. The effectiveness of this solution depends entirely on the ratio of the random signal amplitude to the deterministic signal amplitude. The least effective alternative is to use a constant deterministic modulation signal on the final error correction output 115, which is currently the most popular technology. Our goal of designing a complete spread spectrum clock generator with nonlinear feedback control loops 116 and 120 is to modulate the final error correction output 115 so that the modulation signal is as random as possible in amplitude, frequency and phase. It is quite clear that it is to control the waveform.

  The growing modulation signal on the final error correction output 115 easily generates full spread for the spread spectrum clock generator. This is because the growth of the modulation signal cannot last forever and at some time the growth process is reset or stopped. If the growth process is stopped, the modulation signal on the final error correction output 115 will then vary within several levels due to the inherent noise of the loop. Since the amplitude of the modulation signal on the final error correction output 115 can only vary within some range, clock spreading is not perfect. If the growth process of the modulation signal on the final error correction output 115 is reset, the new growth process can be restarted from a small amplitude so that the amplitude, frequency and phase of the modulation signal on the final error correction output 115 are fully Can be random. The growing modulated signal on the final error correction output 115 is reset regularly and randomly to adjust the complete modulation signal on the final error correction output 115 which adjusts the feedback module 105 to generate the complete broadband spectrum output signal 112. Can be generated.

  The growth of the modulation signal on the final error correction output 115 is determined by two factors. The first factor is the accuracy and precision of the decision threshold 164 as described above. The second factor is the slew rate of increase / decrease of the final error correction output 115. When the slew rate of increase or decrease of the final error correction output 115 is slow, the change that occurs in the feedback signal 112 during the loop delay can be smaller than the amount of random noise around the decision threshold 164. As a result, noise around decision threshold 164 simply cancels out the changes that occur during the loop delay period, making it difficult to grow the modulation signal on final error correction output 115. In order to generate a growth of the modulation signal on the final error correction output 115, it is necessary to increase the slew rate of the increase or decrease of the final error correction output 115, which causes the feedback signal 112 to generate noise around the decision threshold 164. Is changed by an amount greater than the uncertainty caused by. The ratio of the amount of noise around the decision threshold to the amount of change that occurs during the loop delay is the reset signal for the growth of the modulation signal on the final error correction output 115 to reset the modulation signal on the final error correction output 115. Determine whether it will last long enough to generate

  As described in detail in the PCT application "Arrival-time Locked Loop", for example, for a secondary feedback control loop that follows two variables, such as an arrival time locked loop or a PLL, The product of the loop gain and the feedback module determines how fast the feedback signal 112 can be guided or how fast the feedback signal 112 can be extinguished. As described above, the acquisition operation of the second-order nonlinear feedback control loop is slightly different from the first-order nonlinear feedback control loop, and the acquisition operation of the second-order nonlinear feedback control loop is described in the section on the nonlinear arrival time lock loop. Is done.

  For most applications, the linear feedback control loop 100 is everything we have ever needed. The linear feedback control loop 100 manages noisy input signals and helps reduce system fluctuations. The linear feedback control loop 100 can provide a clean signal from a noisy source. The linear feedback control loop 100 is applied throughout our daily lives.

  However, the concept of nonlinear feedback control loops 120 and 116 is relatively new and is just the opposite of linear feedback control loop 100. Nonlinear feedback control loops 120 and 116 are always unstable, which can provide us with an unpredictable feedback output signal 112 from a clean stable reference signal 110. Non-linear feedback control loops 116 and 120 have not helped us at all until now when spread spectrum technology has prevailed, and have helped to help electronic products that meet FCC regulation. Nonlinear feedback control loops 116 and 120 are the best way to generate a true spread spectrum clock signal with random modulation due to its unstable nature and the availability of inherent broadband random noise.

  A linear feedback control loop 116 shown in FIG. 5 using a non-linear error comparator 118 or a linear with an amplifier with infinite gain to produce a non-linear final error correction output 115 having the conversion characteristics shown in FIG. For the nonlinear feedback control loop 120 shown in FIG. 6 using the error detector 101, the derivative of the error input signal 114 is obtained by taking the derivative of the system output with respect to the input of the system to obtain the system gain. , By taking the derivative of the final error correction output 115 shown in FIG. 7, the gains of the non-linear feedback control loops 116 and 120 can be plotted, resulting in the results plotted in FIG. Since the nonlinear feedback control loops 116 and 120 can only produce positive loop gains within a very small range of +/− ε 201 of the error input signal 114, the nonlinear feedback control loops 116 and 120 are always of +/− ε 201. Within this small error range, a feedback signal 112 that follows the reference input signal 110 is generated. The size of ε201 is completely determined by the noise bandwidth of the system. The feedback signal 112 always fluctuates around the reference input signal 110 within a small error range of +/− ε201.

  Since the non-linear error comparator 118 can only produce an H or L state output regardless of the amount of the error input signal 114, the non-linear error comparator 118 is treated as a linear error detector with infinite gain and a non-linear error comparison. The output of the instrument 118 is named 123 to better represent its bipolar characteristics. As a result, the feedback module 105 is always pushed in one direction or pulled in the other direction, and the final error correction output 115 for the feedback module 105 is always increased or decreased, and the systems 116 and 120 are never stable. . Using a loop filter with a large time constant as the forward module 163 stabilizes the nonlinear feedback control loops 116 and 120 so that the noise bandwidth of the loop is small and the error range of +/− ε 201 is very small. In essence, despite the fact that the non-linear error comparator 118 and the linear error detector 101 prevent the feedback module 105 from being quickly corrected so that it actually operates like the linear feedback control loop 100 that generates the feedback signal 112. The nonlinear feedback control loops 116 and 120 are more unstable. Since the loop gains of the nonlinear feedback control loops 116 and 120 are infinite, the feedback signal 112 always follows the reference input signal 110 exactly as shown in Equation 2. This unique feature makes the nonlinear feedback control loops 116 and 120 very attractive and makes the nonlinear feedback control loops 116 and 120 much better than the linear feedback control loop 100. For example, a linear automatic frequency control circuit (AFC) never generates a feedback signal 112 at the same frequency as the reference input signal 110, but a non-linear frequency locked loop is as simple as a normal second order arrival time locked loop. To do it. Since the non-linear frequency lock loop is a first order loop that only needs to follow a single variable, the time to acquire and lock the reference signal 110 for the non-linear frequency lock loop is the second arrival time lock. Less than a loop.

  Since the signal has three independent variables, namely amplitude, frequency and phase, we can generate first order nonlinear feedback control loops 116 and 120 by controlling any one of the three independent variables. Alternatively, we can generate a second order nonlinear feedback control loop by controlling the arrival time of the signal. As a result, there are four different ways to generate a spread spectrum clock signal from a stable reference input clock signal 110 using a non-linear feedback control loop. Since the nonlinear feedback control loop can be assembled in two different ways depending on whether it uses the nonlinear error comparator 118 or the linear error detector 101, the use of the nonlinear feedback control loop allows the spread spectrum clock generator to A total of eight different designs are possible. Since the principle of the nonlinear error comparator 118 and the principle of the linear error detector 101 with an amplifier with infinite gain are the same, unless the design using the linear error detector 101 produces different results, we Since the structure of the error comparator 118 is simple, it is used for the design.

Linear Amplitude Lock Loop A block diagram of a non-linear amplitude lock loop 135 using a non-linear amplitude comparator 139 as a spread spectrum clock generator is shown in FIG. 10 as a first embodiment. The nonlinear amplitude lock loop 135 includes four component blocks, that is, a nonlinear amplitude comparator 139, a variable gain amplifier 137, a loop filter 106, and an amplitude limiting amplifier 131. Nonlinear amplitude comparator 139 compares the amplitude of feedback signal 112 having a constant reference voltage 125. When the amplitude of the feedback signal 112 is smaller than the constant reference voltage 125, the nonlinear amplitude comparator 139 transmits an H output to increase the gain for the variable gain amplifier 137, and the reference voltage 125 has a constant amplitude of the feedback signal 112. If greater, the nonlinear amplitude comparator 139 sends an L output to reduce the gain for the variable gain amplifier. Since it takes time for the amplitude of the feedback signal 112 at the input of the nonlinear amplitude comparator 139 to be updated after the decision output 123 is generated from the nonlinear amplitude comparator 139, the variable gain amplifier 137 is always overcorrected, Vibration at the decision output 123 from the nonlinear amplitude comparator 139 is inevitable. After passing through the loop filter 106, the digital decision output signal 123 from the non-linear amplitude comparator 139 becomes an analog final error correction output 115 that adjusts the variable gain amplifier 137. The gain of the variable gain amplifier 137 is always increased or decreased by the final error correction output 115, and the time for the variable gain amplifier 137 to change the vertical direction is around the decision threshold value 164 of the nonlinear amplitude comparator 139. Depends entirely on the noise in the loop. The decision threshold 164 of the non-linear amplitude comparator is determined by the reference power supply 125. Since a small noisy perturbation around the decision threshold 164 of the nonlinear amplitude comparator 139 can trigger the nonlinear amplitude comparator 139 to switch the variable gain amplifier 137 up and down, the nonlinear amplitude comparator 139 The direction is not changed at the same time in the vibration cycle. As a result, the final error correction voltage 115 for the variable gain amplifier 137 is constantly raised and lowered to generate the feedback output signal 112 linearly, and the moment when the amplitude of the feedback output signal 112 changes up and down is random. The amplitude limiting amplifier 131 can then be used to convert the amplitude variation of the feedback output signal 112 into a phase variation so that the output of the amplitude limiting amplifier 131 has the desired spread spectrum at the same frequency as the reference input signal 110. Although it can be the clock signal 109, the phase of the spread spectrum clock signal 109 is always canceled before and after the phase of the reference input signal 110. The time constant of the loop filter 106 determines how fast the phase of the spread spectrum clock output 109 can change and how much the phase of the spread spectrum clock 109 can be expanded.

  It is difficult to generate a complete spread spectrum clock output 109 from the nonlinear amplitude lock loop 135. This is because growing the modulation signal on the final error correction output 115 for adjusting the feedback module 137 of the nonlinear amplitude lock loop 135 is very limited. This is because the entire loop is only operated at the same frequency and the range of the phase modulation output is limited, so it is highly possible to use the amplitude limiting amplifier 131 to generate phase modulation by AM-PM conversion. Due to inefficiency. Since the propagation delay time and latency delay time around the non-linear amplitude lock loop 135 are relatively short, the modulation signal of the final error correction output 115 on the feedback module 137 typically has a very high frequency to produce a small phase spread. Have.

  There are two ways to increase the phase spread for the nonlinear amplitude lock loop 135. There are a method using a voltage comparator having hysteresis as the nonlinear amplitude comparator 139 and a method using a digital switch for sampling the output from the nonlinear amplitude comparator 139. By these methods, the decision output 123 from the non-linear amplitude comparator 139 can be updated at a constant rate, preferably at a rate of the reference input signal 110. Using a voltage comparator with hysteresis as the amplitude comparator 139 prevents the output 123 from changing very quickly, so the final error correction output 115 is error-corrected before a range of decision output 123 switching. The input signal 114 is forcibly advanced. The method of using a digital switch to sample the output from the nonlinear amplitude comparator 139 is more effective in generating longer loop delay times because the decision output 123 can only be updated at a constant rate. Once the new decision output 123 is generated, it continues to remain until the nonlinear amplitude comparator 139 of the nonlinear amplitude lock loop 135 produces a different result in the next comparison cycle. Both solutions greatly increase the loop delay time of the non-linear amplitude lock loop 135 to generate more spread for the spread spectrum clock output 109 and modulate the modulated signal on the final error correction output 115 to the feedback module 137. Slow down. Since the entire non-linear amplitude lock loop 135 is operated at the same frequency, it is very simple to sample the output from the non-linear amplitude comparator 139.

  The non-linear amplitude lock loop 135 shown in FIG. 10 is similar to a conventional AGC circuit that generates an output signal with stable amplitude from an input signal having large amplitude variations. The only difference between the AGC circuit shown in FIG. 10 and the spread spectrum clock generator 135 is the reference input signal 110 and the loop filter 106. In the AGC circuit, the amplitude of the reference input signal 110 fluctuates so that the amplitude of the feedback output signal 112 does not fluctuate, and the time constant of the loop filter 106 is usually appropriate so as to largely follow the nature of the amplitude fluctuation of the reference input signal 110. is there. In contrast, in the spread spectrum clock generator 135, the amplitude of the reference input signal 110 is very stable and the time constant of the loop filter 106 is usually small so that the amplitude of the feedback output signal 112 can vary rapidly and randomly.

  The conversion characteristic of the variable gain amplifier 137 is usually linear so that the gain of the amplifier 137 is controlled linearly by the linear increase / decrease of the final error correction output 115. Using the linear variable gain amplifier 137, the non-linear amplitude lock loop 135 can only generate a random phase that is spread for the spread spectrum clock output signal 109. Over time, frequency spreading always provides much greater spreading than phase spreading, since the phase of the signal becomes equal to the integration of the signal's frequency. As a result, widening the spread spectrum clock output signal 109 generated from the non-linear amplitude locked loop 135 using the linear variable gain amplifier 137 is very small compared to a system that generates frequency spread.

  In order to improve the spread of the spread spectrum clock 109 generated from the nonlinear amplitude lock loop 135, the conversion characteristic of the variable gain amplifier 137 needs to be improved. When the conversion characteristic of the variable gain amplifier 137 is a square function of the final error correction output 115 instead of the linear function, the increase or decrease of the final error correction output 115 is a variable gain amplifier having an amplitude that changes based on the square function. The feedback output 112 from 137 is generated. Since the accumulated phase change of the signal with a linear frequency increase / decrease exceeding the time period is proportional to the square function of time, the variable gain amplifier 137 with the square function conversion characteristic can efficiently perform the nonlinear amplitude lock loop from phase spreading. Spread spectrum clock output 109 is spread to frequency spread, greatly improving the efficiency of the spread.

Nonlinear Arrival Time Lock Loop FIG. 11 shows a block diagram of a spread spectrum clock generator 150 using a basic nonlinear arrival time lock loop with a nonlinear arrival time comparator as a second implementation, and FIG. 12 shows a third implementation as FIG. 7 shows a block diagram of a spread spectrum clock generator 152 using a basic nonlinear arrival time lock loop with a linear arrival time detector and an amplifier with infinite gain. The basic nonlinear arrival time locked loop 150 is formed from three functional blocks: a nonlinear arrival time comparator (148, 169 and 189), a loop filter 106, and a VCO 108. It is made up of functional blocks: linear arrival time detectors (180, 182, 155 and 154), loop filter 106, amplifier 130 with infinite gain 130, and VCO 108. Both basic nonlinear arrival time lock loops 150 and 152 are rarely used for spread spectrum clock generation. This is because the frequency of the spread spectrum clock output signal 109 must always be equal to the frequency of the reference input signal 110. However, the frequency of the spread spectrum clock output signal 109 is usually required to be adjustable in many spread spectrum clock applications. To meet this requirement, a divider 111 divided by N can be used, and a low frequency feedback comparison signal 112 that is compared with the reference input signal 110 is generated, so that the spread spectrum clock output signal F _OUT The frequency 109 is obtained by multiplying N by the frequency of the reference input signal 110, and the frequency of the spread spectrum clock output signal 109 is easily changed. Therefore, as shown in FIGS. 13 and 14, typical nonlinear arrival time lock loops 151 and 153 with a frequency divider are more useful as spread spectrum clock generators that generate the spread spectrum clock output signal 109. The use of divider 111 divided by N can add more propagation delay and mechanical delay to the feedback signal path so that the frequency of the modulated signal on final error correction output 115 for the die VCO is low and the spread spectrum Generate a larger spread for the clock output 109.

  As a first supplemental embodiment to the second embodiment, FIG. 15 shows a typical non-linear arrival time comparison comprised of four components: PFD 132, complementary PFD 134, polarity selection circuit 142, and decision output latch 156. A device 148 is shown. The principle of the non-linear arrival time comparator 148 is to use a PFD 132 and a complementary PFD 134 that detect the arrival of each input signal and generate two positive and negative arrival signals for the polarity selection circuit 142 to select. Yes, a positive arrival signal is generated from the PFD 132 induced upon arrival of the reference input signal 110, and a negative arrival signal is generated from the complementary PFD 134 induced upon arrival of the feedback signal 112 from the VCO. The polarity selection circuit 142 then selects the first arrival signal as the final polarity output signal 144. Once the final polarity output signal 144 is selected and after both signals arrive, the final polarity output signal 144 is stored in the output latch 156 to become the decision output 123 and the decision output 123 is stored in the next comparison cycle. It remains the same until it gives a different result. The arrival time comparison cycle begins when the first arrival signal arrives and ends when the later arrival signal arrives. After the arrival time comparison cycle is completed, the PFD 132 and the complementary PFD 134 are reset. The presence of the reset signal 128 indicates the end of the arrival time comparison cycle.

  Since the final polarity output signal 144 always lasts longer than the reset output signal 128, the use of the reset output signal 128 to trigger the decision output latch 156 can be safe, error free and accurate. When a completed comparison cycle occurs and the latest arrival signal arrives, the reset output signal 128 is generated and the final polarity output 144 is determined. The reset output signal 128 can then time the final polarity decision output 144 from the decision output latch 156 without error without error. Delay buffer 158 provides the necessary delay to the clock signal to decision output latch 156 to ensure that the safe trigger condition for decision output latch 156 has not been violated. Delay buffer 158 can ensure that the rising edge of the clock input of decision flip-flop 159 always occurs between the end of final polarity signal 144 and the beginning of reset signal 128.

  The two PFDs 132, 134 in the design of FIG. 15 can be merged together to become a mixed PFD 133 shown in FIG. 16 as a second supplemental embodiment of the second embodiment to save some hardware. it can. Despite the fact that PFD 132 and complementary PFD 134 of FIG. 15 each generate two arrival output signals to generate four arrival output signals, only two of these four arrival output signals are selected. Since it is not required for the polarity selection circuit 142, hardware savings are possible. The other two incoming output signals are simply redundant and are removed. Since PFD 132 and complementary PFD 134 are triggered by the same input signal, they can be easily merged without affecting their operation.

  The conversion characteristics of the final error correction output 115 of the non-linear arrival time locked loop 150 with the non-linear arrival time comparator 169 are as shown in FIG. 7 and have an uncertainty of +/− (propagation delay time of a single logic gate). Having a decision threshold 164 located at the zero arrival time difference point with the sex time frame. The uncertainty window around decision threshold 164 is caused by a feedback device between AND logic gate 136 and OR logic gate 138 of polarity selection circuit 142.

  There are two possible feedback devices between the AND logic gate 136 and the OR logic gate 138 of the polarity selection circuit 142. First, when the final polarity output 144 is exercised by the first arrival signal, the latest arrival signal is prevented from switching to the final polarity output 144. If the positive arrival signal from PFD 132 arrives first, the output of AND 136 will be H, forcing OR 138 to H, and if the negative arrival signal from complementary PFD 134 arrives first, the output of the logic gate of OR 138 Becomes L, which forces AND136 to be L. As a result, the first arrival signal cannot change the final polarity output 144 once the first arrival signal determines the state for the output of the AND 136 and OR 138 logic gates. The first arrival signal determines the polarity of the final polarity output signal 144 of the polarity selection circuit 142, and the final polarity output signal 144 does not change until the flip-flop is reset at the end of the arrival time comparison cycle. Before the flip-flop is reset, final polarity output 144 is also stored in decision output latch 156 as decision output 123, and decision output 123 remains in the same state until a new comparison cycle produces a different final polarity output 144. Remains. Second, the feedback device provides a final polarity output signal 144 that lasts as long as the arrival output signal from the PFD flip-flop so that the duration of the final polarity output signal 144 is always the actual arrival time difference between the two input signals. Longer than. Since the arrival time difference between two input signals can be from zero to infinity, the final polarity output signal 144 has a period that is exactly equal to the arrival time difference between the two input signals, and between the two input signals It is very difficult to measure the final polarity output signal 144 when the arrival time difference is close to zero. Fortunately, the arrival output signal from the PFD flip-flop always has a delay time equal to the sum of the propagation delay time of the flip-flop from the reset input and the propagation delay of the AND gate 126, rather than the arrival time difference between the two input signals. Since it lasts long, the arrival output signal of the flip-flop is guaranteed to have a minimum duration to be in the ideal form used as the final polarity output signal 144.

  The feedback mechanism of the polarity selection circuit 142 is complementary to the first arrival signal, ie, the positive arrival output from the normal flip-flop 122 triggered by the arrival of the reference signal 110 or the arrival of the feedback signal from the VCO 112. One of the negative arrival outputs from the flip-flop 119 is selected as the final polarity output signal 144. The final polarity output signal 144 has a minimum width equal to the sum of the flip-flop propagation delay from the reset input and the AND 126 gate propagation delay. Thus, with this minimum width, final polarity determination output signal 144 is safer to be clocked out by reset signal 128 from determination output latch 156.

  Nevertheless, the feedback mechanism of the polarity selection circuit 142 operates around the decision threshold 164 for the non-linear arrival time comparator 169 with a +/− uncertainty window 160 (propagation delay of a single logic gate). Time). This is because the outputs from the AND 136 and OR 138 logic gates are fully ready to block the latest arrival signal when the arrival time difference between the two input signals is within the propagation delay of a single logic gate. This is because the final polarity output 144 of the polarity selection circuit 142 can fluctuate over the entire period of the final polarity output signal 144. During this uncertain oscillation period, there is no longer a safe trigger condition for decision output latch 156, especially when the arrival time difference approaches decision threshold 164, the output of decision output latch 156 is random. Become. The randomness of decisions around the decision threshold 164 can produce many abrupt and inaccurate final polarity decision outputs 123.

  The polarity selection circuit 142 shown in FIG. 15 has an additional OR logic gate 140. This OR 140 logic gate can reduce the range of uncertainty of polarity determination in half because the final polarity output 144 always remains high as long as the reference input signal 110 arrives early. If the reference input signal 110 arrives early and the arrival time difference between the two input signals is less than the propagation delay time of a single logic gate, the outputs from the AND 136 and OR 138 logic gates will still wobble and nevertheless Since the final polarity output 144 remains H as long as the input to any one OR logic gate 140 is H, the final polarity output 144 at the OR 140 gate always remains H. As a result, as shown in FIG. 15, the decision threshold 164 of the polarity selection circuit 142 is shifted to the negative side by an amount half the propagation delay time of a single logic gate, and the decision uncertainty is 0 To-(propagation delay time of a single logic gate) is limited to the range of arrival time difference between 160.

  When the error input signal 114 is within the uncertainty window around the decision threshold 164 of the nonlinear error comparator 118 and the linear error detector 101, the randomness of the decision output 123 is determined by the spread spectrum clock generation. Is the source. Nevertheless, when the error input signal 114 is within the uncertainty time frame of the decision of the nonlinear error comparator 118 and the linear error detector 101, the randomness of the decision output 123 is determined by the polarity decision output 123 and It only affects when switching the non-linear error comparator 118, and the linear error detector 101 must not generate an incorrect polarity determination output 123 that affects the final error correction output 115. However, in the design of the non-linear arrival time comparator 169 shown in FIG. 16, the polarity determination output 123 is H when the error input signal 114 is negative and L, and the polarity determination when the error input signal 114 is positive. The output 123 is L. In the design of the non-linear arrival time comparator 148 shown in FIG. 15, when the reference input signal 110 arrives early, it is guaranteed that the polarity determination output 123 is in the correct H state, while the reference signal 110 is When coming after the feedback signal 112, the polarity determination output 123 can be either H or L. In both cases, the non-linear arrival time comparators 148 and 169 may generate an erroneous decision output 123 that affects the final error correction output 115.

  In order to solve the problem of accuracy of the decision output 123 from the non-linear arrival time comparator of the design shown in FIGS. It is shown in FIG. This new non-linear arrival time comparator is made up of three component modules: a mixed PFD 133, a polarity selection module 142 and an output latch 156. In this new design, it is driven by a polarity selection circuit 142 with additional AND 141 and OR 140 gates to produce an accurate final polarity output 144 for polarity output latches 181 and 183. The final polarity output 144 of the OR logic gate 140 remains in the default H state until the feedback signal from the VCO 112 arrives first. Similarly, the final polarity output 144 of the AND logic gate 141 remains in the default L state until the reference input signal 110 arrives first. These two additional logic gates ensure that the polarity of the decision output signal 123 is always accurate, even if the final polarity output 144 of the polarity selection circuit 142 is still swaying, the final error correction output 115. Does not generate an incorrect decision output 123 that affects it.

  If the feedback signal 112 from the VCO is an inductive signal and the arrival time difference between the two input signals to the nonlinear arrival time comparator 189 is less than the propagation delay of a single logic gate, the final polarity output from the AND logic gate 141 Since 144 remains in the default L state, it is guaranteed that output latch 181 will not produce an output, and final polarity output 144 from OR logic gate 140 will swing between H and L. Since the feedback signal 112 from the VCO is an inductive signal, the correct final polarity output 144 from the OR logic gate 140 must be L to enable the sinking charge pump 129. Fortunately, if the final polarity output 144 from the OR logic gate 140 is incorrectly clocked out due to the uncertain decision uncertainty, the decision output latch 183 generates the wrong H output instead of the correct L output. However, such an error does not generate an error for decision output 123 because only the L output from polarity latch output 183 makes sinking charge pump output 129 available.

  When the reference input signal 110 is derived and the arrival time difference between the two input signals to the non-linear arrival time comparator 189 is less than the propagation delay of a single logic gate, it is guaranteed that the output latch 183 will not produce an output. As such, the final polarity output 144 from the OR logic gate 140 remains in the default H state, and the final polarity output 144 from the AND logic gate 141 swings between H and L. Since the reference input signal 110 is an inductive signal, the correct final polarity output 144 from the AND logic gate 141 should be H enabling the sourcing charge pump 127. Fortunately, even if the final polarity output 144 from the AND logic gate 141 is erroneously clocked out due to uncertainty in the decision oscillation, the decision output latch 181 generates the wrong L output, even if the polarity output latch Since only the H output from 181 can enable sourcing charge pump output 127, this error still does not generate an error in decision output 123.

  As a result, if the error input signal 114 is rotated from the positive side of the decision threshold 164 to the negative side, the non-linear arrival until the error input signal 114 moves beyond the decision threshold 164 to the negative side. The polarity of decision output 123 of time comparator 189 is guaranteed to remain in the H state. After the error input signal 114 exceeds the decision threshold 164, the decision output 123 can then randomly change to the L state at any time. Similarly, if the error input signal 114 is rotated from the negative side of the decision threshold 164 to the positive side, the nonlinear arrival time until the error input signal 114 moves beyond the decision threshold 164 to the positive side. The polarity of decision output 123 of comparator 189 is guaranteed to remain in the L state. After the error input signal 114 exceeds the decision threshold 164, the polarity of the decision output 123 can then randomly change to the H state at any time. In conclusion, when the error input signal 114 is rotated beyond the decision threshold 164, it is never after the error input signal 114 exceeds the decision threshold 164, but before the non-linear arrival time comparator 189. Switching of the decision output 123 always occurs. In contrast, because of the non-linear arrival time comparators 148 and 169 shown in FIGS. 15 and 16, switching of the decision output 123 can occur whenever the error input signal 114 is within the uncertainty window. . Accordingly, the non-linear arrival time comparator 189 shown in FIG. 18 is an accurate and precise arrival time comparator without decision ambiguity, and is the most desirable design for the non-linear arrival time comparator.

  This error affects the final error correction output 115 when the final polarity output 144 from the polarity selection circuit 142 oscillates and causes the nonlinear arrival time comparator 189 to generate an incorrect output in the polarity output latch 181 or 183. The non-linear arrival time comparator 189 is also unable to generate the correct decision output 123 that affects the final error correction output 115, even though it is benign so as not to produce the wrong decision output 123. In other words, when an incorrect decision output is generated from decision output latch 181 or 183, nonlinear arrival time comparator 189 is literally disabled. Thus, since the probability that the polarity output latch 181 or 183 will produce an incorrect output while the final polarity output 144 is oscillating is 50%, the error input signal 114 is within the decision uncertainty window. , The non-linear arrival time comparator 189 is half-functional. The effective size of the dead zone of the non-linear arrival time comparator 189 is equal to half the decision uncertainty time frame and equal to +/− (propagation delay time of a single logic gate) 160.

The acquisition process of the second order nonlinear arrival time lock loop 150 with the nonlinear arrival time comparator 189 is shown in FIG. Since the non-linear arrival time lock loop 150 is a second order loop, there are two variables to be tracked: frequency and arrival time. The acquisition operation of the second arrival time lock loop is represented only in a three-dimensional plot with two vertical axes, one indicating frequency acquisition and one indicating arrival time acquisition. The acquisition process of the non-linear arrival time lock loop 150 can be divided into two phases: acquisition phase 542 and vibration phase 564. The acquisition phase 542 is referred to as the cycle slip phase 542 because many cycle slips occur during this period for the arrival time lock loop. Here, it is assumed that the initial frequency of the feedback signal from the VCO 112 is lower than the frequency of the reference signal 110 at the start of the acquisition process so that the initial frequency difference f ₀ 530 is positive. The non-linear arrival time comparator 189 dispatches a positive decision output 123 most of the initial time to speed up the frequency of the VCO 108 which reduces the frequency difference. The arrival time correction output for the VCO during cycle slip phase 542 is approximately in the H state. This is because the reference signal 110 is always executed faster and arrives earlier so that the decision output 123 of the non-linear arrival time comparator 189 is almost H. Since the frequency difference between the two input signals is reduced during the cycle slip phase 542, cycle slips only occur occasionally, and when a cycle slip occurs, the non-linear arrival time comparator 189 is only short. The polarity of the decision output 123 can be repelled on the negative side. Since the frequency of the reference signal 110 is always faster than the frequency of the feedback signal from the VCO 112 during the cycle slip phase 542, the duration during which the polarity output 123 is negative during the cycle slip phase is always short, so the cycle slip is Does not affect acquisition.

The acquisition process enters the oscillation phase 564 when the frequency of the feedback signal from the VCO 112 eventually becomes the same as the frequency of the reference signal 110 that occurs for the first time at time = T ₀ 552. In this phase, the arrival time difference polarity and frequency difference always oscillate between positive and negative. In the beginning of the acquisition process, when the polarity of the frequency difference between the two input signals is changed for the first time at t = T ₀ 552, the arrival time difference between the two input signals is from 0 to the period of the feedback signal from the VCO 112 Can be anywhere until.

Assuming that the arrival time difference between the two input signals is positive when the frequency difference is zero for the first time at t = T ₀ 552, the arrival time difference is still positive T _ε 532, so a nonlinear arrival time comparator 189 continues to generate an H output to speed up the feedback signal from the VCO 112. Here, the feedback signal from the VCO 112 is to modify the arrival time difference of _T ε 532, T ε 532 is a completely random, it may be anywhere between the period of the feedback signal from 0 and VCO 112. As a result, the frequency difference becomes negative after the current t = 0 552 and the feedback signal from the VCO 112 executes faster than the current reference input signal 110. The final error correction output 115 for the VCO continues to increase the frequency of the feedback signal from the VCO 112 until the feedback signal from the VCO 112 arrives simultaneously with the reference signal 110 at T _A 554. After T _A 554, the frequency of the VCO continues to increase in speed due to the total loop delay time. When the total loop delay time ends, the arrival time difference at the input of the nonlinear arrival time comparator 189 finally exceeds the decision threshold value 164 at t = T _B 556, and the nonlinear arrival time comparator 189 Until the trigger to change polarity is pulled, the frequency of the signal from the VCO 112 will still be increased in speed. Only up to this instant, determined by noise around the decision threshold 164 of the non-linear arrival time comparator 189, the non-linear arrival time comparator 189 provides feedback from the VCO 112 by reducing the final error correction 115 to the current VCO. Start slowing the signal frequency. Thus, before the nonlinear arrival time comparator 189 begins to slow down the frequency of the feedback signal from the VCO 112, the arrival time difference between the two input signals is overcorrected for at least the amount of total loop delay time, and the nonlinear arrival time comparison The time at which the unit 189 begins to increase or decrease in the opposite direction is completely determined by the noise around the decision threshold of the non-linear arrival time comparator 189.

Since the frequency of the VCO is speeded up from t = T ₀ 552 to t = T _B 556 to correct the arrival time difference for T _ε 532, the feedback signal from the VCO 112 at t = T _B 556 is the reference signal. When much higher than the 110 frequency, the feedback signal from the VCO 112 arrives earlier than the reference signal 110. As a result, the arrival time difference remains at the negative side at present, and the polarity of the decision output 123 of the nonlinear arrival time comparator 189 is also switched to the negative side. Although the frequency difference is reduced between t = T _B 556 and t = T ₁ 560 when the frequency difference finally becomes zero again, the arrival time difference between the two input signals actually increases. Continue to become more negative. This is because during the entire period between t = T _B 556 and t = T ₁ 560, the frequency of the feedback signal from the VCO 112 always runs faster than the reference signal 110, so the arrival time difference between the two input signals is This is because it still grows only negative during this period, and the arrival time difference reaches its maximum at t = T ₁ 560.

At t = T ₁ 560, the frequency difference between the two input signals eventually becomes zero again, but the arrival time difference is now negative. Before the arrival time comparator 189 begins to decrease the final error correction output 115 at 556, the arrival time difference is overcorrected so that the arrival time difference at the second time frequency difference is zero at t = T ₁ 560, It is very likely that, for the first time, when the frequency difference becomes zero at t = T ₀ 552, it is much larger than the arrival time difference T _ε 532.

From t = T ₀ 552 to t = T ₁ 560, the frequency difference between the two input signals starting from zero and ending at zero again while the arrival time difference starts with a positive error and ends with a negative error is the first oscillation cycle. Form.

  The same process is then repeated, and each time the frequency difference is zero again, the polarity of the arrival time difference goes back and forth between positive and negative, and the amount of arrival time difference at the beginning of each vibration cycle can increase slightly. Very expensive. The increase in arrival time difference at the new frequency synchronization point at the beginning of each oscillation cycle is equal to the sum of the arrival time changes that occur during the total delay time period, and random arrival times due to noise around decision threshold 164 An error is triggered. The beginning of each new oscillation cycle that occurs if the total loop delay time is long enough to cause a large arrival time change (ie, much larger than the random arrival time error caused by noise around decision threshold 164) The arrival time difference continues to increase. If the arrival time change during the loop delay period is less than the random arrival time error caused by noise around the decision threshold 164, the initial arrival time difference of the new oscillation cycle may not increase, but instead the simple Vibrate. Thus, depending on how much the arrival time of the feedback signal 112 from the VCO can be changed and how long the loop delay is, eventually the arrival time difference of each oscillation cycle is stable to oscillate by a certain amount. Or a complete cycle of the feedback signal 112 is skipped and the arrival time difference becomes longer as cycle slip occurs. Once a cycle slip has occurred, the arrival time difference at the beginning of a new vibration cycle becomes very small and the entire development process of the arrival time difference repeats itself. When a cycle slip occurs from the VCO 112 to the feedback signal, every cycle of the modulation signal on the final error correction output 115 is very different because the arrival time difference of each oscillation cycle here can vary from zero to a specific level. . Thus, the generation of cycle clips makes the nonlinear arrival time locked loop 150 with the nonlinear arrival time comparator 189 a complete spread spectrum clock generator. This is because every cycle of the modulation of the clock signal starts with a random amplitude, frequency and phase and ends with another random amplitude, frequency and phase.

  Whether the non-linear arrival time lock loop 150 becomes a full spread spectrum clock generator is the ability to grow the arrival time difference amount whenever the frequency difference becomes zero during the oscillation phase 564 until a cycle slip occurs. Depends entirely on. As previously noted, the ability to grow the arrival time difference amount is entirely dependent on the total loop delay time and the decision threshold 164 and VCO 112. If the decision threshold of the non-linear arrival time comparator is unambiguous and accurate, the non-linear arrival time loop 150 can easily develop the amount of arrival time difference. It is difficult to grow the arrival time difference because erroneous decisions due to decision ambiguity can cancel each other. The total loop delay time allows the nonlinear arrival time lock loop 150 to overcorrect the arrival time difference before the nonlinear arrival time comparators (148, 169 and 189) change the direction of increase or decrease of the final error correction output 115. As a result, a long loop delay time can guarantee the growth of the arrival time difference. Even if non-linear arrival time comparators (148 and 169) with large decision uncertainty windows are used, as long as the total loop delay time can produce more arrival time differences than the decision uncertainty window The growth of the arrival time difference can still be maintained. The slew rate of the VCO determines the amount of frequency change, or more precisely the amount of arrival time change, and the feedback signal 112 is generated during a fixed delay period. If the arrival time change during the loop delay period is less than the noise uncertainty range, the arrival time difference growth process is not productive, so the arrival time difference only fluctuates around a certain value at the beginning of each oscillation cycle. is there.

  Since the response time of the non-linear arrival time comparators (148, 169 and 189) is fast and the decision output 123 is generated as soon as the later arrival signal arrives, the non-linear arrival time locked loop 150 is essentially two flip-flops. It has a short propagation delay time which is almost equal to the propagation delay of the three logic gates. The latency delay time of the non-linear arrival time lock loop 150 is mainly determined by the period of the later arrival time comparison signal, and the latency delay time is usually the dominant factor for the total loop delay time. As a result, the frequency spread of the spread spectrum clock output signal 109 from the basic non-linear arrival time lock loop is usually small, and the frequency of the arrival time comparison signal is usually high, so a cycle slip is generated for the feedback signal 112 from the VCO. Is difficult. Thus, the representative non-linear arrival time lock loop 151 is a better design for generating a complete spread spectrum clock output 109 due to the long latency delay time through the divider 111.

  The non-linear arrival time comparator 189 does not generate a new decision output 123 early when the error input 114 is rotated beyond the decision threshold 164, so if there is sufficient time, the VCO In order to easily generate a cycle slip in the feedback signal 112 from, the final error correction output 115 can be greatly increased or decreased. The long loop delay time for the non-linear arrival time lock loop 151 can always effectively force the loop to generate a cycle slip in the feedback signal 112.

  The simplest way to add more loop delay to the non-linear arrival time lock loop 150 is to add a divider 111 to the feedback path. The simplest divider used is an asynchronous divide-by-two divider using a self-toggling flip-flop. Unfortunately, any additional divide-by-two divider we use also doubles the latency delay time, so a simple divide-by-two divider can be used to accurately obtain the desired delay time. Is very difficult. Thus, a programmable divider is a better solution. As a result, the programmable divider 111 in the feedback path of the non-linear arrival time lock loop 151 can be a programmable frequency spread controller for the spread spectrum clock generator. We can also adjust the amount of frequency spreading by adjusting the amount of frequency division, and of course we will adjust the frequency of the reference signal 110 so that the frequency of the arrival time comparison signal remains the same as when the frequency spreading is adjusted. It is necessary to use a similar programmable divider for the pass. Thus, an automatic frequency spread control system can be easily implemented.

  An alternative to adding more loop delay time to the non-linear arrival time lock loop 150 to increase the frequency spread for the spread spectrum clock output is to use a digital filter that delays the generation of new decisions. For example, we can store each decision output 123 from the non-linear arrival time comparator 189 in turn in a 1N bit shift register and use an N bit adder to sum all the stored decisions. We then make a final decision based on the total results. For example, if the current final decision is H and the total result is 0, then the final decision is changed to L, only if the current final decision is L and the total result is N The final decision is changed to H. In this way, a new decision output that delays is made a decision and changes from H to L or from L to H can only occur after an N arrival time comparison cycle has occurred. We can adjust the number of shift registers or decision thresholds until the desired total loop delay time is generated. This technique allows us to use high frequency comparison clocks for the non-linear arrival time comparators (148, 169 and 189) and control the frequency spreading of the clock signal in smaller steps.

  The four linear arrival time detectors shown in FIGS. 20-23 are used with an amplifier having an infinite gain 130 as a non-linear arrival time lock loop that becomes the spread spectrum clock generator 152. The linear arrival time detector can generate an error output signal 117 having a polarity determined by the first arriving signal, and the error output signal 117 is between a period determined by the arrival time difference between the two input signals. Since it becomes available, the error output signal 117 of the linear error arrival time detector is charged up when the reference signal 110 arrives and is discharged when the feedback signal from the VCO 112 arrives first. ) Since the error output signal 117 is only activated for a very short time and the stray capacitance of the error output node 117 holds the error output voltage 117 at the current voltage until the next comparison cycle, the charge increase / decrease output driver Sufficient slew rate must be provided to ensure that 117 rises rapidly. The leakage current of the stray capacitance must be controlled so that the leakage current does not discharge the error output voltage 117 when the charge increase / decrease output driver is not available. A larger capacitor may be required to hold the error output signal 117, but a larger capacitor may slow down the charge increase and decrease slew rates and create a dead zone. Using an amplifier with infinite gain 130, the decision output 123 of the output of amplifier 130, like the final error correction output 115, can only stay in either the H or L state, and the loop is nonlinear arrival time locked. A loop 152 is obtained. The action and acquisition operation of the non-linear arrival time lock loop 152 using linear arrival time detectors 180, 182, 154 and 155 and the amplifier with infinite gain 130 uses non-linear arrival time comparators 148, 169 and 189. It is exactly the same as the non-linear arrival time lock loop 150.

  The arrival time detector 180 in FIG. 20 is made up of three functional blocks: a mixed PFD 133, a polarity selection circuit 142, and a double-ended charge pump output 149. The mixed PFD 133 provides two arrival signals to the polarity selection circuit 142 that selects as the final polarity output 144 to enable the charge pump 149. Using a single logic gate of AND 141 and OR 140 as polarity selection circuit 142, the duration of the final polarity output signal 144 is necessarily always equal to the arrival time difference between the two input signals. Since the arrival time difference between the two input signals can be anywhere from 0 to infinity, the duration of the final polarity output 144 can also be zero, and the arrival time difference between the two input signals can reduce the input threshold of the double-ended charge pump output 149. The double-ended charge pump output 149 is disabled until longer than the time required to get over, and a dead zone is created for the error output 117 of the linear arrival time detector 180.

  The dead zone of the linear arrival time detector 182 shown in FIG. 21 is completely eliminated by adding a feedback mechanism consisting of AND 136 and OR 138 logic gates to the polarity selection circuit 142. These two logic gates produce a final polarity signal 144 having a minimum duration equal to the sum of the propagation delay of the flip-flop from the reset input and the propagation delay of the AND logic gate 126. This minimum duration is usually long enough to overcome the input threshold of the charge pump output 149 so that there is no longer a dead zone. As soon as the error input signal 114 exceeds the decision threshold 164 without a dead zone, the error output 117 from the arrival time detector 182 may be available. Thus, without a dead zone, the linear arrival time detector 182 is more accurate and is the best of all designs of linear arrival time detectors and non-linear arrival time comparators.

Although the dead zone can increase the latency delay time of the nonlinear arrival time comparator and the linear arrival time detector, no output is generated during this period, so the dead zone is a linear error detector and nonlinear error comparator. This is an undesired state. The accumulation of phase shift is a linear function of time when the frequency is constant, since the amount of phase shift the signal has advanced is equal to the integral of the frequency over that period of time, and for example, tuning to increase or decrease If the frequency itself is a linear function of time, such as an output signal from a VCO having a voltage, the accumulation of the phase shift is a square function of time. As a result, when the slewing of the final error correction output 115 attempts to cause the error input signal 114 to exceed the decision threshold 164, two before the error input signal 114 exceeds the decision threshold 164, two phase error between the input signal is accumulated at a rate of T ^2. Since no output is generated from the nonlinear error comparator after the error input signal 114 exceeds the decision threshold 164 and during the dead zone, the phase error is accumulated only at a slow rate of T, and the linear error detector. Increases or decreases the frequency of the feedback signal from the VCO 112. Thus, the phase spreading rate is slowed down before the direction of frequency rotation is changed. Without the presence of dead zones, phase errors always continue to accumulate at a similar faster T ² rate, so that linear arrival time detectors and non-linear arrival time comparators without dead zones are better and more uniform Can be generated. Therefore, the presence of the dead zone can deteriorate the smoothness of the output density of the clock spectrum, so that the clock energy has a peak and the loss of diffusion can be reduced.

  The design of the linear arrival time detector 154 shown in FIG. 22 is substantially the same as the design shown in FIG. 20 except that a single-ended charge pump output driver 146 is used in place of the double-ended charge pump 149. The design of the linear arrival time detector 155 shown in FIG. 23 is almost the same as the design shown in FIG. 21 except that a single-ended charge pump 146 output driver is used instead of a double-ended charge pump output 149. The use of single-ended charge pump 146 is somewhat different and does not affect the operation of the arrival time detector. A single-ended charge pump output driver requires two input signals, a polarity signal and an enable signal. While the enable signal determines how long the output current should be enabled, the polarity signal determines the polarity of the output current.

Nonlinear Phase Locked Loop As shown in FIG. 24, as a fourth embodiment, the block diagram of the nonlinear phase locked loop 171 includes a linear phase detector 170, a loop filter 106, an amplifier with an infinite gain 130, and a variable delay circuit 172. Including. Traditionally, in most linear phase locked loop applications, the VCO is usually used as the feedback module 105, but the use of the VCO creates a linear phase locked loop in the arrival time locked loop. This is because the VCO can change the phase and frequency of the feedback signal 112 simultaneously, so that the arrival time of the feedback signal 112 becomes a variable compared by the error comparator instead of the phase. A phase locked loop that uses a VCO as the feedback module 105 is no longer a phase locked loop. For a phase locked loop, which is a pure phase locked loop, the variable delay circuit 172 must be used as the feedback module 105 to control the phase shift of the feedback signal 112, and the entire phase locked loop system is at the same frequency. Can only be activated. This type of pure phase-locked loop is commonly known as a delay-locked loop.

  The simplest way to generate a non-linear phase-locked loop 171 is to use a linear phase detector 170 having an amplifier with an infinite gain 130, as shown in FIG. The linear phase detector 170 can be made in a variety of ways, and the simplest method is to use an exclusive OR gate 145 as shown in FIG. 25 as an analog linear phase detector. The exclusive OR gate 145 provides a multiplication product from the two input signals, and the average phase detector output 187 of the multiplication product at the end of the phase comparison cycle is the two input signals as shown in FIG. The phase relationship between them is shown. If the phase difference between the two input signals to the exclusive OR gate 145 is 90 degrees, the output voltage of the average phase detector 187 on the averaging capacitor 188 is zero at the end of the phase comparison cycle and the averaging capacitor 188 The upper average phase detector 187 is more positive at the end of the phase comparison cycle if the phase difference is greater than 90 degrees and more negative at the end of the phase comparison cycle if the phase difference is less than 90 degrees. The sample and hold circuit 185 is necessary to generate the average error output voltage 117 at the end of the phase comparison cycle. A non-linear amplitude comparator 139 is then used to check the polarity of the average error output 117 and to determine if the phase difference between the two input signals is greater than or less than 90. The non-linear amplitude comparator 139 is used as an amplifier with an infinite gain 130 that produces a decision output 123 because it only produces either one of two digital output states, H or L. Nonlinear amplitude comparator 139 can also be replaced with OPAMP configured as an active low pass filter to provide infinite DC gain to the loop.

  The linear phase detector 170 shown in FIG. 25 is very easy to understand and implement, but the two input signals to EXOR 145 must always have a full 50% duty cycle. Since a duty cycle deviating from 50% will generate a net DC voltage at the phase detector output 187 on the averaging capacitor 188, deviating from a 50% duty cycle will affect the accuracy of the phase comparison. Can be affected. Another disadvantage of the analog linear phase detector 170 is that it requires many linear members and uses a lot of area inside the IC. The most serious limitation of the conventional analog linear phase detector 170 is the small phase detection in the range of +/− 90 degrees. Therefore, a better phase detector is highly desirable.

  A novel digital linear phase detector 174 shown in FIG. 27 is used as a first supplemental embodiment to the fourth embodiment to solve some of the problems of the analog linear phase comparator 170 caused by the exclusive OR gate 145. Provided to. The novel digital linear phase detector 174 is formed from four flip-flops and two charge pumps. The four flip-flops are grouped into two special PFD modules 232 and 234. These special PFD modules do not require an AND gate to reset the flip-flop. In normal PFD, an AND logic gate is required to generate a reset signal for the flip-flop, so that both flip-flops end the comparison cycle when the last arrival signal finally arrives. To reset. Instead of using an AND gate, one of the output signals from the flip-flop is used as the reset signal for the PFD, and the signal is forced to be the last arrival signal. For the PFD module 234, the reference signal 110 is always the last signal, and for the PFD module 232, the feedback signal 112 is always the last signal. An operation timing diagram of this new digital linear phase detector 174 is shown in FIG. Since feedback signal 112 is a reset signal for PFD 232, sourcing charge pump 127 can be used during a period equal to the phase difference between feedback signal 112 and previous reference signal 110. Since the reference signal 110 is a reset signal for the PFD 234, the sinking charge pump 129 can be used during a period equal to the phase difference between the feedback signal 112 and the current reference input signal 110. If the feedback signal 112 is more than 180 degrees after the reference input signal 110, the sourcing charge pump 127 will cause the average phase detector output voltage 187 to be longer than the time that the sinking charge pump 129 decreases the average phase detector output voltage 187. The average phase detector output voltage 187 is positive at the end of the phase comparison cycle. If the feedback signal 112 is after the reference signal 110 by less than 180 degrees, the sinking charge pump 129 will have the average phase detector output voltage 187 longer than the time that the sourcing charge pump 127 increases the average phase detector output voltage 187. The average phase detector output voltage 187 is negative at the end of the phase comparison cycle. Since the flip-flop is activated by the end of the clock input, the clock duty cycle is irrelevant and the digital linear phase detector 174 can detect all phase errors of +/− 180 degrees as shown in FIG. .

  Thus, the digital linear phase detector 174 is a better design than the analog linear phase detector that uses the EXOR gate 145 as the linear phase detector 170. This type of digital linear phase detector 174 is commonly known as a Type II phase detector. Nevertheless, in the analog 145 and digital 174 design for the linear phase detector 170 as shown above, the analog 145 and phase error determination can only be made at the end of the phase comparison cycle. This is because in both designs, two reference signals 110 having different phases are actually used to measure the phase of the feedback signal 112. In the design of an analog linear phase detector that uses an exclusive OR gate 145, the rising and falling edges of the reference signal 110 are phase references, and the decision threshold 164 of the analog linear phase comparator 145 is the reference signal 110. Half of the rising and falling edges. Assuming that the reference input signal 110 has a completely 50% duty cycle since the rising edge of the reference signal 110 is 0 degrees and the falling edge of the reference signal 110 is 180 degrees, the analog linear phase comparator 145 The determination threshold value 164 of the phase is exactly 90 degrees. In a design using digital linear phase detector 174, the rising edge of current reference signal 110 and the rising edge of previous reference signal 110 are two reference signals. Since the rising edge of the current reference signal 110 is 360 degrees and the rising edge of the previous reference signal 110 is 0 degrees, the phase comparison decision threshold 164 is half between these two signals, The phase is exactly 180 degrees. In both designs, the phase comparison decision threshold 164 is never explicitly generated. A decision for error output 117 may be generated after the outputs from both reference signals averaged by averaging capacitor 188. As a result, both phase detectors 145 and 174 require long latency delay times. This is because no decision is made until the output of the phase detector is averaged at the end of the phase comparison. Both the analog linear phase detector 145 and the digital linear phase detector 174 having an amplifier with infinite gain 130 require a sample and hold circuit 185 to generate a final phase comparison error output 117 at the end of the phase comparison cycle. A sampling clock 184 for the sample and hold circuit 185 can be generated from the reference input clock 110 because the reference input clock 110 determines the phase reference. Sampling clock 184 also provides latency delay time for the non-linear phase-locked loop.

  If the phase can be determined simply by comparing a single reference signal 110 with a single feedback signal 112 having a non-linear phase comparator 176, the latency delay time of the analog phase comparator can be improved. Since it is more difficult to define a phase reference for phase comparison, the nonlinear phase comparator 176 is not very popular. The phase of the signal is quite different from other features of the signal. The signal phase ranges from 0 to 360 degrees, and the signal phase can be interpreted differently. For example, the signal A that is 100 degrees after the signal B is also interpreted as the signal A that is 260 degrees ahead of the signal B. To prevent confusion, the phase difference between the two signals is usually limited to 180 degrees or less, so signal A is asserted 100 degrees after signal B, as in the above example.

  A block diagram of a nonlinear phase-locked loop using a nonlinear phase comparator 176 as the spread spectrum generator 166 is shown in FIG. 30 as a fifth embodiment. A non-linear arrival time comparator is ideal for use for the non-linear phase comparator 176 because it can easily detect the phase difference between two signals. Nevertheless, it is necessary that the phase range for the non-linear arrival time comparator be clearly defined so that the non-linear arrival time comparator is always properly reset before making a phase comparison. A novel digital design of a non-linear phase comparator 176 that can detect different phases in the full range of +/− 180 degrees with a minimum latency delay and can be made entirely with digital components is the fifth. A supplemental embodiment to the embodiment is shown in FIG. The novel nonlinear phase comparator 176 is composed of two nonlinear arrival time comparators 190 shown in FIG.

  In this new design, for each two arrival time comparators 190, two streams of reset clocks with opposite phases need to be provided. The reset clock must be generated from the falling edge of the reference signal input 110 so that the rising edge of the reference signal input 110 is located exactly halfway between the edges of the reset clock, as shown in FIG. The two reset clocks are called an even clock 199 and an odd clock 192. If even clock 199 is H, the even arrival time comparator remains in the default state, while the odd clock is L and the odd arrival time comparator generates a decision output for phase comparison; If the odd clock 192 is high, the odd arrival time comparator remains in the default state, the even clock is L, and the even arrival time comparator produces a decision output for phase comparison. Even and odd arrival time comparators can alternately generate decision output 123 for phase comparison, and only one of the two arrival time comparators 190 can generate decision output 123 at any given time.

  In each phase comparison cycle, the reference input signal 110 always arrives at a phase of 180 degrees, the beginning of the phase comparison cycle is always 0 degrees, and the end of the phase comparison cycle is always 360 degrees. Using two reset clock streams, the phase of each arrival time comparison cycle is very clear, and the decision output 123 is present until the new phase comparison cycle begins and the new phase comparison cycle produces different results. In this state, both flip-flops of the arrival time comparator 190 are always in the default state. As a result, the arrival time comparator can generate a phase comparison decision output 123 very quickly in every comparison cycle with only the arrival signals from each of the two input signals. 180 degrees and 360 degrees are clearly defined. If the feedback signal 112 leads to a reference input signal 110 that always arrives at 180 degrees, the arrival of the reference input signal 110 immediately changes the decision output 123 to L when the reference input signal 110 arrives. On the other hand, when the feedback signal 112 arrives, the feedback signal 112 changes the decision output 123 to H. Thus, the design of the non-linear phase comparator 176 is an accurate design of the phase comparator without ambiguity. Nevertheless, the output of the nonlinear phase comparator 176 has a dead zone, such as the dead zone of the nonlinear arrival time comparator 189.

  In order to eliminate the dead zone, it is necessary to use the linear arrival time detector 178 shown in FIG. 34 instead of the non-linear arrival time comparator 176 as a second supplemental embodiment to the fourth embodiment. This design is the best design among all nonlinear phase comparators. This novel linear phase detector 178 using a non-linear arrival time comparator 190 is superior to the two designs of the previous linear phase detectors 145 and 174. This is because the new linear phase detector 178 can generate new decisions with a single arrival event that is fast, accurate, and unambiguous. This can also generate an error output signal 117 without a dead zone, so that a determination is made as soon as the error input signal exceeds the decision threshold 164 and the sample and hold circuit 178 is no longer needed and the linear phase detector The output of 178 can be used directly as the error output 117. Since the error output signal 117 is typically held by a very small stray capacitance, an extra to hold the error output 117 so that the error output can remain at the same level until the next arrival time comparison begins. A capacitor may be required.

  The conversion characteristic of the variable delay circuit 172 is normally linear so that the phase delay of the feedback signal 112 is controlled by linearly increasing or decreasing the final error correction output 115. Using the linear variable delay circuit 172, the nonlinear phase locked loops 166 and 171 can only generate random phase spread for the spread spectrum clock output signal 109, like the nonlinear amplitude locked loop 135. As a result, the spread of the spread spectrum clock output signal 109 generated from the non-linear phase locked loops 166 and 171 using linear variable delay circuits is very small compared to a system that generates frequency spread.

  In order to improve the spread of the spread spectrum clock generated from the non-linear phase locked loops 166 and 171, the conversion characteristic of the variable delay circuit 172 needs to be improved. When the conversion characteristic of the variable delay circuit 172 is not a linear function of the final error correction output 115 but a square function, the linear increase / decrease of the final error correction output 115 is variable delay circuit 172 with a phase that changes according to the square function of time. Produces output from. Since the accumulated phase change of the signal with a linear increase / decrease exceeding the time period is proportional to the square function of time, the variable delay circuit 172 having the square function conversion characteristic outputs the spread spectrum clock output of the nonlinear phase lock loop 135 from the phase spread. The diffusion efficiency can be improved efficiently, and the diffusion efficiency can be greatly improved.

As shown in FIG. 35, the nonlinear frequency lock loop spread spectrum generating apparatus is a sixth embodiment 196 in which a linear frequency detector 194 and an amplifier having an infinite gain 130 are used, or as shown in FIG. The seventh embodiment 213 can be manufactured by using a non-linear frequency lock loop by a method using a non-linear frequency comparator.

  The linear frequency detector 194 is a linear device that generates an analog output having a conversion characteristic as shown in FIG. 37 from a frequency difference between two input signals. Many current linear frequency detectors are built with analog components, such as ratio detectors or quadrature detectors that generate S-curves for conversion characteristics. These analog linear frequency detectors are usually very difficult to use because the gain of these analog linear frequency detectors is usually very low and a large transformer or coil is required. As a result, it is very difficult to implement a complete analog linear frequency detector inside the IC. There are also many ways to implement a linear frequency detector using a digital design. These digital designs for linear frequency detectors can be easily implemented inside the IC, but the current design of digital linear frequency detector 194 is too slow or inaccurate, and phase detector or phase -Current digital linear frequency detectors are not useful at all because they are inferior to frequency detectors. Currently, the only use of digital linear frequency detectors is to create a linear frequency locked loop to help the phase locked loop that initially obtains the reference input signal 110. Once the frequency difference between the two input signals to the phase locked loop is reduced to within the capture range of the phase locked loop, the linear frequency locked loop is then exited. Linear frequency lock loops are rarely used today. Because the current design of the linear frequency lock loop does nothing, it cannot even generate a signal with the correct frequency.

  There are many disadvantages to the current design of the digital linear frequency detector 194. First, most of them are slow to detect frequency differences. In order to know the frequency difference, the beat cycle of the beat signal between the two input signals and the die frequency are usually measured. From the duty cycle of the beat signal, it can be seen that the signal has a higher frequency, and from the frequency of the beat signal, it can be seen how different the two frequencies are. Unfortunately, the smaller the frequency difference between the two input signals, the lower the frequency of the beat signal. Since the duty cycle is measured only when the complete cycle of the beat signal has passed, it takes a very long time to determine the duty cycle when the frequency of the beat signal is small. Usually, in order to speed up the decision process, a frequency time frame is needed so that when the frequency of the beat signal is within the time frame, the two frequencies are considered in a fixed condition. This frequency time frame is sometimes referred to as the dead band, and introduces a second difficulty for the frequency detector, namely the inability to accurately detect the frequency difference. Third, to measure the frequency with the flip-flop, the feedback signal from the VCO 112 is timed asynchronously by the reference input signal 110, or vice versa, ensuring a metastable problem for the flip-flop. Occurs. This problem occurs in flip-flops because when the clock and data inputs arrive at the flip-flop at the same time, it is not known what the flip-flop should do. Because of the flip-flop that registers the data input signal without error, the data input signal is faster than the clock signal arrives at the clock input port of the flip-flop by a time sufficient to satisfy the setup time. Should arrive at the data entry port. The data input signal is then maintained at the same level for a period longer than the flip-flop hold time requirement after the clock signal arrives to maintain an error free output. If one of the setup time or hold time requirements is violated, the output of the flip-flop can become unpredictable and this problem is known as a metastable problem. The metastable problem is a fundamental design flaw for many of today's frequency detectors, and this problem greatly limits the accuracy and usefulness of current frequency detectors, so frequency lock loop technology has been There has not been much progress in the meantime.

  One of the most popular conventional digital linear frequency detectors is that shown in FIG. In this design, the signal from VCO 112 is split into two paths, I path 215 and Q path 217, which are 90 degrees out of phase with each other. Two flip-flops 218 and 219 on the I path 215 and Q path 217 are used to detect the frequency difference between the feedback signal from the VCO 112 and the reference input signal 110. A timing diagram of the operation of the conventional digital linear frequency detector 194 is shown in FIG. From the sequence of how the flip-flop changes state, it can be seen which signal has a faster frequency. Since the reference input signal 110 moves from right to left through feedback signals from the VCOs 215 and 217 when the frequency of the reference input signal 110 is faster, the I flip-flop 219 when the Q flip-flop 218 changes from the L state to the H state. Remains in the L state. Since the reference input signal 110 moves from left to right through the feedback signals from the VCOs 215 and 217 when the frequency of the reference input signal 110 is slow, the I flip-flop 219 will change when the Q flip-flop 218 changes from L to H state. It remains in the H state. As a result, whether or not the frequency of the feedback signal from the VCO 112 advances faster than the reference input signal 110 using the output signal from the Q flip-flop 218 that measures the output from the I flip-flop 219 to the UD flip-flop 221. Recognize. Here, the UD flip-flop 221 generates a U / D control 230 for VCO correction. The amount of VCO correction is determined by the frequency of the beat signal 223 generated using an exclusive OR (OR) gate 225. The higher the beat signal frequency, the more corrections to the VCO 108 are required. This design is simple and easy to implement. However, this design has a basic metastable problem because the reference input signal 110 from the VCO 112 and the feedback signal are asynchronous. The flip-flops 219, 218 do not know what to do if the reference input signal 110 and the feedback signals from the VCOs 215, 217 arrive at that flip-flop at the same time. As a result, this design cannot accurately detect the frequency difference. The accuracy of the current digital frequency detector 194 shown in FIG. 38 is typical only at about 1000 ppm.

  US Pat. No. 6,842,049 discloses another embodiment of a frequency detector that provides a method for detecting a frequency difference by measuring a beat signal. Unfortunately, the frequency of the beat signal is so low that the response time of this frequency detector is very long. Another US Pat. No. 6,834,093 discloses another embodiment that uses a calculator to compare frequencies and requires a large divider to slow response time. There are many other designs for digital linear frequency detectors, but all these current designs of frequency detectors are very similar to the above three techniques and simply make frequency detection fast and accurate. Can not be executed.

  An accurate and precise digital frequency detector is difficult to design but is not required to produce a spread spectrum clock generator. As shown in FIG. 36, the use of a non-linear frequency comparator for the spread spectrum clock generator can further suppress the problem. Unlike linear frequency detectors that need to generate both accurate polarity and amplitude outputs for frequency differences, nonlinear frequency comparators can only generate accurate polarity outputs for frequency differences. The design is easier because it requires. As shown in this disclosure, there are many ways to form an accurate and precise nonlinear frequency comparator for use in a nonlinear frequency lock loop that generates a spread spectrum clock.

  In the non-linear frequency locked loop shown in FIG. 36, the non-linear frequency comparator can generate a final error correction voltage 115 for the VCO 108 only in two stable states, H or L, to determine for the non-linear frequency comparator. The threshold 164 is accurate with zero frequency difference without ambiguity. For spread spectrum clock generators, it is possible to use the current design of frequency comparators with decision ambiguity, but as mentioned above, in a non-linear arrival time lock loop, the decision ambiguities cancel each other out. Since the polarity determination can be generated, a nonlinear frequency comparator with decision ambiguity generates a modulated signal that grows on the final error correction output 115 that adjusts the VCO and generates a cycle slip from the VCO to the feedback signal 112. very difficult. As a result, the nonlinear frequency comparator with decision ambiguity does not spread the feedback signal from the VCO 112 at random as does the nonlinear frequency comparator without decision ambiguity.

A block diagram using a typical non-linear frequency as a spread spectrum clock generator 214 that generates a spread spectrum clock output signal having a frequency F _OUT equal to N times the frequency of the reference input signal 110 is shown in FIG. For the nonlinear frequency, the typical nonlinear frequency lock loop 214 is more useful than the basic nonlinear frequency lock loop as the spread spectrum clock generator 213. This is because the frequency of the spread spectrum clock output signal 109 can be easily changed. The frequency divider 111 that divides the feedback path by N also gives more delay time to the feedback signal, so the oscillation frequency of the loop is low and the frequency spread is wider. The extra delay time can help the loop spread the clock signal frequency more evenly.

  The following is a novel design for a nonlinear frequency comparator that is fast, accurate, and free from all existing metastable problems. The best solution for the new digital frequency comparator is to improve the current design 194 shown in FIG. 38 by correcting the metastable problem. The metastable problem is solved by using the phase frequency detector (PFD 132) shown in FIG. 41 that detects the frequency difference instead of using a flip-flop. FIG. 42 is a timing diagram of a PFD that drives a charge pump output having the same shape (both heads) at both ends.

  The PFD 132 includes two flip-flops that generate a reset signal for the flip-flops, and an AND gate 126. One of the two flip-flops of the PFD 132 is set when the first signal arrives, and both flip-flops are reset after the arrival signal arrives. If the reference input signal 110 arrives first, it sets the reference flip-flop 122 and the UP output 242 goes high (H), and that high state is maintained until the last feedback signal arrives from the VCO 112. The The feedback signal from the VCO 112 is a signal for setting the VCO flip-flop 124 and generating a reset signal 128 that clears both flip-flops by the AND gate 126. If the feedback signal from the VCO 112 arrives first, instead, the same process is repeated except that the DOWN output 244 goes high (H) first. Since each flip-flop is always triggered by only one signal, the PFD 132 has no metastable problem. And since both flip-flops of PFD 132 are reset by the most recent arrival signal, the reset signal 128 generated from AND logic gate 126 should be used as an indicator for the most recent arrival signal, as shown in FIG. Can do.

  The simplest way to know if there is a frequency difference between two signals is to see how one signal slides through the other. When there is no frequency difference, the two signals are stationary relative to each other so that there is no slide-through. If there is a slight frequency difference, one of the signals slides through the other at the rate of the frequency difference. The frequency difference generates a beat signal. Because it is a frequency comparator, you only want to know which signal is faster, not the amount of frequency difference between the two signals. As soon as you know the mutual slide-through of the two signals, you know immediately which signal is faster. A single slide-through is sufficient to know which signal is faster. In order to know which signal is faster, it is not necessary to wait for the whole period of one cycle of the beat signal, and the latency delay time of the new nonlinear frequency comparator is short.

In order to see how one signal slides through the other, one of the two input signals needs to provide an orthogonal reference to the other signal. As shown in FIG. 43, which is a schematic diagram of a nonlinear frequency comparator 220 that uses two PFDs as a first supplementary embodiment with respect to the seventh embodiment, a reference input signal 110 serving as an orthogonal reference signal can be selected. In order to do so, the reference signal 110 needs to be split into two paths and a separate PFD 132 must be used for each path. The two orthogonal reference signal paths are referred to as I _ref 272 and Q _ref 274 and an OR logic gate 256 is used to generate the final reset output 258 by combining the reset signal output 128 from each PFD 132. The For best results, the phase relationship between quadrature signals should be equal to 360 / N, where N is equal to the number of PFDs used for frequency comparison. When N = 2, the phase relationship between the two quadrature signals is 180 degrees, so the quadrature reference can be easily implemented using an inverter. Irregularly spaced phase differences between orthogonal signals generate frequency noise that is not uniform for frequency comparisons and must be prevented. The period of the orthogonal reference signal determines the period of the frequency comparison cycle.

In the design of the nonlinear frequency comparator 220 shown in FIG. 43, if the frequency of the reference signal 110 is earlier than the frequency of the feedback signal from the VCO 112, the feedback signal from the VCO 112 will generate a reset signal for both PFDs 132. Signal. Both I _ref 272 and Q _ref 274 reference input signals are compared to the same feedback signal from the VCO 112 and both PFDs are reset by the same feedback signal from the VCO 112 so that for all frequency comparison cycles, the final reset output 258 has only one reset output signal. If the frequency of the feedback signal from the VCO 112 is faster than the frequency of the reference input signal 110, the reference input signal is the latest arrival signal that generates a reset signal for both PFDs. Since the two I and Q reference signals are out of phase, the reference inputs I _ref 272 and Q _ref 274 occur at different times. As a result, there are two separate reset output signals in the final reset signal 258 at the output of the OR logic gate 256 for all frequency comparison cycles. The pulse width of the reset signal 128 from the PFD 132 is determined by the sum of the propagation delay of the flip-flop from the reset input and the propagation delay of the AND logic gate 126, and the pulse width of the reset signal 128 is the propagation delay of a single logic gate. It is almost equal to 4 times.

  Thus, it is clear that by counting the number of reset pulses with the final reset signal 258 at the output of the OR logic gate 256, it can be known which signal is faster. If the frequency of the reference input signal 110 is faster, there is only one reset signal in every frequency comparison cycle. If the frequency of the feedback signal from the VCO 112 is faster, there are two reset signals in every frequency comparison cycle.

Since the two input signals are asynchronous, the final reset signal 258 at the output of the OR logic gate 256 can be generated by the reference input signal 110 or the feedback signal from the VCO 112. The timing uncertainty between two asynchronous input signals, particularly when a cycle slip occurs, can create a malfunction at the output of the OR logic gate 256. The cycle slip is when the slow signal is much later than the fast signal and the next fast signal arrives during the flip-flop reset period caused by the current slow signal and the next fast signal is lost without being registered. appear. As a result, the slow signal is essentially a fast signal for the next frequency comparison cycle. The slow signal may even remain for a short period of time before the fast signal catches up with the slow signal,
When the feedback signal from VCO 112 is a slow signal, the feedback signal from VCO 112 generates a reset pulse for both PFDs. Since the two reset signals are both generated from the same feedback signal from the VCO 112, the final reset output 258 at the OR logic gate 256 is always the same reset pulse 128 as each PFD. However, when a cycle slip occurs, one of the PFDs generates a reset signal 128 from the reference input signal 110 and the other PFD still generates a reset signal 128 from the feedback signal from the VCO 112, and OR The final reset pulse 258 at the output of logic gate 256 no longer comes from the same source. When a cycle slip occurs, two reset pulses are generated from two different sources, and these two final reset pulses are very close to each other in phase so that the final reset coupled to the output of OR logic gate 256 The pulse output 258 is one or two pulses, and defects due to timing uncertainty between the two asynchronous input signals can be generated. Thus, when the feedback signal from the VCO 112 is a slow signal, cycle slip can increase the number of reset pulses by one.

  If the reference input signal 110 is a slow signal, the reference input signal 110 generates two reset pulses in every frequency comparison cycle. When a cycle slip occurs, one of the reset pulses is generated by the feedback signal from the VCO 112 and the other is further generated by the reference input signal 110. Since the two reference input signals are spaced by an offset of 180 degrees, the two final reset pulses 258 at the output of the OR logic gate 256 are also spaced approximately 180 degrees apart during all periods, even during the cycle slip period. Opened, these two reset pulses do not interfere with each other. Only when the reference input signal 110 is a late signal, the cycle slip can slightly affect the timing of the final reset pulse 258.

  With this understanding, the non-linear frequency comparator 220 can be designed using only two PFDs as shown in FIG. 43 and is formed from three structural modules: a quadrature module 305, a reset pulse module 307, and a decision module 309. The quadrature module 305 is generated from a reference quadrature signal that is compared to the feedback signal from the VCO 112 of the reset pulse module 307. The determination module 309 then determines the polarity of the frequency comparison by counting the number of set pulses that occurred in the frequency comparison cycle. In this circuit, an enable signal 250 is generated by passing the final reset signal 258 through the asynchronous quadrant divider 260, which is used as a reset signal to the frequency determination latches 266 and 268. The two frequency determination latches 266 and 268 alternately generate the frequency determination output stored in the four output latches 264. An OR logic gate with four inputs 270 is then used to generate the final decision output 123 by combining all the outputs from the output latch.

  Since the frequency of the final reset pulse 258 is equal to the frequency of the reference input signal 110 or twice the frequency of the reference input signal 110, the frequency of the enable signal 250 is half the frequency of the reference input signal 110 or the reference input. It is a quarter of the frequency of the signal 110. As a result, the enable signal 250 remains at either the H or L level for a period that is one time that of the reference input signal 110 or twice that of the reference input signal 110. If enable signal 250 remains for a period that is one time that of reference input signal 110, frequency determination latches 266 and 268 do not generate an H output at output latch 264. This is because it requires at least two clock edges from the reference input signal 110 to measure the H output to the output latch 264. Only when the feedback signal from the VCO 112 is a slow signal, the enable signal 250 generates an H output for the output latch 264, and the frequency of the enable signal 250 is a quarter of the reference input signal 110, so The enable signal 250 remains at one of the H and L levels for two reference input signals 110. As a result, as soon as the H output is detected at the decision output 123, it can be seen that the feedback signal from the VCO 112 is a slow signal.

  However, if a cycle slip occurs, this simple frequency comparator using only two PFDs cannot produce an accurate frequency comparison result. If the feedback signal from the VCO 112 is slow and a cycle slip occurs, the failure of the final reset pulse 258 can increase the number of reset pulses up to two and the frequency of the enable signal 250 increases immediately. As a result, the period of the enable signal 250 is shorter than the two clock periods of the reference signal 110, and the output latch 264 generates an incorrect L decision output 123. The erroneous decision output 123 is obvious, especially when the frequency difference between the two input signals is small, and it takes more time for the reference input signal 110 to overcome the cycle slip. As a result, as with all other current frequency comparators, when the frequency difference between two input signals is small, the design of the nonlinear frequency comparator 220 using two PFDs as shown in FIG. Produce accurate results.

  One possible solution to reduce the effects of cycle slip for a nonlinear frequency comparator 220 that uses only two PFDs as shown in FIG. 43 is to increase the pulse width of the final reset signal 258. If the feedback signal from the VCO 112 is a slow signal, the cycle slip will cause an error, and in addition, if the feedback signal from the VCO 112 is a slow signal, the two signals will be in phase with each other during the cycle slip period. Since it is not too far away, extending the final reset signal 258 long enough can repair the failure, but the best way to handle the failure is to not first cause it. Defects are generated by the design engineer, and after they are generated, there is no effort to repair the defects. The design engineer must simply design a circuit that is free from defects (periods).

  A cycle slip is inevitable and occurs whenever two asynchronous signals move relative to each other. The number of PFDs 132 needs to be increased in order to overcome the disadvantages generated by cycle slips that can increase the reset signal by one. If three PFDs are used for frequency comparison, if the frequency of the feedback signal from VCO 112 is fast, there are three reset signals per frequency comparison cycle. If the feedback signal from the VCO 112 is fast, the reference input signal 110 is the latest arrival signal, so all three final reset output signals 258 are generated by the reference input signal 110. During the cycle slip period, one of the reset pulses of the final reset output 258 can be generated from the feedback signal from the VCO 112 and the timing of the final reset pulse 258 can vary. Since the three orthogonal reference input signals are phase shifted by 120 degrees, the reset pulses of the final reset output 258 do not interfere with each other even during the cycle slip period. However, timing uncertainty due to cycle slip can cause uncertainty in the timing of the final reset pulse 258. Since the number of reset pulses in the fixed period of the reference comparison signal 110 is counted, the number of reset pulses in the fixed frequency comparison period is reduced to two due to timing uncertainty when a cycle slip occurs. be able to.

  If the frequency of the reference input signal 110 is faster, all three PFDs will generate a reset signal from the same feedback signal from the VCO 112, so the feedback signal from the VCO 112 will usually be at the final reset output 258 of every frequency comparison cycle, Only one reset pulse is generated. During a cycle slip, the reference input signal 110 that is asynchronous to the feedback signal from the VCO 112 and is very close in phase to the feedback signal from the VCO 112 generates one of the current reset pulses, so that the final reset The number of reset pulses on output 258 will be two or one during the cycle slip period due to the timing uncertainty of the two asynchronous input signals. As a result, if the number of reset output signals of the final reset output 258 is one or three in the frequency comparison cycle, it is possible to reliably know which signal is faster. Thus, a design that uses three PFDs for a nonlinear frequency comparator can always produce accurate frequency comparison results. If the number of reset pulses in the frequency comparison cycle is two, it cannot be determined, so it takes a lot of time for the nonlinear frequency comparator to switch the determination. Therefore, the latency delay time of the non-linear frequency comparator using three PFDs is thus increased. This is because the decision output 123 can only be changed when it requires at least two frequency comparison cycles and the number of reset pulses changes from one to three or from three to one.

  An example of a non-linear frequency comparator 200 that uses three PFDs 132 is shown in FIG. 44 as a second supplemental embodiment to the seventh embodiment. The digital frequency comparator 200 can be formed by three modules: a quadrature module 305, a reset pulse module 307 and a determination module 309. The quadrature module 305 generates a quadrature reference signal for frequency comparison performed in the reset pulse module 307. In order to generate a quadrature signal having the correct phase, a high frequency reference clock 261 having a frequency equal to the number of PFDs used in the reset pulse module 307 multiplied by the frequency of the comparison reference input signal 110 is required. .

  A high frequency reference clock 261 with a frequency equal to three times the frequency of the reference input signal 110 is then three equally spaced quadrature references with exactly 120 degrees of phase difference between any two adjacent reference signals. Signals 110, 306 and 308 are generated. The reset pulse module 307 generates a final reset pulse 258 for the decision module 309 by combining all reset output signals 128 from each PFD 132 having an OR gate 256. The determination module 309 determines which signal has a higher frequency by counting the number of reset pulses that occur during the period of the reference input signal 110 (which is also the frequency comparison period).

As shown in FIG. 44, an OR logic gate with three inputs 256 is used to combine the three reset signals 128 from the three PFDs that result in the final reset output signal 258. There are various designs of the decision module 309 that determines which signal is faster by counting the number of reset pulses from the final reset output 258 during the reference frequency comparison period 110. The simplest way to configure the decision module 309 is to use a divide-by-three divider 320 as shown in FIG. 44, resulting in a final reset output that results in a lower frequency trigger signal 222 for the one-shot generator 262. The one-shot output 224 is finally stored sequentially in the 9-bit shift register, and the 9-bit adder 228 stored in the 9-bit shift register 226 is used. The sum of 228 is equal to the number of reset signals generated during the reference frequency comparison signal 110. The decision can then be made accurately from the result of the 9-bit adder 228. If the sum of the 9-bit adder 228 is 3, the frequency of the VCO signal 112 must be faster than the frequency of the reference signal 110. If the sum of the 9-bit adder 228 is 1, the frequency of the signal from the VCO 112 must be slower than the frequency of the reference input signal 110. This design is very simple but requires a lot of hardware, and the number of hardware increases exponentially as the number of PFDs used increases. The number of flip-flops required in this design increases with the ratio of N ² and N of the number of PFDs used.

  In this design shown in FIG. 44, a divide-by-three divider 320 is used to divide the final reset signal 258 into three. The final reset pulse 258 from the output of the OR logic gate 256 has a very short period, and the timing of the final reset pulse depends on whether one of the feedback signal from the VCO 112 or the reference input signal 110 arrives later. Synchronize with. Accordingly, the timing of the final reset pulse 258 can change. The nature of timing uncertainty and short time period makes it very difficult to process the final reset pulse 258 directly.

  The short time period problem can be solved by using a frequency divider 320 to extend the reset pulse period, and the timing uncertainty problem can be solved with a one-shot circuit 262 measured by the high frequency reference clock 261. It is solved by using. A typical one-shot circuit 262 is shown in FIG. The one-shot circuit 262 always generates an output signal 224 measured by the high-frequency reference clock 261, and the time period of the H output from the one-shot 262 is fixed and always equal to the clock cycle of the high-frequency reference clock 261. . Thus, the metastable problem is no longer a problem. This is because the pulse width of the output pulse 224 from the one-shot 262 can be changed even though the timing of the output pulse 224 from the one-shot 262 can be changed by the clock cycle of the high-frequency reference clock signal 261 due to timing uncertainty. This is because it is always one clock cycle of the high-frequency reference signal 261. In other words, the metastable problem still affects this design but does not adversely affect it. This is because the worst effect the metastable problem has on this design is to delay the output 224 from the one-shot 262 by the clock period of the high frequency reference clock signal 261.

  This one-shot 262 has two JK flip-flops, and the output of the first JK flip-flop 312 is H, while the second JK flip-flop 314 is still L. Sometimes the output of the one-shot 262 is generated. The output from the two J-K flip-flops is a non-trigger part of the high frequency reference clock 261 and a logic before being clocked out by the D flip-flop 316 to ensure timing accuracy. Logically ANDed. The duration of the trigger signal 222 to the one-shot 262 must be longer than the clock period of the high frequency reference clock signal 261 to ensure a successful trigger. Since the maximum frequency of the final reset pulse 258 is three times, the maximum frequency of the trigger signal 222 is the same as the frequency of the reference signal 110 that is 1/3 of the high frequency reference frequency 261. As a result, the trigger signal 222 for the one-shot 262 is always longer than the clock cycle of the high-frequency reference clock signal 261 so that there is always no error in the output 224 from the one-shot 262.

  When the frequency of the feedback signal from the VCO 112 is fast, the trigger signal 222 to the one shot 262 has the same frequency as the reference signal 110, and when the frequency of the feedback signal from the VCO 112 is slow, the trigger signal to the one shot 262 is triggered. The frequency of the signal 222 is only 1/3 of the frequency of the steady state reference input signal 110. When a cycle slip or metastable condition occurs, the frequency of the trigger signal 222 can be 2/3 of the frequency of the reference signal 110.

  A 9-bit shift register 226 for storing the output 224 from the one-shot 262 and an adder 228 for adding a pulse output from the one-shot circuit 262 stored in the shift register 226 for three or more cycles of the reference frequency comparison signal 110 When used, the output of the 9-bit adder 228 indicates how many reset pulses have occurred in one period of the reference frequency comparison signal 110. Basically, the final reset pulse 258 is first divided into three, then it is later multiplied by three to obtain the original number of final reset pulses in the reference frequency comparison period 110 and from the output of the one-shot 262 A 9-bit shift register for storing pulses and an adder 228 for adding them are required. The decision can be made accurately by this design. It is known that when the output of the 9-bit adder 228 is 3, the frequency of the feedback signal from the VCO 112 is known to be faster than the frequency of the reference input signal 110, so it is negative to slow down the VCO 112 frequency. Output is required. When the output of the 9-bit adder 228 is 1, the frequency of the feedback signal from the VCO 112 must be slow and a positive output is required to speed up the frequency of the VCO 112. Multiplexer 237 and latch 239 may be used to generate the decision output 123 signal. Since the output of the latch 239 is changed only when the sum of the 9-bit adder 228 is an odd number, the least significant bit S0 of the output of the 9-bit adder 228 may be used as an enable signal for the multiplexer 237. So, when the least significant bit S0 of the output of the 9-bit adder 228 is false, the output of the latch 239 remains the same. When the least significant bit output S0 of the 9-bit adder 228 is true, the output of the latch 239 is determined by the second least significant output bit S1 of the 9-bit adder 228. The design using shift registers and adders is very simple, but requires more hardware, especially when PFD is used. In order to reduce the amount of hardware, instead of determining which decision module 309 has a faster frequency, as shown in FIG. 46 as a third supplemental embodiment to the seventh embodiment 204, the state A machine 330 is used.

  FIG. 47 shows the algorithm of the state machine 330. The state machine 330 is time-measured by the high frequency reference signal 261. Since the one-shot 262 is also time-measured by the high frequency reference signal 261, its output remains the clock cycle H of the high frequency reference signal 261. As described above, the frequency of the trigger signal 222 at the output of the three-divider divider 320 is between 1/3 the frequency of the reference input signal 110 and the frequency of the reference input signal 110, and the frequency of the reference input signal 110 is Since it is only 1/3 of the high frequency reference signal 261, the period between the one-shot output 224 and the H output is equal to two high frequency reference clock periods when the frequency of the feedback signal from the VCO signal 112 is fast, When the frequency of the feedback signal from the VCO signal 112 is slow, it is one of eight high-frequency reference clock periods. By simply counting how many L states have passed before a new H output from the one-shot 262 arrives, an accurate determination is made each time a new H output from the one-shot 262 arrives. Made. If the current decision output 123 is L, it can only be changed to H when the number of L states is greater than the high decision threshold, and if the current decision output 123 is H, it is Can only be changed to H when the number of is less than a low decision threshold. By this method, the decision output 123 can be made accurately and is not ambiguous.

  Since the state machine 330 method is simple and uses fewer logic gates, however, as shown in the second supplemental embodiment for the seventh embodiment 200, it is determined at a slower rate than the previous shift register and adder method. Is made. This is because the state machine 330 can change the output state only after the arrival of the H output of the one-shot 262 generated at a rate of 1/3 to 1/9 of the high frequency reference clock frequency 261. Conversely, the register and adder method can update the output at the rate of the high frequency reference clock frequency 261. There are many other ways to implement the decision module 309 for a non-linear frequency comparator, and each design has its advantages and disadvantages as the two previous examples shown. Although the response time of the shift register and adder method 200 shown in FIG. 44 is fast, the hardware size increases exponentially as more hardware is used to implement the circuit and the number of PFDs increases. The state machine method 204 shown in FIG. 46 uses a minimum number of hardware, but the response is slow.

  In the above two designs, the decision output 123 can be changed only when the sum of the adders is 3 or 1, and at least two criteria are used to change the sum of the adders from 1 to 3 or from 3 to 1. Since the frequency comparison period 110 is necessary, it takes more time to change the decision output 123.

  As a fourth supplemental embodiment to the seventh embodiment, a new and improved design 430 is shown in FIG. 48 that allows accurate determination at the end of each frequency comparison cycle by using two saturable counters. Shown in The design of decision module 430 is shown in FIG. In this design, the enable signal 408 is generated by dividing the final reset output 258 from the reset pulse module 307 by the divide-by-three divider 320. Using the three PFDs of the reset module 307, there are three reset pulses in every frequency comparison cycle when the feedback signal from the VCO 112 is high frequency, and all frequencies when the feedback signal from the VCO 112 has a low frequency. There is one reset pulse in the comparison cycle. When using the synchronous divide-by-three divider 320 that divides the final reset pulse 258 to generate the enable signal 408 for the saturable counter, does the enable signal 408 have a frequency equal to the frequency of the reference input signal 110? , Having a frequency equal to 1/3 the frequency of the reference input signal 110. If the frequency of the enable signal 408 is equal to the frequency of the reference input signal 110, due to the synchronous divide by frequency divider 320, a duration equal to either 1/3 or 2/3 of the period of the reference comparison frequency input signal 110. During time, the enable signal 408 can remain at either H or L level. When the frequency of the enable signal 408 is equal to 1/3 of the frequency of the reference input signal 110, for a duration equal to one or two periods of the steady state reference comparison frequency input 110 due to the synchronous divide-by-three divider 320, The enable signal 408 can remain at either the H or L level. As a result, the period of the reference signal 110 can be used as a decision threshold to find out which signal is transmitted faster. When detecting an enable signal 408 that remains at the H or L output level for a longer duration than the period of the reference signal 110 (equal to three clock periods of the high frequency reference clock 261), the frequency of the signal from the VCO 112 is more Guaranteed to be slow.

  If the feedback signal from the VCO 112 is fast and a cycle slip occurs, the duration of the enable signal 408 at the output of the synchronous divide-by-three divider 320 is due to the timing uncertainty between the two asynchronous input signals. It becomes slightly longer than 1/3 or 2/3 of the period of the signal 110, or slightly shorter. Timing uncertainty does not change the duration of the enable signal 408 that much. This is because the three quadrature reference signals are spaced by a 120 degree phase offset and the reset pulses do not interfere with each other even during cycle slip. Thus, the period of the enable signal 408 remains substantially the same as 1/3 or 2/3 of the period of the reference input signal 110 and is still well below the threshold of the period of the reference input signal 110. As a result, the saturable counter 406 is never higher than 1, and the CO 404 is always false when the feedback signal from the VCO 112 is a fast signal.

  If the feedback signal from the VCO 112 is slow and a cycle slip occurs, the period of the enable signal 408 is reduced by half due to some fault. As a result, when there is a defect, it is enabled for the period of the reference input signal 110 or half the period of the reference input signal 110 instead of one or two periods of the reference input signal when there is no defect. Signal 408 remains at the H or L level. Thus, regardless of the presence or absence of a cycle slip, enable signal 408 always remains at the H or L level for the duration of reference input signal 110, allowing saturable counter 406 to always reach the top, from VCO 112. The output of the CO 404 is enabled when the feedback signal is a slow signal. As a result, the two saturable counters 406 can easily solve the cycle slip problem.

  Thus, the design of digital frequency comparator 206 using two saturable counters 406 is the best design for providing a decision output 123 with minimal latency delay time for a non-linear frequency comparator. Nevertheless, as you can see from creating a spread spectrum clock generator from a digital arrival time lock loop, the latency delay time of the error comparator increases the frequency spread, so a longer waiting time for the spread spectrum clock generator. Time is not necessarily bad.

  If enable input 408 is false, CO output 404 from saturable counter 406 is held at zero. If enable input 408 is true, it starts incrementing the count of saturable counter 406 whenever a new clock edge arrives. However, for a saturable counter 406 with N = 2, regardless of how many clock edges have arrived, the counter output will not be higher than 2, and the counter output will be held at 2, and N = 2 The Carry Out output CO 404 is held high when the top of the counter it has arrives. For a design 430 that uses two saturable counters 406 as decision module 309, one of the saturable counters 406 is active only when the output of divide-by-three divider 320 is high and the other saturated The possible counter 406 is active only when the output of the three-divider divider 320 is L. The principle of this design is that when the frequency of the signal from the VCO 112 is slow, there is only one reset output at the final reset output 258 of every frequency comparison cycle when the frequency of the signal from the VCO 112 is slow. This means that the period of the enable output signal 408 at the divider divider output 320 is very long. Once a long period is detected from the output of the three-divider divider output 320, it can be seen that the frequency of the signal from the VCO 112 must be slow. The purpose of the two saturable counters is simply to look for a long period at either the H or L level at the output of the divide-by-three divider 320. Once a period from tri-frequency divider output 320 that is longer than three high frequency reference clock periods is detected, the saturable counter enables the CO 404 signal, and the enabled CO 404 signal in turn Stored by the bit shift register 410, the decision output 123 of the frequency comparator is locked by an OR gate with six inputs 412 for the duration of six clock periods of the high frequency reference clock 261, and a fault and decision circuit generated by cycle slip Prevent switching of the saturable counter. As a result, this design provides a fast response time, reduces the amount of hardware, and only increases the number of required shift registers linearly at a rate of 2 * N. Here, N is the number of PFDs used.

  In the design of a frequency comparator using three PFDs and two saturable counters with N = 2, theoretically to prevent faults caused by cycle slips and switching between the two saturable counters An OR gate with a minimum 6-bit shift register and 6 inputs is required. The reason that so many shift registers are required is that the two saturable counters are selectively reset. Once the saturable counter is reset, the current H output is lost immediately. To generate a new H output again, at most six high-frequency reference clock cycles are required, so a 6-bit shift register is required to maintain the current H output. Suppose that one of the two saturable counters is named an even counter and the other is an odd counter, and the even counter is currently producing an H output. In the next cycle where the odd counter is available, it may happen that the odd counter does not generate an H output due to a cycle slip, so it must wait until the even counter is available to generate the next H output. Don't be. It takes at least three high frequency reference clocks for the even counter to generate H output, and it takes at most three high frequency reference clocks for the odd counter not to generate H output due to cycle slip, so a new H output is generated again. Since a high-frequency reference clock is required at most 6 times before starting, a 6-bit shift register is required.

  As a result of using an OR gate with 6 inputs and a 6-bit shift register 410 for the design of the decision module 430, from when the decision output 123 changes from H to L until when it changes from L to H. Since the OR gate advantageously handles the H output, the response time of decision module 430 is not equal. When H is generated for CO 404 from one of the saturable counters, the decision output is immediately H. It takes 3 high frequency reference clocks to generate the H output for CO 404 from the saturable counter, but since 6 high frequency reference clocks are required to exclude the H output from the 6-bit shift register 410, the decision output 123 is It changes from L to H faster than H to L. In contrast, the design of a decision module using a one-shot with shift register and adder as shown in FIG. 44 requires a high frequency reference clock 4-6 times to change decision output 123 from H to L, Alternatively, a high frequency reference clock is required 6 to 9 times to change the decision output 123 from L to H, and the state machine design shown in FIG. 46 uses six high frequency reference clocks to change the decision output 123 from L to H. ~ 9 times are required and a high frequency reference clock is required 3 times to change the decision output 123 from H to L.

  If the number of PFDs 132 is increased to four, there are four reset signals per frequency comparison cycle when the frequency of the feedback signal from the VCO 112 is fast, and one per frequency comparison cycle when the frequency of the reference input signal 110 is fast. There is a reset signal. When cycle slip occurs, when the frequency of the feedback signal from the VCO 112 is fast, the number of reset pulses in each frequency comparison cycle can be three, and the reference input signal is due to the uncertainty caused by the metastable problem. As the frequency of 110 increases, the number of reset pulses is two or one. As a result, you can see which signal is fast, even with cycle slip and metastable problems. Thus, it is clear that at the end of every frequency comparison cycle, which of the two input signals has a fast frequency without error or ambiguity can be determined by more than four PFDs 132. Therefore, the latency delay time of a frequency comparator using four or more PFDs is short because the entire comparison cycle can immediately generate a new comparison result.

  As a fifth supplemental embodiment to the seventh embodiment, an example of a digital frequency comparator 208 using four PFDs 132 is shown in FIG. The decision circuit 309 for the design in FIG. 50 is very similar to the design of FIG. 44 and needs to know whether the sum of the 16-bit adders is 4 or 3. It has been found that if the sum of the 6-bit adders is 4 or 3, the frequency of the feedback signal from the VCO 112 is too fast and must be delayed. The only disadvantage of using the design shown in FIG. 50 is that a lot of hardware is required. One possible way to reduce the amount of hardware involved in the design using the feed register and adder shown in FIG. 51 is to compress the output 224 from one shot. Once the output from the one-shot 224 is compressed, not only the necessary shift registers but also the amount of adders can be saved. The simplest method for compressing the output from one shot is to extend the period of H output from one shot 263 as shown in FIG. For example, if four PFDs with shift registers and adders for the decision module are used, theoretically a 16-bit shift that stores the output from the one-shot 262 over four frequency comparison cycles A register is required. Since the output from the one-shot has a frequency of 1/4 to 1/16 of the high-frequency reference clock frequency 261, the duty cycle of the output from the one-shot is 1/4 to 1/16. If the duration of the period for H output is extended from one shot to two high frequency reference clock periods instead of one period, the duty cycle of the output from one shot 263 is from 1/4 to 1/8 Will be increased. As a result, instead of the 16-bit shift register 227 and the 16-bit adder 229 that are measured by the full speed of the high-frequency reference clock signal 261, 8-bit shift registers 231 and 8 that are measured at half the high-frequency frequency of the reference clock signal 261. A bit adder 233 is required. This simple method of compressing the output signal from the one-shot 263 works in the same way as the original uncompressed design but omits some hardware. As a sixth supplemental embodiment to the seventh embodiment, FIG. 51 illustrates a design that uses a compressed one-shot output to omit the amount of hardware.

  In all the above designs, when the PFD usage count is N, the frequency of the high frequency reference signal 261 must be N times the frequency of the reference input signal 110. The high frequency reference signal 261 is necessary to accurately generate the quadrature signal so that the response of the frequency comparator is linear. If the high frequency reference clock 261 is not available, a delay line or other means of generating the required quadrature reference signal without using the high frequency reference clock can be used. However, the delay times of each delay line must be carefully aligned to maintain a quadrature reference phase relationship.

  Since it is not necessary to measure the frequency of the beat signal, the response time of the all-nonlinear frequency comparator shown so far is fast. Determining which signal is fast takes only one slide-through of the clock edge. Before the slide-through occurs, the output of the nonlinear frequency comparator remains as it is. If the slide-through causes the decision module 309 to change the result of the decision output 123, one slide-through of the edge is sufficient to change the direction of frequency rotation for the nonlinear frequency comparator of the nonlinear frequency lock loop. Since the high-frequency reference signal 261 that is N times the frequency of the reference input signal 110 is used, slide-through occurs at a frequency N times during the beat signal period. Therefore, the operation of the non-linear frequency comparator is increased N times. If more PFDs are used, it is easier and faster to determine which signal is faster because there are more differences in the number of reset pulses in the frequency comparison cycle.

  Since the frequency determination mechanism does not require a lock window and is always accurate, the nonlinear frequency comparator has no deadband. The output of the nonlinear frequency comparator is either high or low. The decision is accurate, error-free, and uncertain. Since all flip-flop triggers are clear, the metastable problem is completely corrected. These novel non-linear frequency comparators other than the design shown in FIG. 43 are thus ideal frequency comparators that provide a fast and accurate binary decision output 123.

  Although the non-linear frequency lock loop is a primary loop, the acquisition operation of the non-linear frequency lock loop is different from other primary feedback control loops. Closer to time lock loop. Since a frequency comparison is performed after a frequency slide-through has occurred, the acquisition process of the frequency lock loop can be shown as in FIG. 53 with a vertical axis on which slide-through units are displayed. Since the beat signal causes slide-through between the two input signals, the frequency of the beat signal depends on how fast the feedback signal from the VCO 112 is changed or rotated through the reference signal 110, so that the actual It is difficult to indicate the vertical axis due to the frequency difference. By using the number of slide-throughs as the unit of the vertical axis, it is easy to understand the acquisition operation of the nonlinear frequency lock loop, and the use of a separate decision output 123 axis can consider the actual frequency of the feedback signal from the VCO 112. It becomes like this. Slide-through and cycle slip are used to explain the same beating phenomenon between two signals having different frequencies. When beating occurs between the two signals, a cycle slip occurs so that it occurs at the same rate as the beat signal. Since multiple PFDs are used for frequency detection, slide through occurs more frequently than cycle slip because there are multiple slide through occurrences during the beat signal cycle. As the frequency difference between the two input signals is reduced, the slide-through frequency is also reduced, so when one signal slides through the other signal at a constant rate, the two frequencies are exactly synchronized. The time interval between slide-throughs increases.

If the initial frequency difference is a positive number, the frequency of the feedback signal from the VCO 112 is initially pumped up by a positive decision, and the beat signal frequency is delayed, slide-through occurs less frequently, Gradually the two frequencies are synchronized. The acquisition process of the nonlinear frequency lock loop can be divided into two phases: a cycle slip phase 542 and a vibration phase 564. In the cycle slip phase 542, the frequency of the feedback signal from the VCO 112 increases and passes through many slide-throughs before the final two frequency synchronization that occurs at t = To 552. Since the feedback signal from the VCO 112 is a slow signal and the nonlinear frequency comparator speeds up the frequency of the feedback signal from the VCO 112 and the final error correction frequency increases the frequency of the VCO, the phase of the feedback signal from the VCO 112 is First, always lag behind the quadrature reference signal 110, and since the frequency of the feedback signal from the VCO 112 is pumped up by the non-linear frequency comparator, the speed of lagging is constantly reduced. When the phase of the feedback signal from the VCO 112 is delayed, a slide-through is generated between the two input signals, which causes the nonlinear frequency comparator to generate an H output for the decision output 123. Since the feedback signal from the VCO 112 is a slow signal, the decision output 123 from the nonlinear frequency comparator is in the H state. If the frequency difference between the two input signals is reduced, less slide-through occurs. Eventually, after the last slide-through (referred to as slide-through # 1) occurs, the two input signals have the same frequency generation at T ₀ 552 at time t = 0. At T ₀ 552, the phase of the feedback signal from the VCO 112 is no longer delayed, and the phase of the feedback signal from the VCO 112 begins to advance further from this time. This is because the frequency of the feedback signal from the VCO 112 is still increased. The feedback signal from the VCO 112 continues to speed up, and the phase continues to advance even after the frequency synchronization point at To552. Because the decision output 123 from the nonlinear frequency comparator is not changed before the slide-through is generated to tell the nonlinear frequency comparator to do something else, the feedback signal from the VCO 112 continues to speed up. Because. To generate a slide-through for reversing the direction of frequency increase of the feedback signal from the VCO 112, the phase of the feedback signal from the VCO 112 proceeds through several phase shifts, thus reversing the direction of the increase. Therefore, it takes time for the nonlinear frequency comparator to generate a new slide-through. The time required for the feedback signal from VCO 112 to proceed to generate a new decision is the time when the last slide-through # 0 is generated at T ₋₁ 558 and the two input signals at T ₀ 552. It is equal to the time that the feedback signal from the VCO 112 passes between when the frequency is synchronized. The phase interval between when the last slide-through # 0 is generated at T ₋₁ 558 and when the frequencies of the two input signals are synchronized at T ₀ 552 is random, and the beat signal from 0 2 π / N of the two input signals at T ₀ 552 to generate a new slide-through to reverse the direction of increasing frequency since slide-through # 0 was last generated at T ₋₁ 558. The feedback signal from the VCO 112 must be advanced during the same interphase period until the other frequencies are synchronized. As a result, the frequency of the feedback signal from VCO is higher than the frequency of the orthogonal reference input signal 110, the frequency of the feedback signal from VCO112 is going on slide-through at _{t =} T A 554, from VCO112 occurring at 556 It continues to rise until the L output for slowing down the frequency of the feedback signal is finally generated by the nonlinear frequency comparator. Due to the inherent loop delay time, the frequency of the feedback signal from the VCO 112 continues to speed up and even after a slide-through is generated at the TA 554 to slow down the frequency of the feedback signal from the VCO 112. . Even after the loop delay time is over, the frequency of the feedback signal from the VCO 112 may continue to be speeded up due to frequency noise uncertainty. As a result, the frequency of the feedback signal from VCO is excessively corrected by the loop delay time, and when t = T A ₅₅₄ last slide through occurs, then when t = T i ₅₆₀ whose frequency is synchronized again The interval between is probably longer than the current phase interval between T ₀ 552 and T _A 554 due to the loop delay time. The same process then repeats in the other direction.

The period of the first frequency oscillation cycle begins when the frequency difference is zero at T ₀ 552, ends when the frequency difference becomes zero again at T ₁ 560, and the oscillation cycle then continues forever. During each frequency oscillation cycle, the frequency of the feedback signal from the VCO 112 is speeded up for about half of that time and slowed down for the remaining half of the time. If the frequency change occurs while the loop delay period is longer than the frequency noise of the nonlinear frequency comparator, the frequency oscillation cycle period can grow when a new frequency oscillation cycle is generated. On the other hand, the duration of the frequency oscillation cycle is stabilized and varies at a specific level.

  As a result, every subsequent phase interval between when the two input frequencies are synchronized and when the last slide-through occurs is a frequency where the loop delay period is greater than or equal to the frequency noise of the nonlinear frequency comparator. If changes, it becomes longer. The growth of the phase interval between when the two input signals are synchronized in frequency and the last slide-through is the phase between when the two input signals are synchronized in frequency and when the last slide-through occurs The interval lasts longer than 2π / N and continues until a phase cycle slip occurs. After a cycle slip occurs, the phase interval between when the two input frequencies are synchronized and when the last slide-through occurs is reset to a very small value, when the two input signals are synchronized in frequency, and finally The process of growing the phase interval between the slide-through is repeated many times before and after the new slide-through. Since the number of slide-throughs that occur in the beat signal is equal to the number of PFDs used in the non-linear frequency comparator, the slide-through moves one after the other while the frequency of the feedback signal from the VCO remains fixed.

  As a result, the decision output 123 of the nonlinear frequency comparator is switched completely randomly, and the frequency of the feedback signal from the VCO 112 of the nonlinear frequency lock loop using the nonlinear frequency comparator is always amplified or reduced at a fixed rate, The frequency of the feedback signal from the VCO 112 is always overcorrected due to the loop delay time, and the frequency of the feedback signal from the VCO 112 changes direction randomly after slide-through occurs.

  Between when the nonlinear frequency comparator decides to generate a new decision signal 123 to correct the frequency of the signal VCO 112 and when a new updated frequency appears at the input of the nonlinear frequency comparator, Since there is always some inherent loop delay time, when the input signal to the nonlinear frequency comparator is finally updated and the nonlinear frequency lock loop is indeed oscillating, the frequency of the signal from the VCO 112 is the reference input frequency 110. Above or below. The vibration frequency of the loop is determined by the delay time before and after the loop, the charge / discharge current from the nonlinear frequency comparator to the loop filter 106, and the time constant of the loop filter 106. The charge / discharge current from the non-linear frequency comparator and the time constant of the loop filter 106 also affect the frequency spreading of the clock signal, particularly when the oscillation frequency of the loop is high. Since the start and end points of each vibration cycle are determined by the frequency noise of the loop, the start and end points of all vibration cycles are different. As a result, the non-linear frequency comparator can provide true broadband spreading for the VCO 108 of the non-linear frequency lock loop. A non-linear frequency lock loop with a non-linear frequency comparator thus becomes a complete spread spectrum clock generator.

  As shown, in all digital frequency comparator designs, a high frequency reference clock is required to generate the quadrature reference signal and further process the reset pulse from the reset pulse module 307. If a high frequency reference clock is not available in the system, one alternative is to use a phase shifter to generate the desired quadrature phase reference. The non-uniform phase between the reference signals generates non-uniform frequency noise and randomly spreads the frequency, so a phase shifter solution should be avoided. Another alternative that does not use a high frequency clock is to use a low frequency signal for frequency comparison instead. In this case, a three-divided period for the reference input signal 110 is used and three orthogonal low frequency reference comparison signals are generated. Here, the three orthogonal low frequency reference comparison signals have 1/3 of the frequency of the feedback signal from the VCO 112 and are compared with the low frequency VCO signal, so that the frequency is 1/3 of the frequency of the reference input signal 110. Have As a result, there is a lot of mechanical delay from the nonlinear frequency comparator. This is because the nonlinear frequency comparator can only generate a new decision output 123 in every three cycles of the reference input signal 110.

  The disadvantage of using a low comparison frequency is obvious because the comparison period becomes too long and the frequency spread of the clock simply exceeds the limit. One solution to this problem is to generate three orthogonal copies of the low frequency VCO from the feedback signal from the VCO 112 as well. Thus, a spread nonlinear frequency comparator for each orthogonal low frequency VCO signal that is compared with each orthogonal reference comparison signal is used. Therefore, in total, nine PFDs are required to obtain a complete design, as shown in FIG. 54 as a seventh supplemental embodiment to the seventh embodiment. As a result, three frequency comparison decision outputs are obtained from each of the three nonlinear frequency comparators. A three bit adder can then be used to add all three decisions from each low frequency comparator making the final decision by majority. As a result, the final frequency determination output 123 can be updated at the same frequency as the initial reference signal 110 and the feedback signal from the VCO 112, but requires three times more hardware to implement this design. .

It is also possible to use an N-divider divider and generate a feedback signal from the VCO 112 from the high frequency feedback signal 400 having a frequency equal to N times the feedback signal from the VCO 112. Here, N is a number greater than 3. As an eighth supplemental embodiment to the seventh embodiment, a high frequency feedback signal 400 can be used to generate N copies of the quadrature feedback signal from the VCO 112, as shown in FIG. Each quadrature feedback signal from the VCO 112 is compared to a high frequency reference comparison signal 261 having a frequency three times that of the reference signal 110 of the nonlinear frequency comparator. This design requires a total of 3 * N PFDs for frequency comparison and generates a final frequency comparison output 123 based on the majority from N decision outputs 123 from N nonlinear frequency comparators. Therefore, an N-bit adder 640 is also required to sum the N decision outputs 123 from each of the N non-linear frequency comparators. The frequency of the high frequency feedback signal from the VCO must be equal to N * F _ref . As the number of N increases, this design has a very unique effect, despite the rapid increase in the number of hardware used. The effect is that each nonlinear frequency comparator can be operated at a low frequency of F _ref 110, while the final decision of the frequency comparison is made at a rate of N * F _ref . This unique design allows a frequency comparison output to be generated rapidly, even when frequency comparison occurs at a slower rate. This design is very useful for frequency locked loop applications where the frequency of the VCO can be switched quickly, even with small frequency steps such as the fractional-N technique used today for phase locked loops It is.

  The number N in the design of the nonlinear frequency comparator 216 shown in FIG. 55 is preferably an odd number. Then, the total of the N-bit adder 640 can be in the range of 0 to N. As a result, the decision threshold for frequency comparison is precisely set to (N + 1) / 2, and there is no ambiguity in frequency decision.

  The nonlinear frequency comparator design using N nonlinear frequency comparators 216, as shown in FIG. 55, is also based on the sum of the N-bit adder 640 instead of generating the digital bipolar decision output 123 from the majority. By generating a linear weighted error output, it can be converted to a linear frequency detector using N nonlinear frequency comparators. There are many possible ways to weight the error output from the N-bit adder 640. For example, a linear weight function for the error output of N-bit adder 640 can be generated. This causes the error output from the linear frequency detector to increase linearly with the sum of the N-bit adder 640. The linear error output from a linear frequency detector using an N nonlinear frequency comparator is then reduced by a fixed constant reference equal to the error output. The error output is generated by a linear frequency detector using an N nonlinear frequency comparator when the sum of the N bit adder 640 is N / 2. The error between the N non-linear frequency comparator and the fixed constant criterion is the desired final linear error output from the linear frequency detector using N non-linear frequency comparators. For this linear frequency detector, a digital complete frequency demodulator, or a fractional frequency synthesizer that always produces an accurate frequency output quickly even at small frequency steps can be built.

In order to build this linear frequency detector using N nonlinear frequency comparators, N must be equal to 2 ^K −1. Then, the sum of the N-bit adder 640 is in the range of 0 to 2 ^K −1 and S ₀ , S ₁ , S ₂ . . . It is expressed in K bits from _SK-1 . Linear weighting function of an N-bit adder 640, and the like ^{2 K-1} taking into taken _{4, S K-1} to 2, _{S 2} taking taking the _{S 0} to 1, _{S 1,} fixed constant ^{criterion, (2} K -1) / 2. Thus, the sum of the N-bit adder 640 produces an output in the range of 0 to 2 ^K −1 and the final linear error output from a linear frequency detector using an N nonlinear frequency comparator is − (2 ^K − 1) / 2 to (2 ^K -1) / 2, and the conversion characteristics of this linear frequency detector using an N nonlinear frequency comparator is 2 ^K -2 separation, evenly spaced ascending steps have a linear ascending slope. Except for replacement, it is similar to the conversion characteristic shown in FIG.

It is very important for a clock frequency spread spread spectrum clock generator to maintain a constant frequency throughout all operating conditions. Unfortunately, the frequency spread of the clock can vary greatly due to many factors, such as manufacturing process variations, temperature and voltage variations. These factors affect the frequency spread of the clock. In order to maintain a constant frequency spread, it is highly desirable to implement an automatic feedback control loop that controls the frequency spread of the spread spectrum clock.

  In order to implement a feedback control loop that controls the frequency spread, a non-linear frequency comparator for providing a feedback signal and means for adjusting the frequency spread are required. Fortunately, you have all the configuration you need for an automatic feedback control loop. For example, a typical non-linear frequency lock loop shown in FIG. 40 can be used, or a non-linear arrival time lock loop with a programmable frequency divider can be used as a spread spectrum clock generator as shown in FIGS. By changing the programmable divider, clock spreading can be easily adjusted. Alternatively, as an output driver for the error comparator, a charge pump having an adjustable output current and controlling clock spreading by changing the charge pump output current can be used. A non-linear frequency comparator is also needed to check if the frequency spread is within limits. If the spread of the clock frequency exceeds the frequency limit within the range of the spread spectrum control cycle, decrease the divide ratio of the programmable divider or from the error comparator to the loop filter to reduce the spread of the frequency Reduce charge and discharge current. If the clock frequency spread is within the frequency spread limits during the entire period of the frequency control cycle, increase the divide ratio of the programmable divider or to the loop filter to amplify the frequency spread Increase the charge / discharge current. Eventually, when the frequency spread of the clock is controlled, the programmable divider is always switched between two numbers, or the current output from the charge pump is constantly switched between the two settings. The spread spectrum control cycle can have a very long period, for example 1 second. The reason is that sometimes it is only necessary to check the result of the frequency limit comparison and adjust the frequency division or charge pump output current. Thus, the step of controlling the frequency spread of the clock does not interfere with the operation of the nonlinear feedback control loop that generates the spread spectrum clock.

Experimental results Experimental circuits were created to demonstrate various techniques for generating spread spectrum clocks. These two methods are most desirable as a spread spectrum clock generator because both a non-linear arrival time locked loop and a non-linear frequency locked loop using the same VCO as the feedback module 105 are easily implemented. A non-linear frequency lock loop is preferred in that it always generates the error output 123 accurately without dead zones, but usually requires more hardware than a non-linear arrival time lock loop, so there is little difference between the above two designs. Absent. Since the nonlinear amplitude lock loop and the nonlinear phase lock loop must be operated at a single frequency unless the nonlinear feedback module 105 is used, and typically generate phase spread instead of frequency spread, Less preferred than design.

  A field programmable gate array 42MX16 from ACTEL was used to provide all logic gates to the circuit. The 42MX16 has two global internal clock buffers to drive all the logic gates and flip-flops to greatly simplify the logic circuit design. A commercially available VCO module, JTOS-1OO, modeled after the mini circuit, was used as the loop feedback module. The VCO can oscillate from 48 to 59 Mhz when adjusted from 0-5V. A 2000 pf bypass capacitor is included inside the VCO module at the VCO tuning input. A schematic diagram of the experimental circuit is as shown in FIG. With the exception of FPGAs and VCOs, only a few components are used in the test circuit. The loop filter is made of a simple RC low-pass filter that does not use OPAMP to provide a bias for the charge pump to reduce component count. Since we are only comparing the performance of different diffusion techniques, a shortcut can be used to use a simple loop filter with no bias. As a result, the VCO can only be operated with a fixed bias of 2.5V to maintain the balance charge / discharge current from the charge pump so that the test frequency is fixed at 53.08 Mhz. .

  The loop filter is made of a 100 kΩ resistor and a 470 pf external capacitor. A 100 kΩ resistor limits the charge pump output to 25 uA. An amplifier made of an inverter is used to amplify the signal from the VCO output to a level with a voltage amplitude between 1 and 4 volts, so that the signal from the VCO output drives the FPGA.

  Six different non-linear comparators are built into the FPGA. 1. An arrival time comparator (A1) shown in FIG. 2. As shown in FIG. 18, the arrival time comparator has a double-ended output (A2). 3. The arrival time comparator shown in FIG. 15 is constituted by an additional digital filter having a 9-bit shift register and generates a decision based on the sum of the 9-bit shift register. It can change the current from the L state to the H state only if the sum is greater than 8, and it can change the current from the H state to the L state only if the sum is less than one. This filter adds at least seven reference comparison clock periods to the loop delay (A3). 4). The frequency comparator is operated at 1/3 of the reference frequency (F1) as shown in FIG. 5). As shown in FIG. 44, the frequency comparator executes at 1/3 of the reference frequency and has the same decision filter as A3 (F2). 6). The frequency comparator uses three low frequency VCO signals to generate the final decision, as shown in FIG.

  VCO frequency spreading was measured in two conditions: low frequency spreading and high frequency spreading. The frequency spread was changed using different fractional periods for the feedback signal path. No other attempt was made to adjust the frequency spread, which was completely determined by the loop delay time.

  The results are as follows.

  1. Low frequency spread. A quadrant divider is used for both the reference signal and the signal from the VCO, and the comparison frequency is currently 13.27 Mhz due to the arrival time lock loop.

  2. High frequency spread. An additional quadrant divider is used for both the reference signal and the signal from the VCO, and the comparison frequency is currently 3.32 Mhz due to the arrival time lock loop.

  From the above results, the arrival time comparator with double-ended output (A2) and the frequency comparator design using 9 PFDs for frequency comparison (F3) are the best of all designs. It is very clear that

  The single-ended mainstay (A1) is not suitable for spreading the clock unless more mechanical delay is added to the loop, for example in the A3 design. The design of A1 simply produces too early and noisy decisions with an uncertain range around the decision threshold.

  Instead of using one frequency comparator, using three frequency comparators can also improve the diffusion loss by 4db when comparing the results from F1 to F3. This is because the frequency spread of a VCO with three frequency comparator designs is generated by three independent frequency noise sources so that the frequency spread is more random and evenly distributed. For designs using three nonlinear frequency comparators, the total noise output is equal to three times the uncorrelated noise output since the noise from each noise source is uncorrelated. Except for designs that use only one nonlinear frequency comparator, the total noise output is always equal to three times the correlated noise output so that it is always high.

  A spread spectrum clock using a non-linear arrival time lock loop and a frequency lock loop can generate a clock with a large spread loss equivalent to 30 db or more 45 db better than current technology with triangle modulation. The reason why the diffusion loss can be so high is that the clock is not usually limited to one frequency or phase, and the amplitude, period and phase of the modulation signal of the final error correction output 115 with respect to the VCO are random. Every modulation cycle of the non-linear arrival time lock loop is different. A full modulation cycle begins with a random frequency with a random phase and ends with a random frequency with another random phase. As a result, the radiated clock energy can only be measured with a video filter having a small bandwidth as low as 300 Hz. For a conventional spread spectrum clock with triangular modulation, it is sufficient to store the modulated signal, so a video filter with a bandwidth of 100 Khz is usually used. Without a spread spectrum clock generator that uses a non-linear feedback control loop, the spectrum is too thin and nothing is stored in the video filter with a small time constant of 100 Khz. A video filter with a small bandwidth is the only way to measure the average power of the radiated clock signal.

  When the frequency spread is large, the modulation frequency of the spread spectrum clock is reduced by 10 Khz. Traditionally, the modulation frequency of the spread spectrum clock is chosen to be higher than 30 Khz so that the frequency of the modulation signal is outside the audible range. Because the modulation signal of the nonlinear feedback control loop is now random noise, instead of a signal with a fixed frequency, the noisy modulation signal behaves like normal noise in the audible range, so it is in the audible range But there is no noticeable effect.

  When the frequency spread is large, the clock spread is most effective and the cycle slip for the signal from the VCO can be easily generated. The frequency spread needs to exceed at least 3% in order to reduce the clock energy below -40db. Although small spreads do not have enough time to cause cycle slips, the clock energy is still concentrated, although much better than current technology. This is a problem for applications that require a small frequency spread, eg, only 0.5% frequency spread. In order to generate such a small frequency spread request with effective random spread, some additional work needs to be done.

One way to provide effective random spread to a small frequency spread clock signal is to first use a frequency mixer that produces a high frequency clock signal with a higher percentage of frequency spread and then shown in FIG. In order to produce an output having a desired clock frequency with a desired frequency spread, a divider is used to divide the high frequency clock signal into smaller parts. First, generate a low frequency clock signal F _out with a frequency spread of Δf and a high frequency clock signal that has no frequency spread but has a frequency equal to N−1 times the desired low frequency clock signal F _out 109. When using a frequency mixer 612 to mix these two signals, extract a high frequency clock signal N times the frequency of the desired low frequency clock signal with Δf frequency spread from the output of the mixer it can. Then, an N-divided divider 616 can be used to generate a clock having the desired frequency F _out 109, and the desired clock frequency spread is only Δf / N. If the initial spreading loss for a low frequency clock with 5% frequency spreading is -45db and N = 10 is selected, the desired clock spreading loss with 0.5% spreading will be -35db, Is still higher than the diffusion loss produced by current technology. This method requires a lot of hardware, but it does not give a low spreading clock with good spreading loss.

  Another way to increase spread loss for spread spectrum clocks with small frequency spread is to artificially add cycle slip. As described above, since the spread modulation signal of the final error correction output signal 115 can be reset, the amplitude, frequency and phase of the modulation signal on the final error correction output 115 are completely random. For a spread spectrum clock generator with a small frequency spread, the amplitude of the modulation signal of the final error correction output signal 115 varies within a small range because the spreading of the final error correction output signal 115 is not long enough to generate a cycle slip. As much as possible, the diffusion loss is small. Fortunately, by utilizing the fact that the polarity of the closed loop gain is irrelevant when the non-linear feedback control loops 116 and 120 are actuated in the oscillation phase 564, cycle slip is artificially induced in the spread spectrum clock generator. Can be added to. Since the polarity of the closed loop gain is irrelevant, the nonlinear feedback control loops 116 and 120 can still vibrate if the polarity of the decision output signal 123 is reversed. Reversing the polarity of the decision output signal 123 can produce many short frequency spreads in the spread spectrum clock generator when it occurs asynchronously and randomly in the spread modulation signal of the final error correction output 115. This is similar to short frequency spreading caused by resetting the modulation signal on the final error correction signal 115. Reversing the polarity of the decision output signal 123 is substantially reversing the direction for generating the spread modulation waveform of the final error correction output 115 towards the feedback module 105. As a result, the amplitude of the modulation signal of the final error correction signal 115 is random between zero and the peak of the spread modulation signal of the final error correction output 115, and the frequency and phase of the spread modulation wave of the final error correction output 115 Since both are random, the diffusion loss is greatly increased. 58 and 59 are block diagrams of a spread spectrum clock generator using a non-linear feedback control loop with a random polarity that switches to a decision output signal 123 that produces an artificial cycle slip that increases spreading loss. In these block diagrams, as the final decision output signal 604 driving the forward module 163, the single pole-double throw switch 600 is used to select one of the normal decision output signal 123 or the reversed decision output signal. Is done. The operation of the switch 600 and the state of the final determined output 604 are determined by the state of the output signal from the random chip generator 602. The random chip generator 602 generates a series of digital signals that randomly switch between the H and L states. The switch 600 selects the normal decision output 123 as the final decision output 604 when the output signal from the random chip generator 602 is L, and reverses when the output signal from the random chip generator 602 is H. The determined output is selected as the final determined output 604. For longer than the period from the spread modulated signal of the final error correction output 115 to the feedback module 105, the switch 600 typically stays at one of the H or L levels.

  Techniques for artificially adding cycle slips to spread spectrum clock generators using non-linear feedback control loops 606 and 608, as shown in FIGS. 58 and 59, can be achieved using other techniques that increase spread loss. The present invention can be similarly applied to a spread spectrum clock generator. One technique that can easily benefit from this technique is the use of a look-up table to spread the clock. In this technique, the amount of frequency spreading for a clock is determined by a formula stored in a look-up table, which in turn orders the formulas stored in a table that generates the desired spread modulation signal for adjusting the VCO. The spread modulated signal to the VCO is usually a repetitive deterministic signal. Even with iterative deterministic signals, cycle slips can be added by randomly reversing the direction of clocking out the formula stored in the lookup table, so that the diffusion stored in the lookup table Reversing the direction of the clock signal for clocking out the modulation signal creates a lot of frequency spreading and makes the amplitude, frequency and phase of the deterministic modulation signal random. As a result, the amplitude of the spread modulation signal in the final error correction output 115 is random between zero and the peak of the repetitive deterministic spread modulation signal, and the frequency and phase of the spread modulation waveform is also random, thus spreading loss. Is greatly increased.

  In order to generate the spread modulation function of the final error correction output 115, the feedback module 105 of the spread spectrum clock generator randomly reverses the direction to the spread modulation signal on the final error correction output 115 to the feedback module 105. This is an effective method for generating random spread to increase the spread loss of the spread spectrum clock generator, regardless of whether it is random or deterministic.

Comparing the results of F1 and F3, it is quite obvious that using more frequency comparators can improve the spreading loss. Theoretically, the spreading loss can be further improved as more frequency comparators are used. The improvement in diffusion loss must be proportional to log ₁₀ (N), where N is the number of nonlinear frequency comparators used for the final fully nonlinear frequency comparator 216. Thus, the design shown in FIG. 55 requires more hardware but is the best design for the nonlinear frequency comparator 216. In this design, the final decision output 123 is a binary output based on a majority vote from the outputs of N nonlinear frequency comparators.

  In the field of general electronic equipment such as PCs, laptops, printers, digital cameras and mobile phones, even while providing sufficient spreading to accept FCC requirements for false emissions from the clock and its harmonics There is a great demand for stable clocks with only a certain amount of frequency spreading. These products benefit greatly from the present invention by providing low-priced products to the market in less time.

FIG. 2 is a diagram showing general clock spreading with triangular modulation signal and random broadband noise (prior art). FIG. 3 is a diagram showing components of a linear feedback control loop. It is a figure which shows the conversion characteristic of the last error correction output of a linear feedback control loop. It is a block diagram which shows the conventional linear feedback control loop (prior art). FIG. 6 is a block diagram showing a nonlinear feedback control loop using a nonlinear error comparator as a preferred embodiment of the spread spectrum clock generator. FIG. 5 is a block diagram illustrating a nonlinear feedback control loop using an amplifier with a linear error detector and infinite gain as another embodiment of a spread spectrum clock generator. It is a figure which shows the conversion characteristic of the last error correction output of a nonlinear feedback control loop. It is a figure which shows the acquisition operation | movement (acquisition behavior) of a primary nonlinear feedback control loop. It is a figure which shows the conversion characteristic of the gain of a nonlinear feedback control loop. 1 is a block diagram of a basic spread spectrum clock generator using a nonlinear amplitude lock loop having a nonlinear amplitude comparator as a first embodiment. FIG. FIG. 4 is a block diagram of a spread spectrum clock generator using a basic nonlinear arrival time lock loop having a nonlinear arrival time comparator as a second embodiment. FIG. 9 is a block diagram of a spread spectrum clock generator using a basic nonlinear arrival time lock loop having a linear arrival time detector and an amplifier with infinite gain as a third embodiment. 1 is a diagram illustrating a general spread spectrum clock generator using a non-linear arrival time lock loop with a non-linear arrival time comparator and a frequency divider. FIG. 1 is a diagram illustrating a general spread spectrum clock generator using a non-linear arrival time lock loop with a linear arrival time detector and a frequency divider. FIG. It is a figure which shows a specific nonlinear arrival time comparator as 1st supplementary embodiment with respect to 2nd Embodiment. It is a figure which shows the nonlinear arrival time comparator simplified as 2nd supplement embodiment with respect to 2nd Embodiment. It is a figure which shows the conversion characteristic of the last error correction output from what is shown in FIG. It is a systematic diagram of an accurate nonlinear arrival time comparator with a dead zone as a third supplemental embodiment for the second embodiment. It is a figure which shows acquisition operation | movement of a secondary arrival time lock loop. It is a systematic diagram of the linear arrival time detector with a dead zone as 1st supplementary embodiment with respect to 3rd Embodiment. It is a systematic diagram of the general linear arrival time detector without a dead zone as 2nd supplementary embodiment with respect to 3rd Embodiment. FIG. 6 is a systematic diagram of a linear arrival time detector using a single-ended charge pump output driver with a dead zone as a third supplemental embodiment to the third embodiment. FIG. 10 is a system diagram of a linear arrival time detector using a single-ended charge pump output driver without a dead zone as a fourth supplemental embodiment with respect to the third embodiment. FIG. 10 is a block diagram of a spread spectrum clock generator using a nonlinear phase-locked loop having a linear phase detector and an amplifier with infinite gain as a fourth embodiment. It is a figure which shows the exclusive OR (EXOR) gate as a linear phase detector. It is a figure which shows the conversion characteristic of the exclusive OR gate as a linear phase detector. It is a figure which shows a general digital linear phase detector as 1st supplementary embodiment with respect to 4th Embodiment. FIG. 28 is a timing diagram of the digital linear phase detector shown in FIG. 27. It is a figure which shows the conversion characteristic of the digital linear phase detector shown in FIG. It is a block diagram of the spread spectrum clock generator which uses a nonlinear phase lock loop with a nonlinear phase comparator as a 5th embodiment. It is a systematic diagram of the nonlinear phase comparator using a nonlinear arrival time comparator as supplementary embodiment with respect to 5th Embodiment. It is a figure which shows the nonlinear arrival time comparator using the nonlinear phase comparator shown in FIG. FIG. 6 is a timing diagram for a reset clock of a nonlinear phase comparator. It is a systematic diagram which shows the linear phase detector which uses an arrival time comparator as 2nd supplementary embodiment with respect to 4th Embodiment. FIG. 10 is a block diagram of a spread spectrum clock generator using a nonlinear frequency lock loop having a linear frequency detector and an amplifier with infinite gain as a sixth embodiment. FIG. 10 is a block diagram of a spread spectrum clock generator using a nonlinear frequency lock loop having a nonlinear frequency comparator as a seventh embodiment. It is a figure which shows the output characteristic of a linear frequency detector. It is a systematic diagram of a current frequency detector (prior art). FIG. 39 is a timing diagram of the current frequency detector shown in FIG. 38. 1 is a diagram illustrating a spread spectrum clock generator using a general nonlinear frequency lock loop with a frequency comparator and frequency divider. FIG. 1 is a system diagram of a basic phase-frequency detector with a charge pump output driver (prior art). FIG. 42 is a timing diagram of basic PFD shown in FIG. 41. It is a systematic diagram of the nonlinear frequency comparator which uses two PFD as 1st supplementary embodiment with respect to 7th Embodiment. It is a systematic diagram of the nonlinear frequency comparator which uses three PFDs with a shift register and an adder as a 2nd supplement embodiment with respect to 7th Embodiment. It is a typical one-shot system diagram (prior art). It is a systematic diagram of the nonlinear frequency comparator which uses a state machine as a determination module as 3rd supplementary embodiment with respect to 7th Embodiment. FIG. 47 is a diagram illustrating an algorithm for designing the state machine of FIG. 46. It is a systematic diagram of the nonlinear frequency comparator using the frequency determination module with a saturation counter as 4th supplementary embodiment with respect to 7th Embodiment. FIG. 3 is a block diagram of a frequency determination module that uses two saturation counters. FIG. 10 is a system diagram of a nonlinear frequency comparator using four PFDs with a shift register and an adder as a fifth supplementary embodiment with respect to the seventh embodiment. FIG. 16 is a system diagram of a nonlinear frequency comparator using a shift register, an adder, and four PFDs with compression one-shot as a sixth supplemental embodiment with respect to the seventh embodiment. It is a systematic diagram of a circuit that generates a compressed one-shot output. It is a figure which shows the acquisition operation | movement of a nonlinear frequency lock loop. It is a block diagram which shows the complete nonlinear frequency comparator using three nonlinear frequency comparators as 7th supplementary embodiment with respect to 7th Embodiment. It is a block diagram which shows the high-speed nonlinear frequency comparator by using N nonlinear frequency comparator as 8th supplemental embodiment with respect to 7th Embodiment. It is a systematic diagram of a test board. FIG. 6 is a block diagram illustrating improving clock spreading loss with small frequency spreading by using a frequency mixer and divider. FIG. 3 is a block diagram illustrating improving the spreading loss of a spread spectrum clock signal generated from a non-linear feedback control loop using a non-linear comparator with small frequency spread by adding artificial cycle slip. FIG. 3 is a block diagram illustrating improving the spreading loss of a spread spectrum clock signal generated from a non-linear feedback control loop using an amplifier with infinite gain with a small frequency spread by adding an artificial cycle slip.

Explanation of symbols

100, 116, 120 feedback control loop,
101 error detector,
102 diffusion loss,
103 difference block,
104 feedback control loop,
105 feedback module,
106 loop filter,
107 gain block,
109 Spread spectrum clock output,
110 reference signal,
111 divider,
112 feedback output,
113 open loop gain,
114 Error input,
115 error correction signal,
117 error output,
118 error comparator,
119 flip-flop,
122 flip-flops,
123 digital decision output,
124 flip-flops,
125 reference voltage,
126 AND gate,
127 sourcing charge pump,
128 reset signal,
129 sinking charge pump,
130 Amplifier with infinite gain,
131 amplitude limiting amplifier,
135 spread spectrum clock generator,
136 AND logic gate,
137 feedback module,
138 OR logic gate,
139 Amplitude comparator,
140 OR logic gate,
141 AND logic gate,
142 polarity selection module,
144 polarity determination output,
145 exclusive OR gate,
146 single-ended charge pump,
148 Nonlinear arrival time comparator,
149 charge pump at both ends,
150 spread spectrum clock generator,
151 Nonlinear arrival time lock loop,
152 spread spectrum clock generator,
155 linear arrival time detector,
156 output latch,
158 delay buffer,
159 decision flip-flop,
160 uncertainty window,
161 Diffusion loss,
163 Forward module,
166 nonlinear phase-locked loop,
169 Nonlinear arrival time comparator,
170 analog linear phase detector,
170 linear phase detector,
171 nonlinear phase-locked loop,
172 variable delay circuit,
172 linear variable delay circuit,
174 Digital,
174 digital linear phase detector,
176 nonlinear phase comparator,
178 linear phase detector,
180 linear arrival time detector,
181 decision output latch,
182 arrival time detector,
183 polarity latch output,
184 sampling clock,
187 phase detector output,
188 averaging capacitor,
189 arrival time comparator,
190 Arrival time comparator,
192 odd clock,
194 digital linear frequency detector,
196 Nonlinear frequency lock loop,
199 even clock,
200 digital frequency comparator,
208 digital frequency comparator,
213 spread spectrum clock generator,
214 spread spectrum clock generator,
216 nonlinear frequency comparator,
219 flip-flop,
220 nonlinear frequency comparator,
221 flip-flop,
222 Trigger signal,
223 beat signal,
224 one shot,
226 shift register,
228 adder,
230 control,
231 bit shift register,
232 modules,
233 bit adder,
234 modules,
237 multiplexer,
239 latch,
250 enable signal,
256 inputs,
258 reset output signal,
260 divider,
261 reference clock signal,
262 one shot,
H.264 output latch,
305 orthogonal module,
307 reset module,
309 decision circuit,
316 flip-flop,
320 divider,
330 state machine,
400 high frequency feedback signal,
404 output,
406 counter,
408 enable output signal,
410 shift register,
430 decision module,
542 cycle slip phase,
542 acquisition phase,
564 vibration phase,
564 vibration phase,
600 switches,
600 double throw switch,
602 random chip generator,
604 decision output,
606 a non-linear feedback control loop;
612 frequency mixer,
616 Divider,
640 bit adder.

Claims (11)

A non-linear error comparator (118) having a first input terminal and receiving a reference signal (110) at the first input terminal;
A feedback control loop (116) having an input terminal coupled to the output terminal of the nonlinear error comparator (118);
An output terminal of the feedback control loop (116) coupled to a second input terminal of the nonlinear error comparator (118);
Have
The non-linear error comparator (118) generates a feedback signal output from the output terminal of the feedback control loop (116) that randomly vibrates around a reference signal (110). Thus, a spread spectrum clock signal generator that generates an infinite closed-loop gain.   The spread spectrum clock signal generator of claim 1, wherein the non-linear error comparator (118) includes a non-linear frequency comparator (200). The non-linear error comparator (118)
Comparing the reference signal (110) provided at a first input terminal of the nonlinear error comparator (118) with a signal (112) received at a second input terminal of the nonlinear error comparator (118); A difference block (103) that generates an error input value (114) based on the result of the comparison;
Regardless of the value of the error input value (114), the gain for receiving the error input value (114) and generating the bipolar digital decision output (123) at the output terminal of the nonlinear error comparator (118) Block (107);
The spread spectrum clock signal generator according to claim 1, further comprising: The nonlinear frequency comparator (200) includes:
An orthogonal module (305) having an output for outputting the reference signal (110);
A reset pulse module (307) coupled to receive the reference input signal (110);
A decision module (309) coupled to the reset pulse module and outputting the bipolar decision output (123);
The spread spectrum clock signal generator according to claim 3.   The reset pulse module (307) includes three phase frequency modules (PFD), and each phase frequency module (PFD) receives one of three quadrature reference signals (110) offset by 120 degrees. 5. A spread spectrum clock signal generator as claimed in claim 4, further comprising an output coupled to an OR gate (256), wherein the OR gate (256) outputs a final reset signal (258) to the decision module (309). apparatus. Providing a reference signal (110) to a first input terminal of the nonlinear error comparator (118);
Coupling an input terminal of a feedback control loop (116) to an output terminal of the nonlinear error comparator (118);
Coupling an output terminal of the feedback control loop (116) to a second input terminal of the nonlinear error comparator (118);
An infinite closed loop gain is generated in the feedback control loop (116), and as a result, a feedback signal output from the output terminal of the feedback control loop (116) that oscillates randomly around the reference input signal (110). Generating a vibration such that the feedback control loop (116) generates;
A spread spectrum clock signal generation method comprising: Generating an infinite closed-loop gain in the feedback control loop (116);
Comparing the reference signal (110) provided at a first input terminal of the nonlinear error comparator (118) with a signal (112) received at a second input terminal of the nonlinear error comparator (118); Generating an error input value (114) based on the result of the comparison;
Generating the bipolar digital decision output (123) at the output terminal of the nonlinear error comparator (118) regardless of the value of the error input value (114);
The spread spectrum clock signal generation method according to claim 6. The non-linear error comparator (118)
8. A spread spectrum clock signal generation method according to claim 7, comprising a non-linear frequency comparator (200). The non-linear error comparator (118)
Comparing the reference signal (110) provided at a first input terminal of the nonlinear error comparator (118) with a signal (112) received at a second input terminal of the nonlinear error comparator (118); A difference block (103) that generates an error input value (114) based on the result of the comparison;
Regardless of the value of the error input value (114), the gain for receiving the error input value (114) and generating the bipolar digital decision output (123) at the output terminal of the nonlinear error comparator (118) Block (107);
The spread spectrum clock signal generation method according to claim 8. The nonlinear frequency comparator (200) includes:
An orthogonal module (305) having an output for outputting the reference signal (110);
A reset pulse module (307) coupled to receive the reference input signal (110);
A decision module (309) coupled to the reset pulse module and outputting the bipolar decision output (123);
10. The spread spectrum clock signal generation method according to claim 9, further comprising:   The reset pulse module (307) includes three phase frequency modules (PFD), and each phase frequency module (PFD) receives one of three quadrature reference signals (110) offset by 120 degrees. 11. The spread spectrum clock signal generation of claim 10, comprising an output coupled to an OR gate (256), wherein the OR gate (256) outputs a final reset signal (258) to the decision module (309). Method.

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