JPH1174787A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase locked loop circuit capable of reducing the number of connecting lines between LSIs without deteriorating characteristics. SOLUTION: The phase locked loop circuit in which a phase error detector 2 to be digitally processed, a VCO(voltage controlled oscillator) 6 to be processed by analog and a loop filter 5 are constituted by separate LSIs is provided with a compression means 3 to reduce bit width of information by inputting outputted information of the phase error detector 2 and processing the information in an area with large phase difference and a non-liner D/A conversion means 4 to output extended voltage in the area in which a value of phase error information is large. And since the bit width of the phase error information is compressed and outputted by the compression means 3, the number of the connecting lines between the LSIs is reduced. In addition, since the area in which the value of the error information is large is extended and outputted in the D/A converter 4 in an analog processing part, time required for lock-in is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (PLL) circuit, and more particularly to a PLL circuit capable of reducing the number of connection lines between LSIs without deteriorating characteristics. is there.

[0002]

2. Description of the Related Art Conventionally, a PLL circuit has been used to generate a clock signal from a reproduction signal read by a head of a hard disk device, for example. FIG. 7 is a block diagram showing a configuration example of a conventional PLL circuit. The reproduction signal Vin and the output signal Vosc of the VCO (voltage controlled oscillator) 14 are each converted into, for example, 6-bit digital data by the A / D converter 10 and input to the phase error detector 11.

FIG. 8 is a graph showing output characteristics of a conventional phase error detector 11. The phase error detector 11 outputs a phase error information code P corresponding to the phase difference between the two input signals.
E is output. The phase error information code PE is, for example, digital data having a range of ± 63 as shown in FIG.
It is represented by a 7-bit code including the sign bit. Linear D /
The A converter 12 is a linear D / A converter, and corresponds to the output code of the phase error detector 11, for example, the maximum value “6”
8 corresponding to the maximum output voltage (full scale) value (see FIG. 8).
In, the full scale value is set to 1.0. ) Is output. The output signal of the linear D / A converter 12 is input to the VCO 14 via the loop filter 13, and the oscillation frequency of the VCO 14 is controlled according to the phase error. And VCO
14 outputs a reproduced clock signal Vosc.

[0004]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
In the circuit, when the phase is locked,
The absolute value of the phase error is small, and 5 bits is sufficient as the absolute value of the phase error information. However, if the lock is released, 6 bits or more are required as an absolute value in order to quickly lock in.

[0005] Here, when the digital processing part and the analog processing part of the PLL circuit are respectively constituted by separate LSIs, it is necessary to exchange phase error information between the two LSIs. However, in the conventional PLL circuit, since 7 bits including the sign bit are required as the phase error information, it is necessary to secure the number of pins of the LSI correspondingly. Therefore, there has been a problem that miniaturization becomes difficult and the manufacturing cost increases. SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase locked loop circuit which solves the above-mentioned problems of the prior art and can reduce the number of connection lines between LSIs without deteriorating characteristics.

[0006]

SUMMARY OF THE INVENTION The present invention comprises a digitally processed phase error detector and an analogly processed VCO.
And a phase-locked loop circuit provided with a loop filter, receiving the output information of the phase error detector and processing information in a region having a large phase error to reduce the bit width of the information. Input the output information, and in the area where the value of the phase error information is large,
A non-linear D / A converter for outputting an expanded voltage.

In the case of a PLL circuit in which the analog processing section and the digital processing section are formed by separate LSIs, the phase error information is converted from the digital processing LSI to the analog processing LS.
However, in the present invention, since the bit width of the phase error information is compressed and output by the compression means, the number of connection lines between LSIs is reduced. Further, since the D / A converter in the analog processing section expands and outputs a region where the value of the error information is large, the time required for lock-in is reduced.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PLL circuit to which the present invention is applied. For example, the reproduced signal Vin and the output signal Vosc of the VCO 6 read by the head of the hard disk device are output from the A / D converter 1
Are converted into, for example, 6-bit digital data, and input to the phase error detector 2.

The phase error detector 2 outputs a phase error information code PE corresponding to the phase difference between the two input signals.
The phase error information code PE is, for example, digital data having a range of ± 63, and is represented by a 7-bit code including a sign bit. Note that various configurations of the phase error detector have been proposed, and any type can be adopted. The clip circuit 3 is a circuit that compresses the bit width by clipping the phase error information.

FIG. 2 is a graph showing an example of the characteristics of the clip circuit 3. For example, as shown in FIG. 2, the clip circuit 3 outputs the input value as it is when the input phase error information is in the range of ± 31, and converts it to ± 31 when the input phase error information is in the range of ± 32 to ± 63. (Clip) and output. Such a circuit can be easily realized by a logic gate circuit. The range of the output data value of the clip circuit 3 is ± 31, and can be represented by 6 bits including the sign.

The nonlinear D / A converter 4 is a nonlinear D / A converter for converting the compressed phase error information into an analog signal. FIG. 3 is a graph illustrating a characteristic example of the nonlinear D / A converter 4. Note that the vertical axis of FIG. 3 indicates a relative output voltage value when the full scale of the output voltage of the D / A converter is set to 1.0.

As shown in FIG. 3, when the input data is within the range of ± 30, the nonlinear D / A converter 4 outputs a voltage corresponding to the linearity. However, if the input data is ± 31
, The corresponding value is 0.5 if linear.
Instead, it outputs an extended voltage of 0.75.

The loop filter 5 and the VCO 6 are PLL
It is a well-known loop filter circuit and VCO in the circuit. An output signal of the non-linear D / A converter 4 is input to a VCO 6 which is a voltage controlled oscillation circuit via a loop filter 5, and the oscillation frequency of the VCO 6 is controlled. And VC
A reproduction clock signal Vosc is output from O6.

FIG. 4 is a graph showing the output voltage characteristic of the D / A converter 4 with respect to the phase error in the embodiment. As shown in FIG. 4, when the absolute value of the phase error is within 90 degrees, a voltage corresponding to linearity is output as in the conventional PLL circuit. However, the absolute value of the phase error is 90 degrees to 18
In the range of 0 degrees, a constant value of 0.75 is output. The value of 0.75 is, for example, an average value of the output voltages in the above range, but is not limited to this value, and any value larger than 0.5 can be selected. As a result, when the phase error is at least in the vicinity of 90 degrees in the region larger than 90 degrees, a larger phase error voltage is generated than in the conventional case, and lock-in is faster.

The PLL circuit of the present invention has a digital processing analog circuit and an analog processing LSI with the above-described configuration and operation without causing the lock-in characteristic of the PLL circuit to deteriorate or locking in at a higher speed.
Can be reduced in the number of connection lines.

FIG. 5 is a graph showing the relationship between the phase error and the code according to the second embodiment. In the first embodiment, an example in which the output of the phase error detector 2 is compressed by the clipping circuit 3 is disclosed.
A non-linear code converter whose characteristics are shown in FIG. 6 may be used. This code converter converts, for example, phase error information PE represented by ± 63 into ± 31 codes, and can be realized by using a ROM or the like. By using such a code converter, it is possible to arbitrarily set the lock-in characteristics and the like of the PLL simultaneously with the compression of the bit width.

FIG. 6 is a graph showing the characteristics of the code expander according to the third embodiment. In the first and second embodiments, for example, an example is shown in which a non-linear D / A converter 4 as shown in FIG. 3 is used, but a code decompressor ( Code converter) and a linear D / A converter. The code expander expands, for example, a code of ± 31 to ± 63 with characteristics as shown in FIG. Then, for example, it is converted into an analog signal by a 7-bit linear D / A converter. With such a configuration, a conventional linear D / A converter can be used, and the PLL characteristics can be arbitrarily set.

[0018]

As described above, the PL in which the analog processing section and the digital processing section are constituted by separate LSIs.
In the case of the L circuit, the phase error information is
However, in the present invention, since the bit width of the phase error information is compressed and output by the compression means, the number of connection lines between the LSIs is reduced. Also, D / in the analog processing unit
Since the area where the value of the error information is large is expanded and output in the A-converter, the time required for lock-in is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit to which the present invention is applied.

FIG. 2 is a graph showing a characteristic example of a clip circuit 3;

FIG. 3 is a graph showing a characteristic example of the nonlinear D / A converter 4.

FIG. 4 is a graph showing an output voltage characteristic of the D / A converter 4 with respect to a phase error in the example.

FIG. 5 is a graph showing a relationship between a phase error and a code according to the second embodiment.

FIG. 6 is a graph showing characteristics of a code decompressor according to the third embodiment.

FIG. 7 is a block diagram illustrating a configuration example of a conventional PLL circuit.

FIG. 8 is a graph showing output characteristics of a conventional phase error detector 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... A / D converter, 2 ... Phase error detector, 3 ... Clip circuit, 4 ... Non-linear D / A converter, 5 ... Loop filter,
6 VCO, 10 A / D converter, 11 Phase error detector, 12 Linear D / A converter, 13 Loop filter,
14 ... VCO

Claims (3)

[Claims] 1. A phase locked loop circuit comprising a digitally processed phase error detector and an analog processed VCO and a loop filter, wherein input information of the phase error detector is input and information of a region having a large phase error is input. A compression means for reducing the bit width of the information by processing; and a non-linear D which inputs the output information of the compression means and outputs an expanded voltage in a region where the value of the phase error information is large.
/ A conversion means. 2. The phase-locked loop circuit according to claim 1, wherein the part to be digitally processed and the part to be subjected to analog processing are constituted by different LSIs. 3. The clipping means is a clipping circuit for converting all absolute values of phase error information having an absolute value of 2 n or more to [2 n -1] when n is an arbitrary natural number. The nonlinear D / A converter outputs an expanded voltage when the absolute value of the input phase error information is [2 n -1]. Phase locked loop circuit