JP3942475B2 - Clock recovery circuit and data receiving circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for performing high-speed signal transmission between a plurality of LSI chips or between a plurality of elements or circuit blocks in one chip, or between a plurality of boards or a plurality of enclosures. In particular, the present invention relates to a clock restoration circuit and a data reception circuit using a feedback loop type clock signal generation circuit.
[0002]
In recent years, the performance of components constituting computers and other information processing devices has greatly improved. For example, semiconductor storage devices such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), processors, The improvement in performance of switch LSIs is remarkable. As the performance of the semiconductor memory device, processor, etc. is improved, the performance of the system cannot be improved unless the signal transmission speed between components or elements is improved. Specifically, for example, a speed gap between a storage device (memory) such as SRAM or DRAM and a processor (between LSIs) tends to increase more and more. In recent years, this speed gap has hindered improvement in the performance of the entire computer. It is becoming. Further, due to the high integration and enlargement of semiconductor chips, the signal transmission speed between elements and circuit blocks in the chip has become a major factor limiting the performance of the chip. Furthermore, the signal transmission speed between the peripheral device and the processor / chipset is also a factor that limits the performance of the entire system.
[0003]
By the way, in general, a clock for determining “0” and “1” of data is generated (restored) on the receiving circuit side in high-speed signal transmission between circuit blocks, between chips, or in a housing. ing. This restored clock is adjusted by a feedback circuit in the circuit so as to be within a certain phase range with respect to the received data so that correct signal reception is always performed. This recovery of the clock and determination of data using the recovered clock is called CDR (Clock and Data Recovery). This CDR is the most important element for high-speed data reception, and various methods are being studied. There is a strong demand to provide a data receiving circuit (clock recovery circuit) capable of high-speed and accurate signal transmission using CDR.
[0004]
[Prior art]
In recent years, it is necessary to increase the signal transmission speed per pin in order to cope with an increase in the amount of data transmission between LSIs and boards or between enclosures. This is also to avoid an increase in the cost of the package and the like due to an increase in the number of pins. As a result, recently, the signal transmission speed between LSIs exceeds 2.5 Gbps, and an extremely high value (high-speed signal transmission) such as 10 Gbps or higher is required.
[0005]
For example, in order to increase the speed of signal transmission between LSIs, it is necessary for the receiving circuit to operate at a somewhat accurate timing (data detection and determination) with respect to the transmitted signal. 2. Description of the Related Art Conventionally, in order to generate a clock (internal clock) having such a timing, a method of providing a clock recovery circuit (CDR) using a feedback loop type clock signal generation circuit in a signal reception circuit is known.
[0006]
That is, in order to realize the CDR, a feedback circuit is used that generates an internal clock for receiving data, compares the phase of the internal clock with the data, and adjusts the phase of the internal clock based on the phase comparison result. It is done.
[0007]
FIG. 1 is a block diagram showing an example of a conventional data receiving circuit, which is configured as a 4-way × 2 type interleave circuit using CDR. FIG. 2 is a diagram showing the timing of each signal in the data receiving circuit of FIG.
[0008]
In FIG. 1, reference numerals 110 to 113 are data determination units (data determination flip-flops), 120 to 123 are boundary detection units (boundary detection flip-flops), and 131 and 132 are data and boundary conversion circuits. Show. Reference numeral 141 is a data determination clock generation circuit, 142 is a boundary detection clock generation circuit, 105 is a phase difference digital code conversion circuit (PDC), and 106 is a digital filter. Further, reference numeral DIL indicates a data input line, DCL indicates a data determination clock line, BCL indicates a boundary detection clock line, and DFL and BFL indicate data and boundary feedback lines.
[0009]
As shown in FIG. 1, the conventional data receiving circuit connects, for example, a data input line DIL for transmitting 10 Gbps data to inputs of four data determination units 110 to 113 and four boundary detection units 120 to 123. , Each is captured with a corresponding 2.5 GHz clock.
[0010]
That is, as shown in FIGS. 1 and 2, the data determination units 110 to 113 each have a phase difference of 90 ° at 2.5 GHz that is the output of the data determination clock generation circuit 141 (for example, 45 ° and 135 °). Four-phase clocks CLKd0 to CLKd3 (with phases of °, 225 °, and 315 °) are supplied, and input data is taken in at phase timings of 45 °, 135 °, 225 °, and 315 °, respectively, and received data DT0 to DT3 are converted. It outputs to 131. The conversion circuit 131 converts 4-bit received data DT0 to DT3 synchronized with a 2.5 GHz clock into 32-bit data (DT [31: 0]) synchronized with a 312.5 MHz clock, and performs phase difference digital code conversion. The received data (DT [31: 0]) is output to the circuit (internal circuit) at the next stage while being output to the circuit 105.
[0011]
Further, the boundary detection units 120 to 123 each have a phase difference of 90 ° at 2.5 GHz that is the output of the boundary detection clock generation circuit 142 (for example, phases of 0 °, 90 °, 180 °, and 270 °). Four-phase clocks CLKb0 to CLKb3 are supplied, and the boundary of input data is detected at phase timings of 0 °, 90 °, 180 °, and 270 °, respectively, and boundary detection data BT0 to BT3 are output to the conversion circuit 132. The conversion circuit 132 converts the 4-bit boundary detection data BT0 to BT3 synchronized with the 2.5 GHz clock into 32-bit data (BT [31: 0]) synchronized with the 312.5 MHz clock to convert the phase difference digital code. Output to the conversion circuit 105. Here, the four-phase clocks CLKd0 to CLKd3 that are outputs of the data determination clock generation circuit 141 and the four-phase clocks CLKb0 to CLKb3 that are outputs of the boundary detection clock generation circuit 142 each have a phase difference of 45 °. .
[0012]
The phase difference digital code conversion circuit 105 compares the input received data DT [31: 0] and the boundary detection data BT [31: 0] to perform 7-bit phase difference information (PDCODE [6: 0], − 32 to +32) are output to the digital filter 106. The digital filter 106 feeds back a 6-bit precision data determination phase control code to the data determination clock generation circuit 141 via the feedback line DFL, and also uses a 6-bit precision boundary detection phase control code via the feedback line BFL. Is returned to the boundary detection clock generation circuit 142. In FIG. 2, the data capture timing (rise timing) of the boundary detection clocks CLKb0 to CLKb3 is the boundary position of the input data. In FIG. 2, the boundary detection data BT0 to BT0 captured by the boundary detection units 120 to 123 are used. BT3 is drawn assuming "1, 1, 0, 1, ...".
[0013]
FIG. 3 is a block diagram showing a data determination clock generation circuit 141 (boundary detection clock generation circuit 142) in the data reception circuit of FIG.
[0014]
As shown in FIG. 3, the data determination clock generation circuit 141 includes a mixer circuit 1411 and a digital to analog converter (DAC) 1413. The mixer circuit 1411 receives the clock signal (four-phase clock) and the output of the DAC 1413, and synthesizes a set of signals having a phase difference of 90 degrees from the four-phase clock to create respective intermediate phases. Then, a clock obtained by adding a phase shift due to a weight (output of the DAC 1413) to the signal having the intermediate phase is generated, and the data determination clock CLKd (CLKd0, CLKd1, CLKd2, CLKd3) is generated. Similarly, the boundary detection clock generation circuit 142 also generates the boundary detection clock CLKb (CLKb0, CLKb1, CLKb2, CLKb3).
[0015]
The mixer circuit 1411 controls the phase based on the current value representing the weight, and the weight for changing the phase is determined by the data determination units 110 to 113 and the boundary detection units 120 to 123 in the phase difference digital code conversion circuit 105. The external input data (or input clock) and the internal clock (data determination clock CLKd and boundary detection clock CLKb) are digitally phase-compared from the output of, and the phase control code (data (Determination phase control code) is supplied to the DAC 1413.
[0016]
The DAC 1413 receives the constant current and the phase control code, converts the phase variable weight into a current and supplies it to the mixer circuit 1411, and the phase of the clock CLKd (CLKb) is varied by the amount of change in the current.
[0017]
Here, the clock recovery circuit (CDR) is a name given by paying attention to the point that the clock for data determination is recovered from the input signal, and the data reception circuit uses the recovered clock to determine the data determination circuit. Is given by paying attention to the point that the data of the input signal is judged and output.
[0018]
In the data receiving circuit (clock recovery circuit) shown in FIGS. 1 and 2, if the same circuit as the data determination units 110 to 113 is used as the boundary detection units 120 to 123 used for phase comparison (clock recovery), a systematic phase is obtained. The clock can be restored with high accuracy without causing a shift, and the sensitivity of phase comparison can be increased.
[0019]
FIG. 4 is a diagram showing an example of data and boundary latch timing in the input signal.
[0020]
In FIG. 4, reference characters DATA [i-2], DATA [i-1], DATA [i], and DATA [i + 1] are latched (determined) by the data determination units 110, 111, 112, and 113, for example. BDATA [i-2], BDATA [i-1], BDATA [i], BDATA [i + 1] are, for example, boundary detection units 120, 121, and 122. , 123 shows the ideal timing of the boundary latched (detected).
[0021]
In the conventional data receiving circuit (clock recovery circuit) described with reference to FIGS. 1 to 4, the input / output characteristics of the phase difference digital code conversion circuit 105 have a large non-linearity. The feedback operation includes limit cycle vibration inherent to so-called bang-bang control. Further, the conventional data receiving circuit also has a disadvantage that the circuit band changes depending on the magnitude of jitter included in the clock for restoring the clock.
[0022]
[Problems to be solved by the invention]
FIG. 5 is a block diagram showing an example of a data receiving circuit according to the related art, and FIG. 6 is a diagram for explaining the operation of the data receiving circuit shown in FIG.
[0023]
As is clear from a comparison between FIG. 5 and FIG. 1, the data receiving circuit of the related art shown in FIG. 5 is provided with a variation generation circuit 107 and an adding circuit 108 with respect to the conventional data receiving circuit shown in FIG. Is.
[0024]
As shown in FIG. 5, the related-art data receiving circuit includes an adder circuit 108 on the feedback line BFL that feeds back the phase control code (boundary detection phase control code) from the digital filter 106 to the boundary detection clock generation circuit 142. The output of the variation generation circuit 107 is supplied to the boundary detection clock generation circuit 142 via the addition circuit 108. That is, by supplying the phase control code, which is the output of the digital filter 106, including the output of the variation generation circuit 107 to the boundary detection clock generation circuit 142, the timing of the boundary detection as shown in FIG. BTi is effectively shifted by the time τ before and after the original boundary detection timing BTi0. Here, for example, the internal reference clock RCLK of 312.5 MHz is supplied to the fluctuation generation circuit 107.
[0025]
The phase difference digital code conversion circuit 105 determines the advance / delay of the phase with several consecutive bit cells, and uses the sum as the output of the phase difference digital code conversion circuit 105. In these determinations, a different time (skew) τ is intentionally given to the determination timing at each determination, and a timing position different from the original boundary determination timing by the skew τ is determined.
[0026]
FIG. 7 is a block diagram showing an example of a phase difference digital code conversion circuit in the data receiving circuit of FIG.
[0027]
As shown in FIG. 7, the phase difference digital code conversion circuit 105 includes a timing determination circuit 151 and a phase difference information output circuit 152. The timing determination circuit 151 receives the 32-bit reception data DT [31: 0] and the boundary detection data BT [31: 0], which are the outputs of the conversion circuits 131 and 132, and determines the timing. Specifically, for example, data determination is performed using received data DATA [i-1], DATA [i] and boundary detection data BDATA [i]. The phase difference information output circuit 152 summarizes the timing determination results for each bit, adds the determination results for 32 bits, and outputs the result as phase difference information.
[0028]
8 is a diagram for explaining the operation of the phase difference digital code conversion circuit shown in FIG. 7, and FIG. 9 is a diagram for explaining the phase difference information output by the phase difference digital code conversion circuit shown in FIG. is there.
[0029]
FIG. 8A shows a case where the latch timing (BTi) by the internal clock (for example, the boundary detection clock CLKb) is earlier than the ideal latch timing (BTi0) (EARLY), and FIG. The case where the latch timing by the internal clock is later than the ideal latch timing (LATE) is shown, and FIG. 8C shows the data (DATA [i-1]) at a certain time point and the next data (DATA [ i]), a transition (“0” → “1” or “1” → “0”) does not appear, that is, the same data continues (NO TRANSITION).
[0030]
As shown in FIGS. 8 and 9, for example, the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [i] are [1, 0, 1] or [0, 1, 0]. (Corresponding to [1, 0, 1] in FIG. 8), the timing determination circuit 151 determines that the latch timing based on the internal clock is earlier than the ideal latch timing (EARLY), and the code CODEi [ 1: 0], “1, 1” (that is, “−1”: delays the phase of the data determination clock) is output to the phase difference information output circuit 152. Further, when the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [i] are [1, 0, 0] or [0, 1, 1] (FIG. 8B shows [1 , 0, 0]), the timing determination circuit 151 determines that the latch timing based on the internal clock is later than the ideal latch timing (LATE), and sets “0, 1” (CODE) [1: 0] (“0, 1”). That is, “+1”: advances the phase of the data determination clock) is output to the phase difference information output circuit 152.
[0031]
In other cases, that is, when the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [i] are [0, 0, 0] or [1, 1, 1] (FIG. 8). (C) corresponds to [1, 1, 1]), or the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [i] are [0, 0 when the boundary detection timing is the boundary position. , 1] or [1, 1, 0], the timing determination circuit 151 outputs “0, 0” (ie, “0”) to the phase difference information output circuit 152 as the code CODEi [1: 0]. .
[0032]
The timing determination circuit 151 performs the above-described processing on all bits (DT [31: 0] and BT [31: 0]), and the code CODEk of each bit k (where k = 0 to 31). [1: 0] is supplied to the phase difference information output circuit 152. Then, the phase difference information output circuit 152 adds all the codes CODEk [1: 0] of each bit k and outputs the phase difference information PDCODE [6: 0] to the next stage digital filter. Therefore, the phase difference information PDCODE [6: 0] is a value within the range of −32 to +32. The phase difference information PDCODE is −32 when all 32 bits are “−1”, and the phase difference information PDCODE is +32 when all 32 bits. Is “+1”.
[0033]
FIG. 10 is a diagram for explaining an example of the operation of the data receiving circuit shown in FIG. 5. FIG. 10 (a) shows nonlinear input / output characteristics, and FIG. 10 (b) shows stepped input / output characteristics. Show.
[0034]
The above-described data receiving circuit of FIG. 5 adds the variation generation circuit 107 and the adding circuit 108 to the conventional data receiving circuit, thereby shifting the boundary detection timing before and after the original position. ing. The phase difference digital code conversion circuit 105 determines the phase advance / delay in a number of consecutive bit cells and uses the sum as phase difference information (phase comparison output). In this determination several times, a different skew is intentionally given to the determination timing for each determination.
[0035]
Specifically, for example, the skews are set to − (3/2) τ, − (1/2) τ, (1/2) τ, and (3/2) τ with respect to the original boundary timing. At this time, the input / output characteristics are step-like characteristics composed of four steps as shown in FIG. This can be interpreted as having a linear input / output characteristic with respect to the conventional single-step nonlinear input / output characteristic (see FIG. 10A). In this example, a substantially linear characteristic can be obtained over a range of 4τ over time. If the value of 4τ is set to be approximately the same as the maximum jitter value input to this system, the phase difference digital code conversion circuit 105 can always be operated in a linear range.
[0036]
In this way, the data receiving circuit of the related art shown in FIG. 5 modulates the boundary detection timing before and after the original position, so that the skew different in the phase advance / delay determination timing by the phase difference digital code conversion circuit. To provide linearity to the input / output characteristics, that is, by substantially linearizing the input / output relationship of the boundary detection units 120 to 123 (phase difference digital code conversion circuit 105), a limit cycle peculiar to the nonlinear system is obtained. The signal amplitude is reduced and the jitter dependency of the feedback loop characteristics is reduced to improve the predictability of the characteristics of the data receiving circuit (clock recovery circuit).
[0037]
However, in the data receiving circuit of the related art described with reference to FIGS. 5 to 10, if the boundary detection timing is modulated before and after the original position, the output of the phase difference digital code conversion circuit 105 includes the modulation. A component appears that fluctuates at the same frequency as used. The phase of the data determination clocks CLKd0 to CLKd3 (CLKd) supplied to the data determination units 110 to 113 includes the above fluctuation component, and this fluctuation component becomes phase noise.
[0038]
Specifically, for example, in SONET (Synchronous Optical Network: North American standard for optical communication), jitter generated in a circuit that performs high-speed signal transmission of about 10 Gbps is defined within 10 ps p-p. Therefore, it is required to minimize the phase noise caused by the phase modulation affecting the internal clock (data determination clock).
[0039]
In view of the problems of the conventional data receiving circuit described above, the present invention reduces the amplitude of the limit cycle signal, reduces the jitter dependency of the feedback loop characteristic, improves the predictability of the characteristic, and linearizes it. The purpose is to minimize phase noise caused by phase modulation for the internal clock. Another object of the present invention is to reduce the clock quantization noise by increasing the resolution of the phase control code generation circuit.
[0040]
[Means for Solving the Problems]
According to the first aspect of the present invention, there is provided a boundary detection circuit that detects a boundary of the input signal according to the first signal, and controls the timing of the first signal according to the detected boundary. A clock recovery circuit for recovering a clock, wherein a boundary detection timing fluctuation means for dynamically changing a boundary detection timing in the boundary detection circuit by giving a fluctuation to the first signal, and the boundary detection timing fluctuation Fluctuation reduction means for reducing phase fluctuations that occur in the recovered clock in response to a dynamic change in boundary detection timing by the means. The boundary detection timing fluctuation means includes a fluctuation generation circuit that generates a fluctuation, and an addition circuit that adds the fluctuation from the fluctuation generation circuit to the first signal, and the fluctuation reduction means The signal related to the recovered clock is averaged over one cycle or a plurality of cycles of the variation output from the variation generation circuit. A clock recovery circuit is provided.
[0041]
According to the first aspect of the present invention, the data determination circuit that determines the data of the input signal using the data determination clock, the boundary detection circuit that detects the boundary of the input signal using the boundary detection clock, and the data Phase control code generating means for receiving the outputs from the determination circuit and the boundary detection circuit and generating a phase control code; and providing a variation to the boundary detection phase control code, and dynamically detecting the boundary detection timing in the boundary detection circuit Boundary detection timing changing means for changing to a boundary, and fluctuation reducing means for reducing a change in phase generated in the data determination clock in response to a dynamic change in the boundary detection timing by the boundary detection timing changing means. The boundary detection timing fluctuation means includes a fluctuation generation circuit that generates a fluctuation, and an addition circuit that adds the fluctuation from the fluctuation generation circuit to the boundary detection phase control code. The means averages a signal related to the recovered clock over one cycle or a plurality of cycles of the variation output from the variation generation circuit. A data receiving circuit is also provided.
[0042]
According to a second aspect of the present invention, there is provided a clock recovery circuit having an internal clock generation circuit that receives a first phase control code having a first number of bits and generates an internal clock. A phase control code generating circuit for generating a second phase control code having a larger second number of bits, and adding a predetermined fluctuation pattern that fluctuates in a low time to the second phase control code, Addition processing means for outputting the first phase control code corresponding to the number of bits, and the internal clock generation circuit effectively generates an internal clock whose phase is controlled with the resolution of the second number of bits. A clock recovery circuit is provided.
[0043]
According to the second aspect of the present invention, a data determination clock generation circuit that receives a first phase control code having a first number of bits and generates a data determination clock, and an input signal by the data determination clock A data determination circuit that determines the data of the input signal; a boundary detection circuit that detects a boundary of the input signal by a boundary detection clock; and an output from the data determination circuit and the boundary detection circuit; A phase control code generating circuit for generating a second phase control code having a larger second number of bits, and adding a predetermined fluctuation pattern that fluctuates in a low time to the second phase control code, Adding processing means for outputting the first phase control code corresponding to the number of bits; Data receiving circuit, characterized by generating a phase control data decision clock with the second resolution of the number of bits to be provided.
[0044]
FIG. 11 is a block diagram showing the principle configuration of the data receiving circuit (clock recovery circuit) according to the first embodiment of the present invention. In FIG. 11, reference numeral 201 is a determination circuit (data determination circuit), 202 is a phase comparison circuit (boundary detection circuit), 205 is a phase code generation circuit, 207 is a fluctuation generation circuit, 208 is an addition circuit, and 209 is fluctuation removal. Reference numeral 241 denotes a determination clock generation circuit (data determination clock generation circuit), and reference numeral 242 denotes a phase comparison clock generation circuit (boundary detection clock generation circuit).
[0045]
As shown in FIG. 11, in the data receiving circuit (clock recovery circuit) according to the first embodiment of the present invention, the output of the phase code generation circuit 205 is supplied to the determination clock generation circuit 241 via the fluctuation removal circuit 209. It has come to be. That is, the input data is supplied to the determination circuit 201 and the phase comparison circuit 202, and the phase comparison circuit 201 compares the phase with the determination clock CLKd, and the phase comparison circuit 202 compares the phase with the phase comparison clock CLKb. The outputs of the determination circuit 201 and the phase comparison circuit 202 are supplied to the phase control code generation circuit 205, and the phase control code from the phase control code generation circuit 205 is supplied to the determination clock generation circuit 241 via the fluctuation removal circuit 209. And supplied to the phase comparison clock generation circuit 242 via the fluctuation removal circuit 209 and the addition circuit 208.
[0046]
The fluctuation generation circuit 207 generates a fluctuation for modulating the phase comparison timing in the phase comparison circuit 202 before and after the original position. The fluctuation from the fluctuation generation circuit 207 is added by the addition circuit 208. By adding and supplying to the phase comparison clock generation circuit 242, the input / output relationship of the phase comparison circuit 202 is substantially linearized. The fluctuation removal circuit 209 removes a periodic or aperiodic fluctuation pattern in the output of the phase control code generation circuit 205 superimposed by the output (fluctuation) of the fluctuation generation circuit 207 added by the addition circuit 208. The variation pattern is removed using the fact that the added value (variation: amplitude and frequency) is known.
[0047]
Here, the fluctuation removal circuit 209 can be configured as, for example, a band rejection filter (notch filter) that removes the added fluctuation frequency components. In addition, the notch filter may be realized by a normal analog band rejection filter or a moving average filter with a period corresponding to a variation to be added. Then, by integrating one cycle of the output of the phase comparison circuit 202, frequency components that are 1 time, 2 times,..., M times the frequency of the added fluctuation can be completely removed. Note that the fluctuation removal circuit 209 can also be configured as a part of a filter that processes the output of the phase control code generation circuit 205, for example.
[0048]
The amount (variation) added by the adding circuit 208 can control (dynamically control) a variation pattern represented by the amplitude and frequency. The amount of addition required for linearization also depends on the magnitude of the phase variation of the data. By changing the amount of addition according to the magnitude of the phase variation, it is possible to minimize the output phase variation due to the addition. It is.
[0049]
FIG. 12 is a block diagram showing a principle configuration of a data receiving circuit (clock recovery circuit) according to the second embodiment of the present invention.
[0050]
As shown in FIG. 12, in the data receiving circuit (clock recovery circuit) according to the second embodiment of the present invention, an adder circuit 300 is provided between the phase control code generation circuit 205 and the determination clock generation circuit 241. The addition circuit 300 adds a predetermined addition series (for example, variation pattern “0 → 3 → 1 → 2 → 0 →...” Or “0 → 1 → 2 → 3 → 0 →...”).
[0051]
That is, linearization (improvement of phase discrimination capability) by adding a known fluctuation pattern to the phase control code (output of the phase control code generation circuit 205) is also possible for the output of the phase control code generation circuit 205. is there. For example, when the phase control code generation circuit 205 is controlled by a digital code, the interval of phase values that can be output is determined by the resolution of the phase control code generation circuit 205. However, as shown in FIG. 12, the phase control code (code having a resolution higher than the resolution of the phase control code generation circuit 205: internal code n + 2 bit code) has a known variation (for example, variation pattern “0 → 3 → 1”). → 2 → 0 → ... ”or“ 0 → 1 → 2 → 3 → 0 → ... ”), and only the upper bits (upper n bits) that can be decomposed by the determination clock generation circuit 241 in the resulting code are added. This is sent to the determination clock generation circuit 241. By averaging the resulting phase (filtering out the fluctuation component), an output with the same resolution as the internal code (phase control code) can be obtained.
[0052]
As described above, according to the first embodiment of the present invention, the amplitude of the limit cycle signal is reduced, the jitter dependency of the feedback loop characteristic is reduced to improve the predictability of the characteristic, and the linearization Therefore, phase noise caused by the phase modulation affecting the internal clock can be minimized. Furthermore, according to the second aspect of the present invention, since the resolution of the phase control code generation circuit can be increased, clock quantization noise can also be reduced. As a result, the timing margin of the receiving circuit is increased, and a data receiving circuit (clock recovery circuit) capable of further stable and high-speed operation can be provided.
[0053]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a data receiving circuit (clock recovery circuit) according to the present invention will be described in detail with reference to the accompanying drawings.
[0054]
FIG. 13 is a block diagram showing an embodiment of a data receiving circuit according to the present invention, which is configured as a 4-way × 2 type interleave circuit using CDR.
[0055]
In FIG. 13, reference numerals 10 to 13 are data determination units (data determination flip-flops), 20 to 23 are boundary detection units (boundary detection flip-flops), and 31 and 32 are conversion circuits for data and boundary. Show. Reference numeral 41 is a data determination clock generation circuit, 42 is a boundary detection clock generation circuit, 5 is a phase difference digital code conversion circuit, 6 is a digital filter, 7 is a variation generation circuit, 8 is an addition circuit, and Reference numeral 9 denotes a fluctuation removing circuit. Further, reference numeral DIL indicates a data input line, DCL indicates a data determination clock line, BCL indicates a boundary detection clock line, and DFL and BFL indicate data and boundary feedback lines.
[0056]
As is clear from the comparison between FIG. 13 and FIG. 5, the data receiving circuit of this embodiment shown in FIG. 13 is further provided with a fluctuation removing circuit 9 in addition to the data receiving circuit of the related art shown in FIG. The periodic or non-periodic fluctuation pattern in the output of the phase difference digital code conversion circuit 5 superposed by the output (fluctuation) of the fluctuation generation circuit 7 added in 8 is removed, and a data determination phase control code is obtained. This is supplied to the data determination clock generation circuit 41. Here, the fluctuation generation circuit 7 is supplied with, for example, an internal reference clock RCLK of 312.5 MHz. In this embodiment, the boundary detection phase control code is also supplied to the boundary detection clock generation circuit 42 after the fluctuation pattern is removed by the fluctuation removal circuit 9.
[0057]
The fluctuation removal circuit 9 is a digitally synthesized band stop filter, and is configured such that the stop frequency matches the frequency of the modulation signal. This band rejection filter can be realized by using a known FIR filter technique. According to the data receiving circuit of the present embodiment, the amplitude of the limit cycle signal is reduced, the jitter dependency of the feedback loop characteristic is reduced to improve the predictability of the characteristic, and phase modulation for linearization is performed. Phase noise caused by the internal clock can be suppressed.
[0058]
14 and 15 are diagrams for explaining linearization processing in the data receiving circuit of FIG. In FIG. 14, reference numeral 1 indicates a data determination unit (data determination flip-flop), and 2 indicates a boundary detection unit (boundary detection flip-flop).
[0059]
Similar to the data receiving circuit of the related art described with reference to FIGS. 5 to 10, in this embodiment, the boundary supplied to the boundary detection unit 1 (10 to 13) by the variation generation circuit 7 and the addition circuit 8. Linearization is performed by changing the phase of the detection clock CLKb (CLKb0 to CLKb3). However, in the data receiving circuit of the related art described above, the skew (change in phase) is − (3/2) τ, − (1/2) τ, (1/2) τ with respect to the original boundary timing. In this embodiment, the phase of the boundary detection clock CLKb is, for example, 0.5 UI (Unit Interval: clock cycle on the data side). ) Is dynamically changed on the basis of eight steps, and the average value of the phase information during one period is obtained.
[0060]
Specifically, for example, the skew for one step is set to 0.0625 UI, and the phase difference between the input data and the data determination clock (CLKd) in the initial state such as when the device (data receiving circuit) is powered on. Therefore, the linearization range is expanded, for example, to 12 stages (the linearization range is 0.75 UI: (1) side in FIG. 15), so that large jitter of input data can be dealt with. When the apparatus is stabilized and the phase difference between the input data and the data determination clock becomes small, the linearization range is set to, for example, four stages (the linearization range is 0.25 UI: (2) side in FIG. 15). As narrow. Thus, for example, the linearization range can be dynamically controlled by the initial state, the stable state, etc. (by the phase difference between the input data and the data determination clock). Here, a state in which the phase difference between the input data in the initial state when the power is turned on and the data determination clock is large is referred to as an unstable state, and the apparatus stably stabilizes the phase difference between the input data and the data determination clock to be small. This state is called a stable state.
[0061]
In addition, the slope (gain) of the fluctuation used for linearization is steep in the unstable state ((3) side in FIG. 15) and loose in the stable state ((4) side in FIG. 15). The slope of the minute can also be controlled dynamically. Conversely, the frequency characteristics of the loop can be kept constant by maintaining a constant proportional relationship between the phase difference (phase difference between the input data and the data determination clock) and the gain regardless of the linearization range. it can. Note that when the slope (gain) of the fluctuation is dynamically changed, the proportional relationship between the phase difference and the gain is broken. For example, in a stable state of a device where the phase difference between the input data and the data determination clock is small, if the gain is increased more than necessary (that is, if the slope is steep), excessive follow-up characteristics will result in the data determination clock. This may cause jitter and may be undesirable. In the opposite case, that is, when the gain is too small, it may be impossible to follow the phase.
[0062]
Further, the skew for one step (for example, 0.0625 UI is set as a reference) is set to be small (for example, 0.05 UI) in the unstable state and set to be large (for example, 0.075 UI) in the stable state. Thus, it is also possible to dynamically control the skew setting value for one stage.
[0063]
In the process of locking the internal clock (for example, data determination clock) to the input data, the CDR loop time constant is set short in the initial state, and then changed to a longer time constant when the steady state is reached. The time for the clock to lock to the input data can be shortened. This means that the cutoff frequency of the loop is changed between the initial state and the steady state. That is, when the loop time constant is short, the cutoff frequency is high, and when the loop time constant is long, the cutoff frequency is low. In this case, the period for the fluctuation added to the boundary detection phase control code to be supplied to the boundary detection clock generation circuit 42 can be made variable, and the frequency for the fluctuation to be added can be changed along with the change in the cutoff frequency. it can.
[0064]
Further, the amplitude of the fluctuation added to the boundary detection phase control code can be made variable, and when the phase difference between the input data and the data determination clock is small, the fluctuation amplitude can also be controlled to be small. At this time, the gain of the phase detector also changes depending on the amplitude of the fluctuation added to the boundary detection phase control code, but the digital filter parameters are automatically adjusted so that the frequency characteristics of the loop are the same. May be.
[0065]
Note that the amplitude of fluctuation necessary for linearizing the phase detector is proportional to the magnitude of the input of the phase detector (that is, the phase difference between the input data and the boundary detection clock). Since it is sufficient to perform linearization only in a range that covers the input range of phase detection, it is possible to minimize clock phase fluctuations due to fluctuations by not giving more fluctuations than necessary.
[0066]
FIG. 16 is a diagram showing an example of an output pattern of the fluctuation generation circuit in the data receiving circuit of FIG. 13, FIG. 16 (a) shows an example of a triangular wave, and FIG. 16 (b) shows an example of a zigzag wave. Show.
[0067]
In the triangular wave shown in FIG. 16A, one cycle (3.2 ns × 8 = 15.6 ns) is configured with eight steps in which the time for one step is 1 / (312.5 MHz) = 3.2 ns. The frequency of the triangular wave is 312.5 MHz ÷ 8≈39.1 MHz. In addition, the zigzag wave shown in FIG. 16B is composed of two stages in which the time for one stage is 3.2 ns, and one cycle (3.2 ns × 2 = 6.4 ns) is formed. The frequency is 312.5 MHz ÷ 2 = 156.25 MHz.
[0068]
That is, the triangular wave shown in FIG. 16A has a code value ranging from −2 to +2, for example, a pattern of 0 → + 1 → + 2 → + 1 → 0 → −1 → −2 → −1 → 0 →. The frequency of fluctuation is 39.1 MHz. Further, the zigzag wave shown in FIG. 16B has a code value ranging from −4 to +4, for example, 0 → −4 → + 1 → −3 → + 2 → −2 → + 3 → −1 → + 4 → 0 → Since the pattern is + 3 →... And the frequency of the fluctuation is 156.25 MHz, which is higher than the triangular wave, the fluctuation that appears in the data determination clock (internal clock) is smaller due to the low-pass characteristics of the feedback loop. There is an advantage.
[0069]
FIG. 17 is a block diagram showing an example of a fluctuation removing circuit in the data receiving circuit of FIG. 13. In the case where the fluctuation is a triangular wave as shown in FIG. 16A (and as shown in FIG. 16B). This is an example of the configuration of the fluctuation removal circuit 9 applicable to the case of a zigzag wave.
[0070]
As shown in FIG. 17, the fluctuation removal circuit 9 is configured as a notch filter, and is connected in series to eight stages of flip-flops 911 to 918, a subtraction circuit 92, an addition circuit 93, a flip-flop 94, and a division circuit. 95. For example, the flip-flops 911 to 918 sequentially take in data with a 312.5 MHz clock, and the time for one stage is 3.2 ns (= 1 / (312.5 MHz)) by the eight flip-flops 911 to 918. Fluctuations in the phase control code (data determination phase control code) corresponding to the triangular wave constituting one cycle with 8 stages are removed. Here, the adder circuit 93 and the flip-flop 94 constitute an integration circuit for outputting a low-frequency component in the initial state or when locked, and the division circuit 95 is an output of the integration circuit (flip-flop 94). Is divided by the number 8 corresponding to the eight-stage flip-flops 911 to 918 and output.
[0071]
FIG. 18 is a diagram for explaining the operation of the fluctuation removal circuit of FIG.
[0072]
As can be seen from FIG. 18, the fluctuation removal circuit (notch filter) 9 shown in FIG. 17 can remove a triangular wave having a frequency of 39.1 MHz as shown in FIG. Further, it can be seen that the fluctuation removing circuit 9 can remove a zigzag wave having a frequency of 156.25 MHz as shown in FIG. For zigzag waves with a frequency of 156.25 MHz, two stages (corresponding to one cycle of the zigzag wave) or 2h stages (h is a positive integer: zigzag wave) instead of the eight-stage flip-flops 911 to 918. It can also be removed by providing only flip-flops (corresponding to h times one cycle).
[0073]
FIG. 19 is a block diagram showing another example of the fluctuation removing circuit in the data receiving circuit of FIG. 13, and FIG. 19 (a) shows a fluctuation removing circuit configured with a FIR (Finit-duration Impulse Response) filter. FIG. 19B shows a variation removing circuit configured with a moving average circuit.
[0074]
As shown in FIG. 19A, the fluctuation removing circuit 9 is configured by, for example, a known FIR filter including delay elements 961 to 963 and adders 971 to 974, or FIG. As shown in FIG. 4, for example, it can be configured by a known moving average circuit including delay elements (for example, flip-flops) 981 to 983 and an average circuit 99. Here, the number of stages of delay elements 961 to 963 and adders 971 to 974 in the FIR filter of FIG. 19A and the number of stages of delay elements 981 to 983 in the moving average circuit of FIG. (The output of the fluctuation generation circuit 7 given through the adder circuit 8), and thus, the fluctuation from the past one cycle to the present time is removed. Further, the FIR filter of FIG. 19A and the moving average circuit of FIG. 19B are, for example, a variation of a triangular wave that constitutes one cycle in four stages (and a zigzag wave as shown in FIG. 16B). Can be removed. The fluctuation of the zigzag wave is, for example, an FIR filter having one delay element (961) and two adders (971, 972) as the fluctuation removal circuit 9, or one delay element (981) and an average. It can be eliminated by using a moving average circuit with circuit (99).
[0075]
FIG. 20 is a block diagram showing another example of the data receiving circuit according to the present invention.
[0076]
As apparent from the comparison between FIG. 20 and FIG. 13 described above, in the data receiving circuit of this embodiment, the output of the digital filter 6 is directly supplied to the adding circuit 8 and the output of the fluctuation removing circuit 90 (for data determination). The phase control code) is supplied only to the data determination clock generation circuit 41. This is because it is necessary to supply the data determination phase generation code from which the variation pattern is removed by the variation removal circuit 90 to the data determination clock generation circuit 41, but to the boundary detection clock generation circuit 42. This is because it is not always necessary to supply the boundary detection phase control code from which the fluctuation pattern is removed by the fluctuation removal circuit 90.
[0077]
This is because the fluctuation of the output of the digital filter 6 supplied to the adding circuit 8 is smaller than the amplitude of the output of the fluctuation generating circuit 7. The data receiving circuit shown in FIG. 20 has an advantage that the delay of the fluctuation removing circuit 90 is removed from the feedback loop on the boundary detection side, so that the stability of the feedback is not impaired.
[0078]
FIG. 21 is a block diagram showing still another example of the data receiving circuit according to the present invention, and FIG. 22 is a diagram for explaining the operation of the data receiving circuit of FIG.
[0079]
As shown in FIG. 21, in the data receiving circuit of this embodiment, the digital filter 600 generates a 6-bit precision phase control code and supplies it to the adder circuit 8, and 8 bits through the fluctuation removing circuit 900. An accurate phase control code is supplied to the adder circuit 80. That is, the digital filter 600 supplies a phase control code having a resolution (for example, 8-bit accuracy) higher than the resolution (for example, 6-bit accuracy) of the data determination clock generation circuit 41 to the adder circuit 80 via the fluctuation removal circuit 900. The addition circuit 80 adds the output (variation) of the variation generation circuit 70 and adds the upper 6 bits (6-bit precision) data determination phase control code corresponding to the resolution of the data determination clock generation circuit 41. Is supplied to the data determination clock generation circuit 41. Further, the digital filter 600 supplies a 6-bit precision phase control code to the adder circuit 8 and generates a boundary detection phase control code to which the output of the variation generation circuit 7 is added by the adder circuit 8. This is supplied to the circuit 42, which is performed by using the triangular wave shown in FIG. 16A or the zigzag wave shown in FIG. The fluctuation generation circuits 7 and 70 are supplied with, for example, an internal reference clock RCLK of 312.5 MHz.
[0080]
Specifically, as shown in FIG. 22A, for example, when the 8-bit phase control code output from the fluctuation removing circuit 900 (digital filter 600) is “−1”, the fluctuation is caused by the adding circuit 80. When a periodic fluctuation pattern “0 → 1 → 2 → 3 → 0 →...” That is an output of the minute generation circuit 70 is added, a 6-bit precision phase control code (data) that is the output of the addition circuit 80 is added. The phase control code for determination) is (−1 + 0 + 0 + 0) /4=−0.25 (average code) by the rounding operation. That is, it can be seen that the 8-bit precision phase control code “−1” becomes the 6-bit precision phase control code “−0.25”.
[0081]
Specifically, as shown in FIG. 22B, for example, when the 8-bit precision phase control code output from the fluctuation removing circuit 900 (digital filter 600) is “−3”, the adder circuit 80 When a periodic fluctuation pattern “0 → 1 → 2 → 3 → 0 →...” Which is the output of the fluctuation generation circuit 70 is added, the 6-bit precision phase control code which is the output of the addition circuit 80 is added. Becomes (-1-1-1 + 0) /4=-0.75 (average code) by the rounding operation. That is, it can be seen that the 8-bit precision phase control code “−3” becomes the 6-bit precision phase control code “−0.75”.
[0082]
In this way, the value of the data determination phase control code supplied to the data determination clock generation circuit 41 is the same value as the 8-bit precision code whose average value is the output of the fluctuation removal circuit 900 (digital filter 600). This shows the fluctuation pattern.
[0083]
FIG. 23 is a diagram showing an example of the variation added to the data determination phase control code in the data receiving circuit of FIG.
[0084]
As described above, the variation added to the data determination phase control code by the addition circuit 80 (output of the variation generation circuit 70) is, for example, “0 → 1 → 2 → as shown in FIG. 3 → 0 → ... ”is a periodic variation pattern (sawtooth wave pattern). As this variation pattern, for example,“ 0 → 3 → 1 → 2 → 0 →... ”As shown in FIG. May be a periodic variation pattern (harmonic pattern).
[0085]
The fluctuation pattern “0 → 3 → 1 → 2 → 0 →...” Shown in FIG. 23B is more frequency component than the fluctuation pattern “0 → 1 → 2 → 3 → 0 →...” Shown in FIG. That is, that is, a 6-bit precision phase control code (input signal of the data determination clock generation circuit 41) obtained by rounding an 8-bit precision phase control code to which each variation is added is shown in FIG. The harmonic fluctuation pattern shown in (b) has a higher frequency component than the sawtooth wave fluctuation pattern shown in FIG. As a result, the fluctuation in the signal averaged by the LPF (low-pass filter: CR integration circuit 415; see FIG. 24) of the data determination clock generation circuit 41 is the harmonic fluctuation pattern shown in FIG. Is smaller than the sawtooth wave fluctuation pattern shown in FIG. 23 (a), the harmonic fluctuation pattern of FIG. 23 (b) is preferable. Needless to say, the output of the variation generation circuit 70 can be variously modified according to the number of bits of the applied phase control code.
[0086]
FIG. 24 is a block diagram showing an example of a data determination clock generation circuit in the data reception circuit of FIG.
[0087]
As shown in FIG. 24, the 6-bit precision data determination phase control code that is the output of the adder circuit 80 is supplied to the DAC 413 in the data determination clock generation circuit 41, and further via the CR integration circuit 415. This is supplied to the mixer circuit 411. The data determination phase control code is averaged by the time constant of the integration circuit 415 by CR, and the resolution of the actually output phase is equivalent to 8 bits. Therefore, in the data receiving circuit of the present embodiment, it is possible to improve the resolution of the digitally controlled clock generation circuit (data determination clock generation circuit 41) and reduce the quantization error in the digital control. .
[0088]
Further, the data receiving circuit of the embodiment shown in FIG. 21 adds a fluctuation generating circuit 70 and an adding circuit 80 to the data receiving circuit of FIG. 20, and the data determination phase control code output from the digital filter 6 is 8 bits. It has become.
[0089]
FIG. 25 is a block diagram showing still another example of the data receiving circuit according to the present invention.
[0090]
In the data receiving circuit of the embodiment shown in FIG. 25, a variation generation circuit 70 and an adding circuit 80 are added to the data receiving circuit of FIG. 13, and the data determination phase control code output from the digital filter 6 is converted to 8 bits. Is. As described above, in the first embodiment (see FIG. 11 and the like) and the second embodiment (see FIG. 12 and the like) of the present invention, one or both of them can be appropriately applied to configure the data receiving circuit. it can.
[0091]
(Supplementary Note 1) A clock having a boundary detection circuit that detects a boundary of an input signal according to a first signal, and that restores a clock by controlling the timing of the first signal according to the detected boundary. A restoration circuit,
Boundary detection timing changing means for giving a change to the first signal and dynamically changing a boundary detection timing in the boundary detection circuit;
A clock restoration circuit comprising: fluctuation reduction means for reducing a fluctuation in phase generated in the recovered clock in accordance with a dynamic change in boundary detection timing by the boundary detection timing fluctuation means.
[0092]
(Supplementary note 2) In the clock restoration circuit according to supplementary note 1, the boundary detection timing varying means includes:
A fluctuation generation circuit for generating fluctuations;
A clock restoration circuit comprising: an addition circuit for adding a variation from the variation generation circuit to the first signal.
[0093]
(Supplementary note 3) The clock restoration circuit according to supplementary note 2, wherein the fluctuation generation circuit generates a triangular wave fluctuation that changes in a stepwise manner over one period of fluctuation. Restoration circuit.
[0094]
(Supplementary Note 4) The clock restoration circuit according to Supplementary Note 2, wherein the fluctuation generation circuit generates a zigzag fluctuation that changes while repeating increase / decrease a plurality of times within one period of fluctuation. Restoration circuit.
[0095]
(Supplementary Note 5) In the clock restoration circuit according to Supplementary Note 3 or 4, the fluctuation generation circuit generates a fluctuation over a wide phase range in an unstable state, and covers a narrow phase range in a stable state. A clock recovery circuit that generates fluctuations.
[0096]
(Supplementary Note 6) In the clock restoration circuit according to Supplementary Note 3 or 4, the variation generation circuit generates a large gain variation in an unstable state and generates a small gain variation in a stable state. And a clock recovery circuit.
[0097]
(Supplementary Note 7) In the clock recovery circuit according to Supplementary Note 3 or 4, the fluctuation generation circuit generates a fluctuation by increasing a unit time of one step in an unstable state, and one step in a stable state. A clock recovery circuit characterized by generating a fluctuation amount by reducing the unit time.
[0098]
(Supplementary note 8) In the clock restoration circuit according to supplementary note 2, the fluctuation reducing means averages a signal related to the restoration clock over one period or a plurality of periods of the fluctuation output by the fluctuation generation circuit. A clock recovery circuit.
[0099]
(Supplementary note 9) The clock restoration circuit according to supplementary note 8, wherein the fluctuation reducing means is a notch filter, an FIR filter, or a moving average circuit.
[0100]
(Supplementary Note 10) In the clock restoration circuit according to Supplementary Note 1, the boundary detection circuit includes a plurality of boundary detection units, and each of the boundary detection units performs detection of a boundary according to each of the boundary detection clocks. A clock recovery circuit.
[0101]
(Supplementary Note 11) A clock recovery circuit having an internal clock generation circuit that receives a first phase control code having a first number of bits and generates an internal clock,
A phase control code generating circuit for generating a second phase control code having a second number of bits greater than the first number of bits;
Addition processing means for adding a predetermined fluctuation pattern that fluctuates in low time to the second phase control code and outputting the first phase control code corresponding to the first number of bits; The clock generation circuit effectively generates an internal clock whose phase is controlled with a resolution of the second number of bits.
[0102]
(Supplementary note 12) In the clock recovery circuit according to Supplementary note 11, the addition processing means is configured to “0 → 1 → 2 → 3 → 0 →... With respect to the 8-bit precision phase control code from the phase control code generation circuit. A clock restoration circuit characterized by adding periodic fluctuation patterns.
[0103]
(Supplementary note 13) In the clock recovery circuit according to supplementary note 11, the addition processing means is configured to “0 → 3 → 1 → 2 → 0 →...” With respect to the 8-bit precision phase control code from the phase control code generation circuit. A clock restoration circuit characterized by adding periodic fluctuation patterns.
[0104]
(Supplementary Note 14) In the clock recovery circuit according to Supplementary Note 11, the internal clock generation circuit includes a plurality of data determination units, and each data determination unit determines data according to each data determination clock. A clock recovery circuit.
[0105]
(Supplementary Note 15) A data determination circuit that determines data of an input signal using a data determination clock;
A boundary detection circuit for detecting a boundary of the input signal by a boundary detection clock;
Phase control code generating means for receiving outputs from the data determination circuit and the boundary detection circuit and generating a phase control code;
Boundary detection timing changing means for giving a change to the boundary detection phase control code and dynamically changing a boundary detection timing in the boundary detection circuit;
A data receiving circuit, comprising: fluctuation reducing means for reducing a fluctuation in phase generated in the data determination clock in response to a dynamic change in boundary detection timing by the boundary detection timing changing means.
[0106]
(Supplementary note 16) In the data receiving circuit according to supplementary note 15, the boundary detection timing varying means includes:
A fluctuation generation circuit for generating fluctuations;
A data receiving circuit comprising: an adding circuit for adding a fluctuation from the fluctuation generating circuit to the boundary detection phase control code.
[0107]
(Supplementary Note 17) In the data receiving circuit according to Supplementary Note 16, the phase difference between the data of the input signal and the data determination clock and the gain of the feedback loop are independent of the amplitude of the variation generated by the variation generation circuit. And a data receiving circuit characterized by maintaining a constant proportional relationship.
[0108]
(Supplementary note 18) The data reception circuit according to supplementary note 16, wherein the variation generation circuit is capable of changing an output pattern.
[0109]
(Supplementary note 19) The data reception circuit according to supplementary note 18, wherein the fluctuation generation circuit is capable of changing a frequency of a certain output pattern between an initial state and a steady state.
[0110]
(Supplementary note 20) The data receiving circuit according to supplementary note 16, wherein the fluctuation generation circuit generates a triangular wave fluctuation that changes in a stepwise manner over one period of fluctuation. Receiver circuit.
[0111]
(Supplementary note 21) The data receiving circuit according to supplementary note 16, wherein the fluctuation generation circuit generates a zigzag fluctuation that changes while repeating increase / decrease a plurality of times within one cycle of fluctuation. Receiver circuit.
[0112]
(Supplementary note 22) In the data receiving circuit according to supplementary note 20 or 21, the fluctuation generation circuit generates a fluctuation over a wide phase range in an unstable state, and covers a narrow phase range in a stable state. A data receiving circuit that generates fluctuations.
[0113]
(Supplementary note 23) In the data receiving circuit according to supplementary note 20 or 21, the fluctuation generation circuit generates a large gain fluctuation in an unstable state and generates a small gain fluctuation in a stable state. A data receiving circuit.
[0114]
(Supplementary Note 24) In the data receiving circuit according to Supplementary Note 20 or 21, in the fluctuation state, the fluctuation amount generation circuit generates a fluctuation amount in which one unit time is increased in an unstable state, and one step in a stable state. A data receiving circuit characterized by generating a fluctuation amount by reducing the unit time.
[0115]
(Supplementary note 25) In the data receiving circuit according to supplementary note 16, the fluctuation reducing means averages a signal related to the restored clock over one cycle or a plurality of cycles of the fluctuation output from the fluctuation generating circuit. A data receiving circuit.
[0116]
(Supplementary note 26) The data reception circuit according to supplementary note 25, wherein the fluctuation reducing means is a notch filter, an FIR filter, or a moving average circuit.
[0117]
(Supplementary Note 27) A data determination clock generation circuit that receives a first phase control code having a first number of bits and generates a data determination clock;
A data determination circuit for determining data of an input signal by the data determination clock;
A boundary detection circuit for detecting a boundary of the input signal by a boundary detection clock;
A phase control code generation circuit that receives outputs from the data determination circuit and the boundary detection circuit and generates a second phase control code having a second number of bits greater than the first number of bits;
Addition processing means for adding a predetermined fluctuation pattern that fluctuates in low time to the second phase control code and outputting the first phase control code corresponding to the first number of bits; The determination clock generation circuit effectively generates a data determination clock whose phase is controlled with the resolution of the second number of bits.
[0118]
(Supplementary note 28) In the data receiving circuit according to supplementary note 27, the addition processing means is configured to “0 → 1 → 2 → 3 → 0 →... With respect to the 8-bit precision phase control code from the phase control code generation circuit. A data receiving circuit characterized by adding periodic fluctuation patterns.
[0119]
(Supplementary note 29) In the data receiving circuit according to supplementary note 27, the addition processing means performs “0 → 3 → 1 → 2 → 0 →... With respect to the 8-bit precision phase control code from the phase control code generation circuit. A data receiving circuit characterized by adding periodic fluctuation patterns.
[0120]
(Supplementary Note 30) In the data receiving circuit according to any one of Supplementary Notes 15 to 29, the boundary detection circuit includes a plurality of boundary detection units, and each boundary detection unit is respectively in accordance with each boundary detection clock. A data receiving circuit, wherein the data determination circuit includes a plurality of data determination units, and each data determination unit determines data according to each data determination clock.
[0121]
【The invention's effect】
As described above in detail, according to the data receiving circuit (clock recovery circuit) of the present invention, the amplitude of the limit cycle signal is reduced, and the jitter dependency of the feedback loop characteristic is reduced to improve the predictability of the characteristic. In addition, phase noise caused by the phase modulation for linearization affecting the internal clock can be minimized. Furthermore, according to the data receiving circuit (clock recovery circuit) of the present invention, the resolution of the phase control code generation circuit can be increased to reduce clock quantization noise.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a conventional data receiving circuit.
FIG. 2 is a diagram illustrating timings of signals in the data receiving circuit of FIG.
3 is a block diagram showing a data determination clock generation circuit in the data reception circuit of FIG. 1; FIG.
FIG. 4 is a diagram showing an example of data and boundary latch timing in an input signal.
FIG. 5 is a block diagram illustrating an example of a data receiving circuit according to related technology.
[Fig. 6]
FIG. 6 is a diagram for explaining the operation of the data receiving circuit shown in FIG. 5.
7 is a block diagram illustrating an example of a phase difference digital code conversion circuit in the data reception circuit of FIG. 5;
8 is a diagram for explaining the operation of the phase difference digital code conversion circuit shown in FIG. 7;
9 is a diagram for explaining phase difference information output from the phase difference digital code conversion circuit shown in FIG. 7; FIG.
10 is a diagram for explaining an example of the operation of the data receiving circuit shown in FIG. 5. FIG.
FIG. 11 is a block diagram showing a principle configuration of a data receiving circuit according to the first embodiment of the present invention.
FIG. 12 is a block diagram showing a principle configuration of a data receiving circuit according to a second embodiment of the present invention.
FIG. 13 is a block diagram showing an embodiment of a data receiving circuit according to the present invention.
14 is a diagram (No. 1) for describing linearization processing in the data receiving circuit of FIG. 13; FIG.
15 is a diagram (No. 2) for explaining the linearization processing in the data receiving circuit of FIG. 13; FIG.
16 is a diagram illustrating an example of an output pattern of a variation generation circuit in the data reception circuit of FIG. 13;
17 is a block diagram illustrating an example of a fluctuation removal circuit in the data reception circuit of FIG. 13;
18 is a diagram for explaining the operation of the fluctuation removal circuit of FIG. 17;
19 is a block diagram showing another example of a fluctuation removing circuit in the data receiving circuit of FIG. 13;
FIG. 20 is a block diagram showing another example of the data receiving circuit according to the present invention.
FIG. 21 is a block diagram showing still another example of the data receiving circuit according to the present invention.
22 is a diagram for explaining the operation of the data receiving circuit of FIG. 21;
FIG. 23 is a diagram illustrating an example of a variation added to the data determination phase control code in the data reception circuit of FIG. 21;
24 is a block diagram showing an example of a data determination clock generation circuit in the data reception circuit of FIG. 21. FIG.
FIG. 25 is a block diagram showing still another example of the data receiving circuit according to the present invention.
[Explanation of symbols]
1,10-13,110-113 ... Data determination unit
2, 20-23, 120-123 ... Boundary detection unit
5,105 ... Phase difference digital code conversion circuit
6,106,600 ... Digital filter
7, 70, 107, 207 ... fluctuation generating circuit
8, 80, 108, 208... Addition circuit
9, 90, 109, 209, 900 ... fluctuation elimination circuit
31, 32; 131, 132 ... conversion circuit
41, 141 ... Data determination clock generation circuit
42, 142 ... Boundary detection clock generation circuit
201: determination circuit
202... Phase comparison circuit
205 ... Phase control code generation circuit
241... Clock generation circuit for determination
242 ... Clock generation circuit for phase comparison
411, 1411 ... mixer circuit
413, 1413 ... Digital-to-analog converter (DAC)
415. Integration circuit
DATA [i-2], DATA [i-1], DATA [i], DATA [i + 1] ... Data judgment timing
BDATA [i-2], BDATA [i-1], BDATA [i], BDATA [i + 1] ... Boundary detection timing
CLKb; CLKb0, CLKb1, CLKb2, CLKb3 ... Boundary detection clock
CLKd; CLKd0, CLKd1, CLKd2, CLKd3 ... Clock for data determination

Claims (9)

A clock recovery circuit that includes a boundary detection circuit that detects a boundary of an input signal according to a first signal, and that recovers a clock by controlling the timing of the first signal according to the detected boundary. And
Boundary detection timing changing means for giving a change to the first signal and dynamically changing a boundary detection timing in the boundary detection circuit;
Fluctuation reduction means for reducing fluctuations in the phase generated in the recovered clock in response to dynamic changes in the boundary detection timing by the boundary detection timing fluctuation means ,
The boundary detection timing variation means includes a variation generation circuit that generates a variation, and an addition circuit that adds the variation from the variation generation circuit to the first signal,
The fluctuation reducing means includes a clock recovery circuit according to claim Rukoto said variation generating circuit turn into average signals associated with the restoration clock over one period or plural periods of fluctuation to be output. A clock recovery circuit having an internal clock generation circuit that receives a first phase control code of a first number of bits and generates an internal clock,
A phase control code generating circuit for generating a second phase control code having a second number of bits greater than the first number of bits;
The second by adding a predetermined variation pattern varying low temporally to the phase control code, and an addition processing means for outputting the first phase control code corresponding to said first number of bits, the An internal clock generation circuit effectively generates a phase-controlled internal clock with a resolution of the second number of bits. A data judgment circuit for judging data of an input signal by a data judgment clock;
A boundary detection circuit for detecting a boundary of the input signal by a boundary detection clock;
Phase control code generating means for receiving outputs from the data determination circuit and the boundary detection circuit and generating a phase control code;
Boundary detection timing changing means for giving a change to the boundary detection phase control code and dynamically changing a boundary detection timing in the boundary detection circuit;
Fluctuation reduction means for reducing fluctuations in the phase generated in the data determination clock in response to a dynamic change in the boundary detection timing by the boundary detection timing fluctuation means ;
The boundary detection timing variation means includes a variation generation circuit that generates a variation, and an addition circuit that adds the variation from the variation generation circuit to the boundary detection phase control code,
The fluctuation reducing means, the data receiving circuit according to claim Rukoto said variation generating circuit turn into average signals associated with the restoration clock over one period or plural periods of fluctuation to be output.   4. The data receiving circuit according to claim 3, wherein the fluctuation generation circuit generates a fluctuation over a wide phase range in an unstable state, and generates a fluctuation over a narrow phase range in a stable state. A data receiving circuit.   4. The data receiving circuit according to claim 3, wherein the fluctuation generating circuit generates a large gain fluctuation in an unstable state and generates a small gain fluctuation in a stable state. Data receiving circuit.   4. The data receiving circuit according to claim 3, wherein the fluctuation generating circuit generates a fluctuation by increasing a unit time of one step in an unstable state, and decreases a unit time of one step in a stable state. A data receiving circuit characterized by generating a fluctuation amount. In the data receiving circuit according to claim 3, wherein the variation reducing means includes a notch filter, the data receiving circuit according to claim FIR filter or moving average circuits der Rukoto. A data determination clock generation circuit for receiving a first phase control code having a first number of bits and generating a data determination clock;
A data determination circuit for determining data of an input signal by the data determination clock;
A boundary detection circuit for detecting a boundary of the input signal by a boundary detection clock;
A phase control code generation circuit that receives outputs from the data determination circuit and the boundary detection circuit and generates a second phase control code having a second number of bits greater than the first number of bits;
Addition processing means for adding a predetermined fluctuation pattern that fluctuates in low time to the second phase control code and outputting the first phase control code corresponding to the first number of bits, data decision clock generation circuit, the data receiving circuit according to claim that you generate phase control data decision clock at effectively the second number of bits of resolution. 9. The data receiving circuit according to claim 3, wherein the boundary detection circuit includes a plurality of boundary detection units, and each boundary detection unit detects a boundary according to each boundary detection clock. And a data receiving circuit comprising a plurality of data judging units, wherein each data judging unit judges data according to each data judging clock .

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