JP2001156625A - Digital vco circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional digital VCO circuit that has had a limit in an operation with a high speed clock because an operating speed of an n-bit adder has a limit. SOLUTION: The digital VCO circuit is provided with an adder means 1 that sums an input value determining the oscillating frequency to an output of an n-bit register, a means 4 that compares the absolute values of the two consecutive output values of the adder means 1 with values of three-times the absolute values to determine the position of a VCO output so as to obtain phase resolution equivalent to the operation of the reference clock with a double frequency in spite of the operation of the reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital VCO for generating a reproduction clock synchronized with a signal reproduced from a medium on which digital data is recorded, such as an optical disk.

[0002]

2. Description of the Related Art In the case of a compact disk (hereinafter, referred to as a CD), in a CD format, recorded information is EF.
Recording is performed by applying a modulation called M. At the time of reproduction, a PLL circuit is used which compares the phase of this EFM signal with the phase of a signal obtained by dividing the clock of the VCO output and generates a reproduction clock. When this PLL circuit is constituted by a digital circuit, it is necessary to digitize the VCO.

FIG. 7 shows a conventional digital VCO circuit.
In FIG. 7, 1 is an n-bit adder, and 2 is a first n-bit register. The input value for determining the oscillation frequency and the output of the first n-bit register 2 are added by an n-bit adder 1, and the output of the n-bit adder 1 is input to a first n-bit register 2 operating with a reference clock. I do. The MSB (most significant bit) of the output of the first n-bit register 2 is
Output.

FIG. 8 is a time chart when the VCO input value is 256. For example, it is assumed that the VCO output is 10 MHz. To obtain a frequency resolution of 1/256 for this clock, the value input to the n-bit adder 1 must be 256 (hexadecimal notation 10
0). For example, if the required phase resolution is 1/8, the frequency of the reference clock is 80 MHz, which is eight times the VCO output.
And Since the addition of 256 becomes one cycle with eight times, n = 11 in this case (256 × 8 = 2048 =
2 ¹¹ ). When the VCO input value is 256, the VCO output is the same as the output obtained by dividing the reference clock by 8, and is always 4 clocks “L” and 4 clocks “H”.

[0005]

However, the operation limit of the conventional digital VCO is limited by the operation speed of the n-bit adder 1. If the latest miniaturized process is used, the operation speed is increased. However, a situation occurs in which the cost must be reduced by an inexpensive process without using the miniaturization process and the operation must be performed with a high-speed clock.

An object of the present invention is to solve this problem, and an object of the present invention is to realize a digital VCO circuit capable of obtaining a phase resolution equivalent to an operation at twice the frequency of a reference clock for operating the circuit. And

[0007]

In order to solve this problem, a digital VCO circuit according to the present invention comprises: a means for adding an input value for determining an oscillation frequency to an output of a first n-bit register; And a means for determining the position of the VCO output by comparing the absolute value of two consecutive values of the output value and its triple value.

According to a first aspect of the present invention, there is provided a digital VCO circuit comprising: an n-bit adder having a VCO input value for determining an oscillation frequency as one addition input; Is a first n-bit register serving as the other addition input of the n-bit adder, and a second n-bit input receiving an output of the first n-bit register.
A bit register; an output of the first n-bit register; an output of the second n-bit register;
When a reference clock, which is an operation reference of the second n-bit register, is input and the most significant bit of the output of the first n-bit register and the output of the second n-bit register are the same, V
When the CO output is not changed and the most significant bit is different, it is determined whether the change point of the most significant bit is closer to the output of the first n-bit register or the output of the second n-bit register, and the VCO output is determined. And a register output value comparison / judgment circuit for controlling.

According to a second aspect of the present invention, there is provided a digital VCO circuit comprising: an n-bit adder having a VCO input value for determining an oscillation frequency as one of the additional inputs; Is a first n-bit register serving as the other addition input of the n-bit adder, and a second n-bit input receiving an output of the first n-bit register.
A bit register, a first absolute value calculation circuit that outputs an absolute value by using an output of the first n-bit register as an input, and outputs a triple value by using an output of the first absolute value calculation circuit as an input A first triple value arithmetic circuit and the second n
A second absolute value calculating circuit that outputs an absolute value by using an output of the bit register as an input, a second triple value calculating circuit that outputs a triple value by using an output of the second absolute value calculating circuit as an input, A first comparison circuit which receives an output of the first triple value calculation circuit and an output of the second absolute value calculation circuit as inputs, and an output of the first absolute value calculation circuit and the second A second comparison circuit which receives an output of the double value calculation circuit as an input, an output of the first comparison circuit, an output of the second comparison circuit, and the first
A determination circuit that receives the most significant bit of the output of the n-bit register and the most significant bit of the output of the second n-bit register as inputs, and serves as a reference for the operation of the first and second n-bit registers. A VCO output having twice the phase resolution of the reference clock is extracted from the output of the determination circuit.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 shows a digital V of the present invention.
3 shows a CO circuit. 1 is an n-bit adder, 2 is the first
N-bit register, 3 is a second n-bit register, 4
Is a register output value comparison determination circuit, 5 is a first absolute value calculation circuit, 6 is a first triple value calculation circuit, 7 is a second absolute value calculation circuit, 8 is a second triple value calculation circuit, 9 is a first comparison circuit, 10 is a second comparison circuit, and 11 is a judgment circuit.

An input value for determining an oscillation frequency and an output of a first n-bit register 2 operated by a reference clock are added by an n-bit adder 1. FIG. 2 shows a time chart of the operation. For example, assume that the VCO output is 10 MHz. To obtain a frequency resolution of 1/256 for this clock, the value input to the n-bit adder is 256 (100 in hexadecimal). Here, for comparison with the conventional example, the frequency of the reference clock is set to 40 MHz, which is four times the VCO output, and the added value is 25 MHz.
6 (hexadecimal representation 100) is configured so that four additions constitute one cycle.

That is, n of the n-bit adder 1, the first n-bit register 2, and the second n-bit register 3 are "1".
0 ". The addition result of the n-bit adder 1 is the first 1
After latching by the 0-bit register 2 and the second 10-bit register 3, the output timing is determined by the register output value comparison determination circuit 4.

In the register output value comparison judgment circuit 4, VC
A comparison is made to output the O output with a phase resolution twice as high as the reference clock. First, the absolute value of the output value A of the first 10-bit register 2, the triple value of the absolute value of A, and the second 1
The absolute value of the output value B of the 0-bit register 3 and the triple value of the absolute value of B are respectively converted into a first absolute value calculating circuit 5, a first triple value calculating circuit 6, a second absolute value calculating circuit 7, It is determined by the second triple value arithmetic circuit 8.

Here, the first and second absolute value calculation circuits 5, 7
Outputs the outputs of the first and second 10-bit registers 2 and 3 to 2
The first absolute value calculation circuit 5 outputs “−A” when the input A is negative, and outputs (2 ⁹ −A) when the input A is positive. It is configured to output. When the input B is positive, the second absolute value calculation circuit 7 outputs B as it is, and when the input B is negative, (2 ⁹ +
B) is output. The outputs of the first and second absolute value calculation circuits 5 and 7 are referred to as | A in the following description.
|, | B |.

Next, in the first comparison circuit 9, the output (| triple of | A |) of the first triple value calculation circuit 6 and the output (| B |) of the second absolute value calculation circuit 7 are calculated. Compare the magnitude of the values. The output of the first absolute value calculation circuit 5 (|
A |) is compared with the magnitude of the value of the output (triple value of | B |) of the second triple value arithmetic circuit 8, and the following determination operation is performed.

That is, as shown in FIG. 3, | B |> 3 | A |
Is satisfied, the VCO output is changed at the point (A) in FIG. When | A |> 3 | B | holds as shown in FIG. 4, the VCO output is changed at the point (B) in FIG. Other than as shown in FIG. 5 (| B | <3 | A | and | A | <3 | B
In the case of |), the VCO output is changed at the point (C) in FIG.

These determination operations are performed only when the MSBs of A and B are different, and when they are the same, the VCO output is not changed. The fact that such a determination is appropriate will be described below. The configuration of the VCO circuit according to the present invention includes a VCO input value and a first
The output value of the 10-bit register 2 is added for each reference clock, but it is assumed that there is virtually a clock obtained by multiplying the reference clock by the VCO input value. Considering a counter that increments (+1) by this virtual clock, the output value of this counter matches the VCO output value of the present invention at the rising point of the reference clock. That is, it can be considered that the VCO output value of the present invention intermittently outputs the value immediately after the reference clock rising point in the output of the virtual clock counter. Considering the change point (1 → 0) of the MSB as shown in FIG. 6, A is negative and B is positive. From the operation of the first and second absolute value calculation circuits 5 and 7, | A | And | B | are considered to represent the distance from the MSB change point of the virtual clock counter.

As described above, when the condition of | B |> 3 | A | is satisfied, the MSB change point of the virtual clock counter exists in the first quarter of the reference clock. Also |
In the case of A |> 3 | B |, it exists during the latter quarter period. When | B | <3 | A | and | A | <3 | B |, it can be seen that they exist in the intermediate period of 1/4 to 3/4.

Thus, it is clear that the operation of the above-described determination circuit is appropriate. MSB change point (0 →
In the case of 1), similarly, the first and second absolute value calculation circuits 5 and 7
| A | and | B | indicate the distance from the MSB change point, and the operation is the same. When the VCO output is changed at an intermediate point of the reference clock as shown in FIG. 5, the generation of the intermediate timing is performed by using the falling edge of the reference clock, the method using a clock twice as large as the reference clock, the gate delay, or the like. There is a method using
Either method may be used. As described above, VC
The O output can have a phase resolution equivalent to twice the reference clock.

[0020]

As described above, the digital VCO circuit of the present invention can realize a digital VCO that can obtain a phase resolution equivalent to an operation with a reference clock having twice the frequency by the operation of the reference clock. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital VCO according to an embodiment of the present invention.

FIG. 2 is a time chart of the embodiment.

FIG. 3 is a time chart of a first example of comparison determination according to the embodiment;

FIG. 4 is a time chart of an example 2 of comparison and judgment of the embodiment.

FIG. 5 is a time chart of a third example of comparison determination according to the embodiment;

FIG. 6 is a time chart of the embodiment.

FIG. 7 is a configuration diagram of a conventional digital VCO.

FIG. 8 is a time chart of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 n-bit adder 2 1st n-bit register 3 2nd n-bit register 4 Register output value comparison judgment circuit 5 1st absolute value calculation circuit 6 1st triple value calculation circuit 7 2nd absolute value calculation Circuit 8 Second triple value operation circuit 9 First comparison circuit 10 Second comparison circuit 11 Judgment circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5D044 BC03 CC04 FG11 GM12 5J106 AA05 BB03 BB04 CC58 DD09 DD13 DD42 DD44 DD48 HH02 JJ02 KK25 LL02

Claims (2)

[Claims] 1. An n-bit adder having a VCO input value for determining an oscillation frequency as one addition input, an output of the n-bit adder being input, and an output being the other addition of the n-bit adder. A first n-bit register that is an input; a second n-bit register that receives an output of the first n-bit register; an output of the first n-bit register; An output and a reference clock as an operation reference of the first and second n-bit registers are input to the first
When the most significant bit of the output of the n-bit register and the output of the second n-bit register are the same, the VCO output is not changed. When the most significant bit is different, the change point of the most significant bit is the first n-bit register. A digital VCO circuit provided with a register output value comparison judging circuit for judging which is closer to the output of the second n-bit register or the output of the second n-bit register and controlling the VCO output. 2. An n-bit adder having one input of a VCO input value for determining an oscillation frequency, an input of an output of the n-bit adder, and an output of the other adder of the n-bit adder. A first n-bit register that is an input; a second n-bit register that receives an output of the first n-bit register; and a second that outputs an absolute value by receiving an output of the first n-bit register as an input. 1, an absolute value calculation circuit, an output of the first absolute value calculation circuit as an input, a first triple value operation circuit for outputting a triple value, and an output of the second n-bit register as an input A second absolute value calculating circuit that outputs an absolute value; a second triple value calculating circuit that receives an output of the second absolute value calculating circuit as an input and outputs a triple value; and the first triple value Output of Value Operation Circuit and Calculation of Second Absolute Value A first comparison circuit that receives an output of the circuit as an input; a second comparison circuit that receives an output of the first absolute value calculation circuit and an output of the second triple value calculation circuit; A determination circuit which receives the output of the comparison circuit, the output of the second comparison circuit, the most significant bit of the output of the first n-bit register, and the most significant bit of the output of the second n-bit register. A digital VCO circuit for extracting a VCO output having a phase resolution twice as high as a reference clock used as a reference for the operation of the first and second n-bit registers from the output of the determination circuit.