JP2760123B2 - Digital phase locked loop - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase locked loop circuit suitable for clock recovery of a digital modulation signal.

2. Description of the Related Art A conventional digital phase locked loop is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-92410. FIG. 5 is a block diagram for explaining the outline of the publication.

In FIG. 5, 301 is an A / D converter, 302 is delay means for one clock period, 303 is an arithmetic circuit, 304 and 307 are 3-input adders / subtracters, 305 is a multiplier for multiplying an input by a coefficient k, 306
Denotes a switch unit, and 309 denotes a circuit block including an adder 307 and a delay unit 308.

The operation of FIG. 5 will be described with reference to FIG. The waveform 200 in FIG. 6 is a reproduced waveform of the digital signal, and the sampling points 201 and 202 are sampling points at certain times. now,
If the amplitude at the sampling point 201 immediately before the intersection between the reproduced waveform of the digital signal and the reference level is S _i, and the amplitude at the sampling point 202 immediately after the intersection is S _{i + 1} , the following equation is established by the similarity of the triangle.

Where k is the sampling interval and x is the sampling point
The interval between the point where the straight line connecting 201 and 202 intersects the reference level and the sampling point 202 is used as an approximate value of the interval between the point where the reproduced waveform of the digital signal intersects the reference level and the sampling point 202.

Solving equation (1) for x gives: Now, assuming that the number of sampling points per cycle of a reproduced waveform of a digital signal is N, So, (However, the unit is phase deg). In this manner, the phase distance from the intersection between the digital signal reproduction waveform and the reference level to the sampling point can be obtained from the sample value of the sampling point of the reproduction waveform of the digital signal. This is realized by the circuit of the A / D converter 30 in FIG.
1, a delay means 302 and an arithmetic circuit 303. Although the reason will be described later, since the delay unit 303 wants the half cycle of the reproduced waveform of the digital signal to be 360 °, the numerator coefficient is 720 °.

 Next, the circuit block 309 will be described.

Now, if switch 306 is off, the output of 308 will be 360 °
Since (720 ° / N) is successively added by the addition of the remainder system, a sawtooth wave like 203 in FIG. 6 is obtained. Switch 3
When 06 is turned on and a certain value is input to the adder 307, the frequency of the sawtooth wave output from the delay means 308 decreases if the value is positive, and increases if the value is negative. When the switch 306 is turned on for a certain period and turned off again, the frequency of the sawtooth wave does not change, but the phase shifts by the value input during the turning on. Thus, the circuit block 309 is P
It operates as a VCO of the LL circuit (hereinafter, 309 is referred to as a VCO).

Further, the adder / subtractor 304 adds 180 ° to the phase of the input signal, outputs a value obtained by subtracting the phase of the output signal of the VCO 309, and operates as a phase comparator of the phase synchronization circuit. The reason for adding 180 ° to the phase of the reproduced waveform of the digital signal is to make the phase of the reproduced waveform of the digital signal 0 ° correspond to the phase of the output signal of the VCO 309 of 180 °. Thus, the phase relationship between the reproduced waveform of the digital signal and the output signal of the VCO 309 in the synchronized state is as shown in FIG. As can be seen from the figure, if the sign of the reproduced waveform of the digital signal is determined when the output signal of the VCO 309 changes from 360 ° to 0 °, it can be read correctly.

However, in the digital phase locked loop circuit described above, the output value of the adder / subtractor 304, which is a phase comparator, is adjusted by a coefficient unit and supplied to the VCO 309. Therefore, there has been a problem that the ability to follow the frequency change of the reproduced waveform of the digital signal is low.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems. By adding a frequency detecting means, it is possible to improve the followability to a change in the frequency of a reproduced waveform of a digital signal while suppressing the jitter component. It is intended to provide a circuit.

Means for Solving the Problems In order to achieve the above object, a digital phase locked loop of the present invention provides an A / D converter for sampling a reproduced waveform of a digital signal at a frequency exceeding a maximum value of a channel bit rate.
A D converter, an arithmetic circuit for calculating the position data of the intersection from the sample values of the sampling points before and after the intersection of the reproduced waveform and the reference level, and 360 ° divided by the number of samples per cycle of the reproduced waveform. Frequency detecting means for obtaining a reproduction phase value at a certain sampling interval from the position data of the intersection, a multiplier for converting the reproduction phase value at the sampling interval to a phase value by multiplying the position data at the intersection, A VCO unit that adds a reproduction phase value for each sample and performs cumulative addition in a 360 ° remainder system; and a phase comparison unit that outputs a difference between an output of the VCO unit and an output of the multiplier. The output of the VCO unit is input to the VCO unit and added together with the reproduction phase value at the sampling interval to vary the output of the VCO unit.

According to the present invention, the position data at the point where the reproduced waveform intersects with the reference level is replaced by the phase data based on one cycle of the reproduced waveform by the output of the frequency detecting means. Since it operates, the operating center frequency of the phase locked loop does not change even when the frequency of the reproduced waveform changes. For this reason, it is possible to improve the follow-up property to the frequency change of the reproduction waveform of the digital signal without lowering the jitter component suppressing property of the phase locked loop.

Embodiments Hereinafter, embodiments of a digital phase locked loop according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital phase locked loop circuit according to an embodiment of the present invention. In FIG. 1 and claim 1, 101 corresponds to the A / D converter, 113 corresponds to the arithmetic circuit, 105 corresponds to the frequency detecting means, and 104 corresponds to the multiplier.

In FIG. 1, 101 is an A / D converter, and 102 and 110 are 1
Clock period delay means, 103 is an arithmetic circuit, 104 is a multiplier, 105 is a frequency detector, 106 and 109 are adders, 107 is a coefficient unit, and 108 is switch means. This circuit is similar to the conventional digital phase detection circuit shown in FIG.
105 and a multiplier 104 are added. Further, a circuit obtained by removing the frequency detector 105 from the entire circuit is referred to as a phase synchronization circuit 112.

The operation of the digital phase locked loop of the present invention will be described below. For example, if there are four sampling points in one cycle of the reproduction waveform of the digital signal (N = 4), the reproduction waveform of the digital signal and the sampling state of the output signal of the VCO 111 are as shown in FIG.

At this time, the operation of the phase detection circuit is such that the sampling interval is Therefore, the phase position x of the sampling point 202 in FIG. Becomes

In addition, the operation of the VCO 111 adds 180 ° one after another in the adder 109 in the addition of the remainder system of 360 °, so that the output becomes a sawtooth wave which completes two cycles in one cycle of the reproduction waveform of the digital signal.

If the adder 106 adds 180 ° to the phase data of the sampling point of the reproduced waveform of the digital signal and subtracts the phase of the output signal of the VCO 111 to obtain the output of the phase comparator, the reproduced waveform of the digital signal becomes 0 °. 180 ° of the output signal of VCO111
Correspond to each other and are locked in a phase relationship shown in FIG.
In this way, the sample value at the sampling point of the reproduced waveform of the digital signal is correctly converted into phase data, and the output signal of the VCO 111 is synchronized with the reproduced waveform of the digital signal in a correct phase relationship.

Next, consider the case where the frequency of the reproduced waveform of the digital signal increases by 10%. At this time, the period of the reproduction waveform of the digital signal is reduced by 10%, so that the number N of samples per period is 3.6. Therefore, the sampling interval is And the phase data at the sampling point is Becomes In addition, the operation of VCO111 is 2
00 ° (= 720 ° / N) is successively added by the adder 109, and the output is a sawtooth wave that completes two cycles in one cycle (3.6 samples) of the reproduced waveform of the digital signal.

If the adder 106 adds 180 ° to the phase data of the sampling point of the reproduced waveform of the digital signal and subtracts the phase data of the output signal of the VCO 111 to obtain the output of the phase comparator,
The output signal of VCO111 is
180 ° corresponds to each other, and they lock in the phase relationship shown in FIG. In this way, the reproduction waveform of the digital signal is correctly converted into phase data, and the output signal of the VCO 111 is synchronized with the reproduction waveform of the digital signal in a correct phase relationship even if the frequency of the reproduction waveform changes.

As described above, if the value (720 ° / N) output from the frequency detector 105 is set to an appropriate value corresponding to the frequency of the reproduction waveform of the digital signal, the phase synchronization circuit 112 It can follow signals of various frequencies.

Next, an embodiment of the frequency detecting means 105 will be described with reference to FIG. FIG. 2 and claim 2 show that 414 is the first circuit, 4
01 corresponds to a subtractor, 411 corresponds to a first low-pass filter, 407 corresponds to a coefficient multiplier, and 415 corresponds to a coefficient correction circuit.

In FIG. 2, 401 and 405 are subtractors, and 402, 406, 407 and 412
Are coefficient units for applying the coefficients A, B, k, k to the inputs, respectively, 403, 40
9,413 is an adder, 404,410 is delay means for one clock period,
408 is a switch means. A circuit block 411 composed of 402 to 406 is a bilinear digital filter. This digital filter is used as a lag-lead type low-pass filter having the frequency characteristics shown in FIG. 3 as -1 <B <A <1. Further, since the frequency detector 105 is a loop having a delay means of one clock period inside 401 → 408 → 411 → 407 → 409 → 410 → 401, its input / output characteristic is a second-order low-pass filter. become.

The circuit shown in FIG. 2 is such that a digital filter 411 having a lag-lead type frequency characteristic is inserted into a PLL loop composed of 304 to 308 of the circuit shown in FIG. Therefore, the circuit shown in FIG.
It can follow an input signal in a wider frequency range than the primary phase locked loop shown in the figure.

Next, the inside of the digital filter 411 will be considered. The inputs of the adder 403 are the output of the switch 408 and the output of the delay means 404.Assuming that there is no output of the delay means 404, the output of the adder 403 becomes equal to the output of the switch 408. The circuit shown in FIG. 2 is a primary phase locked loop circuit. From this it can be seen that the output of the delay means 404 contains frequency information. In the steady state, the number of samples per cycle of the input signal is N. Now, when the frequency of the input signal changes and the number of samples per cycle changes to Na, the output of the delay means 404 is represented by X. Then, the following equation is established from the output sampling value interval of the VCO 414.

Since the output of the frequency detector 105 only needs to be (720 ° / N · a), the output of the delay means 404 is added to the coefficient unit 412 and the adder 41.
By performing the operation of 3, the output of the frequency detector 105 is obtained.

Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 4 and claim 3, 606 corresponds to the second low-pass filter.

In FIG. 4, 601 is an A / D converter, and 602 and 611 are 1
Clock period delay means, 603 is an arithmetic circuit, 604 is a multiplier, 605 is a frequency detector, 606 is a low-pass filter for smoothing the output of the frequency detector 605, 607 and 610 are adders, 609 is a coefficient unit, 608 Is switch means. Also, a phase synchronization circuit 612 is obtained by removing the frequency detector 605 and the low-pass filter 606 from the entire circuit. This circuit includes a low-pass filter 60 in the digital phase detection circuit shown in FIG.
6 is added. In this case, the S / N ratio of the reproduced waveform of the digital signal is poor, and the frequency detector 6
Even if the output of 05 varies, it can be smoothed by the low-pass filter 606, and a good value of the S / N ratio can be output to the phase locked loop 612, so that the safety of the circuit can be improved.

As described above, the digital phase-locked loop according to the present invention includes an A / D converter that samples a reproduced waveform of a digital signal at a frequency exceeding the maximum value of the channel bit rate, and an intersection between the reproduced waveform and a reference level. And an arithmetic circuit for obtaining the position data of the intersection from the sample values of the sampling points, and frequency detection for obtaining the reproduction phase value of the sampling interval by dividing 360 ° by the number of samples per cycle of the reproduction waveform from the position data of the intersection. Means,
A multiplier for multiplying the reproduction phase value of the sampling interval by the position data of the intersection, and outputting the position data of the point where the reproduction waveform crosses the reference level by one cycle of the reproduction waveform according to the output of the frequency detecting means. , And the main body of the phase-locked loop operates based on the phase data. Therefore, even when the frequency of the reproduced waveform changes, the operation center frequency of the phase-locked loop does not change. For this reason, it is possible to improve the follow-up property to the frequency change of the reproduction waveform of the digital signal without lowering the jitter component suppressing property of the phase locked loop.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a digital phase locked loop circuit of the present invention, FIG. 2 is a block diagram of a frequency detecting circuit according to claim 2 of the digital phase locked loop circuit of the present invention, and FIG. Frequency characteristic diagram of a bilinear digital filter,
FIG. 4 is a block diagram showing the configuration of a digital phase locked loop circuit according to the third aspect of the present invention, FIG. 5 is a block diagram showing the configuration of a conventional digital phase locked loop circuit, and FIG. FIG. 4 is a waveform diagram illustrating a phase relationship between output signals. 101 A / D converter, 102 delay means for one clock period, 103 arithmetic circuit, 104 multiplier, 105 frequency detector, 106 subtractor, 107 multiplier multiplier , 108 ……
Switch means, 109 ... Adder, 110 ... Delay means for one clock period.

Claims (3)

(57) [Claims] A digital signal reproduction waveform is sampled at a frequency exceeding a maximum value of a channel bit rate.
An A / D converter; an arithmetic circuit for obtaining position data before and after the intersection of the reproduction waveform from the A / D converter and the reference level; and a sampling interval of 360 ° divided by the number of samples per cycle of the reproduction waveform. Frequency detection means for obtaining a reproduction phase value from the intersection position data; a multiplier for converting the reproduction phase value at the sampling interval to a phase value by multiplying the intersection position data; and a reproduction phase value at the sampling interval. A VCO unit for adding and accumulating in a 360 ° remainder system for each sample, and a phase comparison unit for outputting a difference between an output of the VCO unit and an output of the multiplier, and an output of the phase comparison unit. A digital phase-locked loop, wherein the digital phase-locked loop is configured to be input to the VCO section and added together with the reproduction phase value of the sampling interval to vary the output of the VCO section. Road. 2. The frequency detecting means detects a reference phase value of a sampling interval in a reproduction waveform of a reference bit rate.
A first circuit for performing cumulative addition in a 360 ° remainder system, a subtractor for subtracting an output of the first circuit from position data of an intersection which is an input of the frequency detection means, and an output of the subtractor as an input. A first low-pass filter having a register for storing frequency information therein, a frequency information output terminal, and a filter output terminal; and a coefficient unit connected to a filter output terminal of the first low-pass filter, The output of the coefficient unit is input to the first circuit, added to the reference phase value of the sampling interval, and the reproduction phase value of the sampling interval is obtained by the coefficient correction circuit connected to the frequency information output terminal of the first low-pass filter. 2. The digital phase-locked loop according to claim 1, wherein said digital phase-locked loop is configured to output. 3. The digital phase-locked loop according to claim 1, wherein a reproduction phase value at a sampling interval, which is an output of the frequency detection means, is passed through a second low-pass filter and then multiplied by intersection position data.