JPH04137914A - Pll synthesizer - Google Patents

Abstract

PURPOSE:To attain high speed frequency control and to obtain a stable output without spurious radiation by comparing a reference phase with a feedback phase and driving a voltage controlled oscillator depending on an analog quantity equivalent to a phase difference. CONSTITUTION:A phase between a reference phase signal thetar obtained by a phase accumulator 1 and a phase of a feedback phase signal thetav being the output signal of a phase accumulator 6 are compared by a phase comparator 2, from which a phase error signal thetak is obtained. Moreover, a correction circuit 3 corrects an output range to be >>-pi, pi] to obtain a correct phase error signal thetak'. The phase error signal does not include any component other than the DC component required for VCO control and since the increment of the phase of the phase accumulators 1,6 is formed variable by data M, L given externally, then no normalizing circuit is required, then a round-off error for normalization is not caused and the output of a voltage controlled oscillator 5 is changed widely.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a P
Regarding LL synthesizer.

<Prior art> In a conventional PLL synthesizer, in order to extract a phase error signal for controlling the output frequency of a voltage controlled oscillator (hereinafter referred to as VCO), phase comparison is performed by performing multiplication between a reference signal and a feedback signal. was being carried out.

However, since the phase comparison is performed by multiplication, a high frequency component is generated in addition to the phase comparison component.

In order to suppress this high frequency component, an LPF is required within the loop. For this reason, it is impossible to make the frequency switching time shorter than the time constant of the LPF in the loop, and is usually quite slow, ranging from several + m5 ec to several sec. If this is made faster, the frequency stability of the VCO output signal will deteriorate. Conversely, if the bandwidth of the LPF is narrowed, a stable output can be obtained, but the time constant becomes larger and the frequency switching time becomes longer.

Regarding digital PLL synthesizers that take these problems into consideration, IEICE Transactions 1990, 2
Suggestions are made on page 95 of the monthly issue.

This proposal is a hybrid PLL synthesizer in which the low frequency part other than the VCO is replaced with digital signal processing (DSP). That is, the phase error component is detected by subtracting the phase component of the reference signal given by signal processing and the order [11 component] of the feedback signal. Therefore, high frequency components, which were unavoidable in the past, are not generated. As a result, the LPF for removing unnecessary high frequency components becomes unnecessary, and the response characteristics of the loop are improved.

<Problems to be Solved by the Invention> In this proposal, frequency switching is realized by switching the modulo value N of the modulo N frequency counter and the N of the 1/N multiplier. The 1/N multiplier is necessary to normalize the modulo value N of the modulo-N frequency counter because it changes depending on the modulo value or the resolution of the phase being compared by the phase comparator when the modulo value N is switched. It is. For this reason, the proposed method requires a 1/N multiplier for normalization in addition to the modulo N frequency counter.

However, since normalization is performed using a 1/N multiplier, there is a problem in that rounding errors occur during normalization.

The present invention has been made to solve the above-mentioned problems, and its purpose is to realize a PLL synthesizer that can perform frequency control at high speed and obtain stable output without generating spurious. do.

Means for Solving the Problems> The present invention to solve the above problems detects a phase error component by subtracting a reference phase signal and a feedback phase signal, and drives a voltage controlled oscillator based on this phase error component. PLL
This synthesizer includes reference phase signal generation means configured to vary the phase increment, and feedback phase signal generation means configured to vary the phase increment.

In the PLL synthesizer of the present invention, the reference phase calculated in the phase accumulator using the reference signal as the clock is compared with the feedback phase calculated by the phase accumulator using the output of the voltage controlled oscillator as the clock, or by dinotal subtraction. The voltage controlled oscillator is driven by an analog value corresponding to the phase difference. As a result, the output frequency of the voltage controlled oscillator or the digital PL
L controlled. In this case, since the double-phase accumulator is configured to be variable in increments of 01 or 01 depending on the data obtained from the outside, a separate circuit for normalization is required. It becomes possible to vary the output of the voltage controlled oscillator over a wide range without causing rounding errors.

<Examples> Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic structure of an embodiment of the present invention.

In this figure, 1 is a phase accumulator that uses the reference signal EC as a clock to generate a reference phase signal whose phase increases based on external data N1, and 2 is a phase that compares the phases of the reference phase signal θr and the feedback phase signal θV. comparator,
3 is a phase error signal θk by supplementing the phase comparison result θk
Complementary 1F circuit that generates
5 is a D/A converter that converts `` into an analog value, and 5 changes the oscillation frequency based on the phase error signal converted into an analog value.V6O13 uses the output of VCO5 as a clock, and the phase increases based on the external pig L. 7 is a sampler for matching the output signal of the phase accumulator 6 with the reference phase signal θr.

Here, the general operation of the entire apparatus of this embodiment will be explained.

A phase comparison is made between the reference phase signal θ' obtained from the phase accumulator and the feedback phase signal θV (Fig. 2), or the phase comparator 2 performs a phase error signal θk (θ = θr-
θV...■) is obtained. Here, the phase component θ
Since both θV and θV are periodic functions from 0 to 2π, if the above equation 0 is used, a phase error of ±2π will occur each time θV or θr is converted from 2π to 0 (Fig. 3 ■ to ■). Therefore, by the correction circuit 3, θk −((θk +π) mod2πl −
By performing the calculation π, the output range is corrected to U-π, π, and a correct phase error signal θ is obtained (FIG. 4).

This phase error signal contains only the C component necessary for VCO control, and does not contain any harmonics unlike the phase comparator of a conventional PLL synthesizer. Therefore, a filter for removing harmonics is not required. This allows the PLL
frequency switching time becomes shorter.

Next, the output signal of the VCO 5 is converted into a feedback phase signal θν by a phase accumulator 6 and a sampler 7.

Incidentally, by sampling L/fc by the sampler 7, θr and θV are synchronized.

Here, the reference phase signal θr generated by the phase accumulator 1 is as follows.

θr - (2π/2N)M (t/lc) where, N is the number of bits of the output of the phase accumulator tc is the counting period M is the setting data, Q<M<2N Also, the feedback phase generated by the digit + 11 accumulator 6 The signal θV is as follows. θν゛=(2π/2
N)L (t/lν) Here, tv is sample link data whose period is equal to the period of the VCO output signal, and 0<L<2N.

Here, if the reference signal and the VCO output are synchronized,
From θ “−θ■, fc(M/L)fc, so the PL according to this proposal is
The output of the L sensor has the following characteristics.

Lowest frequency: fc/L.

Maximum frequency: (2N-1)fc/L.

Step: fc/L...■(
However, L=1 to 2 N -,> Below, an example of operation in the case of N=2 (2 focal points) will be shown.

(1) When M-1 and L-1, the amount of phase increase (M) in phase accumulator 1 is:
For one period (tc), 1 ((2π/22) /ra
d) (see Figure 5).

The amount of phase increase (L) in the phase accumulator 6 is 1-((2π/22)/
rad) (see Figure 6).

Further, the sampler cycle (cycle for comparing phases) at this time is tc.

Note that the output frequency fv in this case is fv
-fc.

(2) When M-1 and L-2: The amount of increase in phase (M) in phase accumulator 1 is
1 per period (tc) (see FIG. 7).

The amount of phase increase (L) in the phase accumulator 6 is:
2 per period (tv) (see Figure 8).

Further, the sampling period (period for comparing phases) at this time is 2tc (-tv).

Note that the output frequency fv in this case is fv
= (1/2)fc.

(3) M=3. In the case of L-1, the amount of increase (M) in the Fth place in phase accumulator 1 is 3 per cycle (tc) (see Figure 9, 11?
1).

The amount of phase increase (L) in the phase accumulator 6 is:
1 per period (tv) (see FIG. 10).

Further, the sampling period (period for comparing phases) at this time is tc (=3tv).

Note that the output frequency fv in this case is fv
-3fc.

(4) When M-3L-2: The amount of increase in phase (M) in phase accumulator l is
3 per period (tc) (see FIG. 11).

The amount of phase increase (L) in the phase accumulator 6 is:
2 per period (tv) (see Figure 12).

Further, the sampler cycle (cycle for comparing phases) at this time is 2tc (=3tν).

In addition, the output frequency fv in this case is fv
= (1/2)fc.

As explained in detail above, by generating the reference phase signal and the feedback phase signal using the digit accumulator,
A special circuit for normalization is no longer required, rounding errors that occur during normalization are eliminated, and frequency switching becomes easier.

Therefore, according to the PLL synthesizer of this embodiment, frequency control can be performed at high speed and stable output can be obtained.

Incidentally, as shown in FIG. 13, the output frequency fv is frequency-mixed by the local oscillation frequency f mix to obtain fv - (=
A similar effect can be obtained by converting to fv −fmix ).

<Effects of the Invention> As explained in detail above, in the present invention, the phase error component is detected by subtracting the reference phase signal and the feedback phase signal, and the P that drives the voltage controlled oscillator based on the second phase error component is
The LL synthesizer is provided with a reference position signal generating means configured to have a variable phase increment, and a feedback phase signal generating means configured to have a variable phase increment.

As a result, the reference phase calculated in the phase accumulator and the feedback phase calculated by the phase accumulator are compared by digital subtraction, and the voltage controlled oscillator is driven by an analog value corresponding to the phase difference. As a result, the output frequency of the voltage controlled oscillator is digitally PLL controlled. In this case, since the dual-phase accumulator is configured to have a variable phase increment based on externally supplied data, it does not require a normalization circuit, so there is no rounding error for normalization, and the voltage It becomes possible to vary the output of the controlled oscillator over a wide range.

Therefore, it is possible to realize a PLL synthesizer in which frequency can be controlled at high speed and stable output can be obtained without generating spurious signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a PLL synthesizer according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of phase comparison of the embodiment shown in FIG. 1, and FIG. 3 is an implementation diagram showing the implementation shown in FIG. 1. FIG. 4 is an explanatory diagram of the operation of the PLL synthesizer of the example shown in FIG. 1. FIG. 5 is an explanatory diagram of the reference phase of the PLL synthesizer of the embodiment shown in FIG. 1. , FIG. 6 is an explanatory diagram of the phase of the feedback signal of the PLL synthesizer of the embodiment shown in FIG. 1, FIG. 7 is an explanatory diagram of the reference phase of the PLL synthesizer of the embodiment shown in FIG. 1, and FIG. is an explanatory diagram of the phase of the feedback signal of the PLL synthesizer of the embodiment shown in FIG. 1, FIG. 9 is an explanatory diagram of the reference phase of the PLL synthesizer of the embodiment shown in FIG. Figure 11 is an explanatory diagram of the reference phase of the PLL synthesizer of the embodiment shown in Figure 1, Figure 2 is an illustration of the phase of the feedback signal of the PLL synthesizer of the embodiment shown in Figure 1, An explanatory diagram of the phase of the feedback signal of the PLL synthesizer of the embodiment. FIG. 13 is a configuration diagram showing the configuration of another embodiment of the present invention. 1..Phase accumulator 2..Phase comparator 3. Correction circuit 4.D/A converter 5.■CO 6..Phase accumulator 7 Sunbrar

Claims (1)

[Scope of Claims] A PLL synthesizer that detects a phase error component by subtracting a reference phase signal and a feedback phase signal, and drives a voltage controlled oscillator based on this phase error component, the phase increment being configured to be variable. What is claimed is: 1. A PLL synthesizer comprising: a reference phase signal generating means having a reference phase signal generating means; and a feedback phase signal generating means having a variable phase increment.