JP2669068B2 - PLL circuit - Google Patents

Description

The present invention relates to a PLL used for data extraction on the receiving side of a system that transmits information by self-clocking.
It is related to the circuit.

2. Description of the Related Art A PLL circuit is a circuit that synchronizes the phase with an input signal.

The conventional PLL circuit will be described below with reference to FIG.

First, the input signal is sampled by the comparator 1.

Next, the phase comparator 2 compares the phase of the sampled signal with the output of the voltage oscillation controller (VCO) 4 and outputs an error signal. The method of feeding back the output of the VCO to the phase comparator in this way is called self-clocking, and the output of VCO4 corresponds to the clock.

Then, the low-pass filter (LPF) 3 converts this error signal into a DC voltage.

Finally, the oscillation frequency of the output of the VCO 4 is controlled by the DC voltage.

However, the conventional PLL circuit cannot be used for a digital signal modulated by NRZI (a method of inverting and outputting a signal when the original data is "1"). There was a problem.

In other words, the PLL circuit compares the phase of the edge (change point) of the signal with the phase of the clock, but the edge of the signal modulated by NRZI corresponds to the time when the data is inverted.

Therefore, the data transmission rate is a fraction of the clock
However, there was a problem that the phase was judged to be in sync and it was not possible to get out of that state.

On the other hand, a method of solving this problem can be considered by limiting the frequency at which the PLL circuit can be phase-locked. Furthermore, this method limits the signals that can be phase-locked.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a PLL that can obtain a signal that is accurately phase-locked to a clock while obtaining a signal that can be phase-locked as widely as possible.

Means for Solving the Problems The present invention provides a PLL circuit that outputs an output signal that is phase-synchronized with an input signal that changes at least once during a period from a period x to a period y. Controls the oscillation frequency of the voltage controlled oscillator to be high,
When the input signal is larger than the period y, the voltage control oscillator is controlled so that the oscillation frequency becomes low.

Action The PLL circuit of the present invention can cancel the phase synchronization when the input signal is an integral multiple of the clock.

Embodiment FIG. 1 shows a PLL circuit according to an embodiment of the present invention.

As an example, the case of using it for a CD player will be described.

In this case, in general, Runlengh-Limited-Code (converted so that data "1" is always included in a certain period; hereinafter referred to as RLC) is NRZI-modulated and input to the PLL circuit. In the CD player, conversion is performed so that at least data "1" is included between 3T and 12T.
The RLC is used because the phase comparison cannot be performed when the data “0” is too continuous due to the characteristics of NRZI modulation.

Since the comparator 1, the phase comparator 2, the LPF3, and the VCO4 are the same as those in the conventional PLL circuit, the description thereof will be omitted.

First, the hysteresis comparator 5 is for removing noise. It outputs the data “1” and then the data “0”, and the data “0” and then the data “1”. The level of the input signal to be output is different. That is, once the data "1" is output, the data "0" is not output even with a little noise, and it plays a role of noise removal.

Next, the inversion detector 6 detects the case where the phase difference from the clock output from the VCO 4 is 2T or less.

Further, the inversion detector 7 detects a case where the phase difference from the clock output from the VCO 4 is 12T or more.

The outputs of the inversion detectors 6 and 7 are held by timers 8 and 9 for a certain period of time, and when the phase difference from the clock is 2T or less, control is performed so that the frequency of VCO4 increases.
If it is equal to or greater than T, control is performed so that the frequency of VCO4 decreases. Since the outputs of the inversion detectors 6 and 7 are instantaneous signals, the timers 8 and 9 have a role of extending the pulse to a fixed time.

Specifically, the inversion detectors 6 and 7 detect signals by sampling the input signal with the clock of the VCO4.

As a result, the oscillation frequency of the VCO 4 is always kept between 3T and 11T, so that it is possible to solve the problem that the phases are synchronized with each other by an integral multiple of the clock.

Although the VCO 4 has three frequency control inputs in the present embodiment, the outputs of the timers 8 and 9 may be added to or subtracted from the LPF 3 output.

Further, the PLL circuit of the present invention is not limited to a CD player and can be widely applied.

Further, as shown in FIG. 2, the hysteresis comparator 5 only needs to remove noise.

EFFECTS OF THE INVENTION According to the present invention, it is possible to obtain a phase-synchronized signal with high accuracy even for an NRZI-modulated signal.

[Brief description of the drawings]

1 is a PLL circuit according to an embodiment of the present invention, FIG. 2 is a PLL circuit according to another embodiment of the present invention, and FIG. 3 is a conventional P circuit.
LL circuit, Fig. 4 is an operation diagram of the PLL circuit, Fig. 5 is a timing diagram showing that the phase is synchronized even if the transmission speed is reduced to 1/2, and Fig. 6 shows the inversion exceeding the maximum and the inversion below the minimum. FIG. 7 is a timing chart for detection, and FIG. 7 is a diagram showing the occurrence of a malfunction when the input signal contains noise. 1 ... comparator, 2 ... phase comparator, 3 ... LPF,
4 ... VCO, 5 ... Hysteresis comparator, 6, 7
…… Reversal detector, 8, 9 …… Timer.

Claims (2)

(57) [Claims] 1. A PLL circuit that outputs an output signal that is phase-synchronized with an input signal that changes at least once during a period from x to y, wherein the PLL circuit includes: a comparator that samples an input signal; A phase comparator that compares the phase of the output signal of the comparator with the clock; a low-pass filter that converts the output signal of the phase comparator into a DC voltage; and a transmission frequency of the output signal that is controlled based on the output voltage of the low-pass filter. A voltage-controlled oscillator, wherein the output signal is fed back as a clock of the phase comparator, and a first inversion for outputting a constant voltage when the input signal is less than a period x with respect to the clock. A detector, a second inversion detector that outputs a constant voltage when the input signal is greater than the period y, and a voltage control oscillator And an adder / subtractor which is provided in the previous stage and adds the voltage from the first inversion detector and subtracts the voltage from the second inversion detector.
PLL circuit. 2. A PLL circuit that outputs an output signal that is phase-synchronized with an input signal that changes at least once during a period from x to y, wherein the PLL circuit includes: a comparator that samples an input signal; A phase comparator that compares the phase of the output signal of the comparator with the clock; a low-pass filter that converts the output signal of the phase comparator into a DC voltage; an output voltage of the low-pass filter, a frequency increase control terminal, and a frequency decrease terminal. A transmission frequency of an output signal is controlled based on the input voltage of the voltage-controlled oscillator, and the output signal is feedback-inputted as a clock of the phase comparator; and the input signal is less than a period x with respect to the clock. When a constant voltage is applied to the frequency increasing control terminal,
And the second inversion detector that applies a constant voltage to the frequency reduction control terminal when the input signal is longer than the period y.