JPH09297969A - Optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical disk device which enables semiconductor integration by digitizing the whole and can simply cope with the variation of operational speed. SOLUTION: Thus device has a digital demodulation circuit 26 to which a signal reproduced and binarized from an optical disk in which a digital modulation signal is previously recorded is supplied and which performs digital demodulation, a digital phase locked loop circuit 30 generating a clock signal phase-synchronizing with a demodulated signal outputted by the digital demodulation circuit 26, and a digital servo circuit 34 performing the rotation control of an optical disk 20 so that frequency deviation and phase deviation between a clock signal and a reference clock signal are compensated. Thus, semiconductor integration of each circuit can be simply performed by digitizing the whole circuits of the modulation circuit 26, the PLL circuit 30, and the servo circuit 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device, and more particularly to an optical disk device for recording / reproducing a recordable optical disk.

[0002]

2. Description of the Related Art A recordable compact disc system (CD-
R). In this CD-R, synchronization information and address information for rotation control are recorded as a wobble signal by forming the groove in a meandering manner.

This wobble signal is a modulation signal BIDAT of a bi-phase code which is information such as a disc address.
The signal is FSK-modulated by A, and the WBL frequency f _WBL is 22.05 ± 1 kHz when the disk rotation is at the specified linear velocity.
It is. The ATIP signal, which is information such as the above address, is composed of a synchronization signal (ATIP _syc ), an address, and an error detection code CRC, and the repetition frequency of the synchronization signal is 75 Hz.

An example of an optical disk device for recording / reproducing such an optical disk is disclosed in Japanese Patent Application Laid-Open No. 5-225580.

[0005]

In the conventional optical disc apparatus, the reproduction signal reproduced by the optical head is subjected to signal processing using an analog circuit to control the rotation of the optical disc. For example, as a demodulation circuit for FSK demodulating a wobble signal to obtain a BIDATA signal as a modulation signal, there is a circuit shown in FIG. 8 as an example.

In FIG. 8, the wobble signal coming into the terminal 10 is supplied to the phase comparator 12 and compared in phase with the output signal of the VCO (voltage controlled oscillator) 14. The phase error signal obtained here is supplied to the low-pass filter 16, the unnecessary high-frequency component is removed, and is output from the terminal 20 as an FSK demodulated signal and is also supplied to the multiplier 22. The signal multiplied by the loop gain K in the multiplier 22 is supplied to the VCO 14.

The transfer function of the above low-pass filter 16 is F
When (S) = 1 + ω _P / S (where ω _P is the cutoff frequency), the FSK demodulation characteristics depend on ω _P. Here, if the operating speed changes to 1 × speed, 2 × speed, and 4 × speed,
Wobble signal frequency is 22.05 ± 1kHz, 44.1 ± 2kHz
z, 88.2 ± 4 kHz. Therefore, in the conventional circuit, the cutoff frequency of the low-pass filter 16 must be changed in accordance with the change in the operating speed, and in addition to this, there is a problem that the circuit constant must be optimized in order to stabilize the loop. there were.

Further, in the case of integrating the whole of an analog circuit into a semiconductor, it is difficult to set the circuit element constant with high accuracy, and the circuit element requiring the accuracy must be externally attached, so that the integration is difficult. There was a problem that it was difficult. The present invention has been made in view of the above points, and an object of the present invention is to provide an optical disk device that can digitize the whole and can be integrated into a semiconductor and can easily cope with a change in operating speed.

[0009]

According to a first aspect of the present invention, there is provided a digital demodulation circuit which performs digital demodulation by supplying a reproduced and binarized signal from an optical disc on which a digital modulation signal is recorded in advance. A digital phase-locked loop circuit that generates a clock signal that is phase-synchronized with the demodulation signal output from the digital demodulation circuit,
And a digital servo circuit for controlling the rotation of the optical disc so as to correct the frequency shift and the phase shift between the clock signal and the reference clock signal.

By using all the demodulation circuit, PLL circuit, and servo circuit as digital circuits in this way, semiconductor integration of each circuit is simplified. According to a second aspect of the present invention, in the optical disk device according to the first aspect, the digital demodulation circuit and the digital servo circuit are integrated on a single semiconductor chip.

By thus integrating all the circuits on the semiconductor chip, the device can be downsized. Claim 3
In the optical disc device according to claim 1 or 2, the digital demodulation circuit measures an edge interval of the supplied binarized signal by using a master clock having a frequency according to an operating speed, The demodulated signal of the level based on the value is output.

Since the edge interval of the binarized signal is measured by using the master clock in this way, the frequency of the master clock can be changed according to the operating speed to easily deal with the change in the operating speed. it can.

[0013]

1 shows a block diagram of an embodiment of the device of the present invention. In the figure, the optical disk 20 is rotated by a spindle motor 22. The optical pickup 24 reproduces the wobble signal shown in FIG. 2B from the disk 20 and outputs the WBL signal shown in FIG.

The above-mentioned WBL signal is supplied to the digital FSK demodulation circuit 26, and BIDAT as shown in FIG.
The A signal is demodulated and the sync signal (ATIP _syc ) is detected. The digital PLL circuit 30 is a digital FS
A clock signal synchronized with the BIDATA signal supplied from the K demodulation circuit 26 is generated and supplied to the switch 32.
The switch 32 selects the WBL signal reproduced at the start, and when the rotation of the optical disk 20 becomes stable, the digital PL
The clock signal output from the L circuit 30 is selected and supplied to the digital spindle servo circuit 34. The digital spindle servo circuit 34 controls the rotation of the spindle motor 22 on the basis of a signal obtained by dividing the WBL signal supplied from the switch 32 by 1 / 3.5, or a clock signal and a synchronization signal from the digital FSK demodulation circuit 26. Make sure that the line run rate of 20 is constant.

The above digital FSK demodulation circuit 26, digital PLL circuit 30, switch 32, and digital spindle servo circuit 34 all perform digital processing and are integrated on a semiconductor chip 36. First,
The principle of the digital demodulation circuit 26 will be described. The digital demodulation circuit 26 is supplied with the WBL signal reproduced by the optical pickup 24 and binarized. This WBL signal (FSK modulated signal) Vi (t) is expressed by the following equation.

Vi (t) = A ₀ cos (ωct + ΔΩ∫
Vs (t) dt + ψ) where ωc is the carrier frequency, ΔΩ is the modulation depth, and Vs
(T) is a modulation signal, and ψ is an initial value. Here, the instantaneous phase angle φ (t) is represented by the following equation: φ (t) = ωct + ΔΩ∫Vs (t) dt + φ The modulated signal Vs (t) can be obtained from this instantaneous phase angle φ (t). It is FSK demodulation. By the way, φ (t) = (2
The time tn that satisfies n-1) π / 2 is equivalent to the phase angle when Vi (t) = 0. Vi in digital circuit
It is easy to detect (t) = 0, the phase φ (n) at the time t is obtained, and the differential value x (n) = φ (n) −φ
The angular frequency can be obtained by obtaining (n-1).

That is, X obtained by Z-transforming the function X (n)
(Z) = Φ (z) (1-z ⁻¹ ) where X (z) is Φ
Since it represents the derivative of (z), the angular frequency is obtained. That is, Vs (t) is obtained from the equation of dφ (t) / dt = ωc + ΔΩVs (t). Practically, the frequency of the clock for counting the phase angle φ (n) is sufficiently high, and if it can be considered that there is no error due to sampling error, then FSK
It can be demodulated.

FIG. 3 shows a block diagram of an embodiment of the digital demodulation circuit 26. In FIG. 2, the terminal 40 is shown in FIG.
The WBL signal as shown in (1) comes in and is supplied to the edge detector 42. The WBL signal has an operating speed of 1x and a frequency of 22.0.
5 ± 1kHz, frequency is 44.1 ± 2kHz at double speed
And the frequency is 88.2 ± 4 kHz at 4 × speed. Also,
The system clock CLK coming in from the terminal 44 has a frequency of 8.64 MHz at 1x speed and a frequency of 17.29 MHz at 4x speed.
It is 34.57 MHz at double speed.

The edge detector 42 uses the system clock CL
The rising edge of the WBL signal is detected by using K and supplied to the counter 46, the register (REG) 48, and the timing generator 50, respectively. The counter 46 is reset to zero by the rising edge detection signal, then counts up the system clock and supplies the count value to the register 48. The register 48 stores the count value when the rising edge detection signal comes in. That is, the register 48 stores a count value representing the cycle of the WBL signal, that is, x (n) =
The value of φ (n) −φ (n−1) is stored.

Further, the timing generator 50 is synchronized with the rising edge detection signal of the WBL signal and has timing signals Ta, Tb and timing signals Sa, Sb, S having different phases.
Generate each c. On the other hand, the timing generator 52 outputs the timing signals Ta ₁ and T ₁ from the system clock CLK.
b ₁ , Tc ₁ , Ta ₄ , Tb ₄ , Tc ₈ , Td ₈ , Te
Generates ₈ each. Here, the subscripts a, b, c, d, and e represent the output timing, where a is the earliest, e is the latest,
Subscript 1 is 1x speed and frequency 22.05 kHz, subscript 2 is 1x speed and frequency 88.20 kHz, subscript 4 is 1x speed and frequency 176.4
If the operating speed is 2 × speed or 4 × speed, these frequencies will also be 2 according to the frequency of the system clock.
It becomes 4 times.

The count value stored in the register 48 is 196 ± α (where α is several tens) during normal operation. This count value is calculated by the comparator 54 and the multiplexer (MU).
X) 56. The comparator 54 generates a low-level selection signal when the count value of the register 48 is within the range of, for example, 100 to 300, and a high-level selection signal outside the range, and supplies the selection signal to the multiplexer 56. The previous count value output from the register 58 is also supplied to the multiplexer 56.
When the selection signal output by is low level and the count value of the register 48 is within the normal operation range, the output value of the register 48 (the value obtained this time) is selectively output. On the other hand, if the selection signal is at the high level and the count value is outside the normal operation range, the output value of the register 58 (the value obtained last time) is selectively output.

The output value of the multiplexer 56 is the register 5
8 and the output value of the register 58 is directly supplied to the multiplexer 60 and is also supplied to the multiplexer 60 through the register 62. The registers 58 and 62 respectively store different timing signals Ta and Tb.

The decoder 64 decodes the values of the timing signals Sa, Sb, Sc at the time when the timing signal Ta ₄ is supplied to the multiplexer 60 and registers 58, 62 in the multiplexer 60.
Which of the above is selected is determined. According to this determination, the count value output from the multiplexer 60 is stored in the register 66 at the incoming timing of the timing signal Tb ₄ , from which the digital low pass filter (LPF) 68 is stored.
And the threshold generation circuit 70. Register 5 above
8, 62, multiplexer 60, decoder 64 is WBL
Timing conversion from the timing synchronized with the signal to the timing synchronized with the master clock CLL is performed.

The digital low-pass filter 68 removes the abrupt fluctuation component of the supplied count value and removes it from the comparator 7.
Feed to 2. The threshold value generation circuit 70 averages the count values of several tens to several hundreds of times in the past, generates a threshold value, and supplies it to the adder 74. When the optical disk is rotating at a predetermined linear velocity, the threshold value is a value near 196. Also,
Hysteresis generator 76 is BISK of FSK demodulation output.
When the A signal is at the high level, the BIDATA signal goes to the low level next time, so the count value should be lowered, and when the BIDATA signal is at the low level, the value of + β is generated in the opposite. However, β is a value of about 10 or less.

The adder 74 sets a hysteresis in the above threshold and supplies it to the comparator 72 as a comparison reference value. The comparator 72 compares the count value of the output of the low-pass filter 68 with the comparison reference value, and determines whether the former is the latter or more (higher when it is higher) or lower than the latter (low level when it is lower). The two types of comparison results are supplied to the multiplexer 80. The reason why the count value of the output of the low-pass filter 68 is compared with the threshold value obtained by averaging is to remove the DC component due to ωc and the DC component due to noise, and the addition of hysteresis improves noise resistance. This is to allow it.

The multiplexer 80 is the B of the FSK demodulation output.
When the IDATA signal is high level, the comparator 72
A comparison result of whether the output count value is less than or equal to a threshold value is selected, and when the BIDATA signal is at a low level, a comparison result of whether the output count value of the comparator 72 is greater than or equal to the threshold value is selected and the D-type flip-flop is selected. Supply to 82.
The flip-flop 82 latches the comparison result with the timing signal Tc ₈ and outputs it as an FSK demodulated output, that is, a BIDATA signal from the terminal 84.

FIG. 4 shows a digital PLL circuit 30 of the present invention.
1 shows a block diagram of one embodiment. In the figure, the terminal 140 receives the BIDATA signal as shown in FIG. 5A and is supplied to the edge counter 142. Edge counter 142
Resets the rising and falling edges of the BIDATA signal and then counts the system clock coming from the terminal 144 to measure and output the edge interval. The system clock frequency is also changed in conjunction with 1 time, 2 times, and 4 times in response to changing the operating speed of the disk 20 to 1 × speed, 2 × speed, and 4 × speed. Also, the number of system clock pulses in the pulse width 1T of the BIDATA signal is 686 as standard. As a result, the edge counter 142 has a pulse width of 1T, a count value of 686, a pulse width of 2T, a count value of 1372, a pulse width of 3T, and a count value of 205 as standard.
It becomes 8.

The 1T generating circuit 146 is the edge counter 14
It is determined whether or not the count value (maximum value) immediately before the count value supplied from 2 becomes 0 is 686 ± α (where α is a value of several tens) or 1372 ± 2 · α. If the maximum value is in the range of 686 ± α, the maximum value is held as a value of 1T, and the maximum value is 1372 ± 2 · α.
In the range of, the half value of the maximum value is held as the value of 1T. That is, in the 1T generation circuit 146, BIDATA
The pulse widths 1T and 2T of the signal are detected and a value of 1T is generated from them, and the pulse width 3T of the BIDATA signal is ignored. The 1T value in the vicinity of the value 686 output from the 1T generating circuit 146 is used as the edge interval value by the adder 14
8 and the multiplier 150, respectively.

The adder 148 adds the constant −343 supplied from the constant generator 152 to the value of 1T in order to reduce the number of bits and supplies it to the digital low pass filter 154. The digital low pass filter 154 removes the abrupt fluctuation component of the supplied value and supplies it to the adder 156. Adder 15
In step 6, the constant 343 supplied from the constant generator 158 is added to obtain a value of 1T, and then the value is supplied to the adder 160. The adder 160 adds the phase error correction values and supplies the corrected 1T value to the NCO (numerical control oscillator) 162.

The NCO 162 is supplied with the system clock from the terminal 164. The clock shown in FIG. 5B rises when the system clock is counted and the count value becomes 1T from the adder 160. Generates a signal and resets the count value. This clock signal is output from the terminal 166 and is also supplied to the latch circuit 168.

The latch circuit 168 has an edge counter 142.
Is supplied with the count value output by the latch circuit 1
68 latches the count value at the rising edge of the clock signal supplied from the NCO 162 and supplies it to the subtractor 170. However, the latch circuit 168 latches only when the rising edge of the clock signal first comes in from the edge of the pulse width 1T, 2T, 3T of the BIDATA signal.
This is because latching is not performed at the rising edges of the first and third clock signals.

In addition to this, the subtractor 170 has a 1T generating circuit 1
A value obtained by multiplying the 1T value output by 46 by ½ by the multiplier 150 is supplied as a reference value, and the subtractor 170 subtracts the reference value from the value output by the latch circuit 168 to obtain the phase error value. The result is supplied to the integrator 172. Like this one
As shown in FIG. 5A, the standard value is 1/2 of the value of T.
As shown in (B), the rising edge of the clock signal is BIDAT.
This is because it is at the center position of the pulse width 1T of the A signal.

The integrator 172 proportionally integrates the phase error value. The integrated value is 1 / K in the multiplier (K is a real number greater than 1)
Is multiplied by to obtain a phase error correction value, which is supplied to the adder 160. Thus, in the 1T generator 146, BIDAT
A value of 1T is generated only from the pulse widths 1T and 2T of the A signal, and the pulse width 3T of the BIDATA signal is not used. Repetition frequency 75 Hz (1 in BIDATA signal
Sync signal (ATIP _syc ) is 3T, 1T,
It is a pattern of 1T and 3T, and 3T in the 1T generator 46.
Since the pattern is not used, the output value of the 1T generator 146 is not mixed with the 75 Hz component of the synchronizing signal, and the stability of the clock signal is improved.

From the 1T generation circuit 146 to the adder 14
8, the digital low-pass filter 154, the frequency system of the path of the adder 148, the multiplier 150, and the latch circuit 16
Since the phase system of the path from 8 to the adder 170, the integrator 172, and the multiplier 174 is provided, and the adder 160 generates the clock signal by the frequency system and the phase system, a stable clock signal synchronized with the BIDATA signal can be generated. . Further, since the present embodiment is entirely composed of digital circuits, it is more resistant to fluctuations in ambient temperature and power supply voltage than analog circuits, and external circuits can be eliminated when the semiconductor is integrated. Further, the operating speeds of 1 × speed, 2 × speed, and 4 × speed can be supported by simply changing the frequency of the system clock supplied from the terminals 44 and 64. Further, since the operation is based on the count value of the edge counter 42, the linearity is good and the capture range of the phase lock operation is wide.

FIG. 6 shows a block diagram of an embodiment of the digital spindle servo circuit. In the figure, a clock signal P output from the digital PLL circuit 230 is applied to a terminal 240.
LLCLK comes in and is provided to edge detector (EDG) 242. This clock signal has a frequency of 6.3 kHz at a speed of 1 ×, a frequency of 12.6 kHz at a speed of 2 ×, and a frequency of 25.2 kHz at a speed of 4 ×. Edge detector 24
2 generates a pulse which detects the rising edge of the clock signal.

The counter 244, when supplied with this edge detection pulse, loads the value supplied from the adder 246 and thereafter counts up the system clock CLK supplied from the terminal 248. This adder 246
The output value of is normally the reference value -371. The system clock CLK has an operating speed of 1 × and a frequency of 8.64 MHz,
The frequency is 17.29 MHz at 2x speed and 34.57 MHz at 4x speed. Therefore, the counter 44 normally has a speed error of zero when the clock signal PLLCLK has no speed error at the time when the edge detection pulse arrives, negative when the clock signal PLLCLK is fast, and positive when the clock signal PLLCLK is slow. The corresponding count value is output.

This count value is stored in the register (REG) 25.
It is supplied to 0 and stored when the edge detection pulse comes in. The count value stored in the register 50 is averaged by the averaging circuit 252 with the count value of the preceding predetermined number of times and then supplied to the oversampling circuit (OVS) 254.

The oversampling circuit 254 is supplied with a clock obtained by multiplying the edge detection pulse by 4 in the multiplying circuit 256, and using this clock, the averaging circuit 252.
Output oversampling and averaging circuit 252
The value of about 1/4 of the output is obtained and supplied to the adder 258. The adder 258 adds the offset value 172 to the oversampling output and supplies it to the PWM (pulse width modulation) circuit 260. Note that the offset value 172 is a value corresponding to the 50% duty.

The PWM circuit 260 is reset by the clock output from the multiplier circuit 256 and counts the system clock CLK supplied from the terminal 262, and is at a high level (+) until the count value reaches the output value of the adder 258.
Then, a rectangular wave signal as a low level (0 V) speed error signal is generated and supplied to the adder circuit 264.

On the other hand, the reference value 676 and the output of the register (REG) 272 are supplied to the adder 270, and the added value thereof is supplied to the counter 274. The register 27
2 is initially reset to zero. Counter 274 is 1
It is a 1-bit counter that feeds back the carry output by itself to the load terminal, loads the output value of the adder 270 at the carry output timing, and outputs it to the terminal 276.
Of the system clock CLK supplied from the CPU. That is, normally, after loading 676, a carry is output every time the system clock CLK comes in for 1371 pulses to run by itself. This carry has a frequency of 6.3 kHz at the 1 × speed and is supplied to the edge detector 278 and the multiplication circuit 280 as the reference signal Tref.

The edge detector 278 detects the rising edge of the reference signal Tref and detects the rising edge of the counter 286 and the register 29.
Feed to 2. Further, the clock signal PL is applied to the terminal 281.
LCLK comes in and is provided to edge detector 282. The edge detector 282 detects the rising edge of the clock signal PLLCLK and supplies it to the counter 288 and the register 290. The counter 286 is reset at the rising edge of the reference signal Tref, counts the system clock CLK from the terminal 284 and supplies it to the register 290, and the register 290 stores the count value at the rising edge of the clock signal PLLCLK. The counter 288 is a clock signal PLL
After being reset at the rising edge of CLK, the system clock CLK from the terminal 284 is counted to register 292.
The register 292 stores the count value at the rising edge of the reference signal Tref. Therefore, FIG. 7 (A), (B)
With respect to the reference signal Tref and the clock signal PLLCLK shown in, the system clock count value of the period A is stored in the register 290, and the system clock count value of the period B is stored in the register 292.

The subtractor 296 subtracts the output value of the register 292 from the output value of the register 290 to obtain the phase error amount AB and supplies it to the averaging circuit 296. The averaging circuit 296 averages this phase error amount AB with the preceding phase error amount of a predetermined number of times, and the absolute value of the average value is calculated by the PWM circuit 298.
And the sign of the average value is supplied to the tristate buffer 30.
Supply to 0 input terminal.

The PWM circuit 298 is reset by the clock obtained by multiplying the reference signal Tref by 4 in the multiplication circuit 280 and counts the system clock CLK supplied from the terminal 302, and the count value changes from zero to the output value of the averaging circuit 296. A rectangular wave having a high level up to and then a low level is generated and supplied to the control terminal of the tri-state buffer 300.

The tri-state buffer 300 is in an output state when the rectangular wave output from the PWM circuit 298 supplied to the control terminal is in a high level, and is +5 V when the sign supplied from the averaging circuit 296 is positive, and 0 V when the sign is negative. Signal is output, and when the rectangular wave is at a low level, it is in a high impedance state. That is, the PWM circuit 298 and the tri-state buffer 300 have high impedance when the period A and the period B are the same, and 5 V when the period A is larger than B.
Then, when the period B is longer than A, a phase error signal which becomes 0 V is generated and supplied to the adder circuit 264.

The adder circuit 264 has a built-in low-pass filter,
Adds analog voltage. The 0V and 5V speed error signals supplied from the PWM circuit 260 are integrated by a low pass filter to obtain a DC component, and the 0V and 5V phase error signals supplied from the tri-state buffer 300 are high impedance in the low pass filter. The state is 2.
A DC component is obtained by being integrated as 5 V, and an addition signal of the DC components of each of the speed error signal and the phase error signal is supplied to the spindle motor 22 from the terminal 304 as a servo signal.

The above description is based on the clock signal PLL extracted from the BIDATA signal reproduced from the optical disk 20.
CLK is a servo that operates so that the frequency (speed) and the phase match the reference signal Tref generated from the system clock CLK. Next, a synchronizing signal (ATIP _syc ) with a frequency of about 75 Hz reproduced from the optical disk 20.
Will be described with reference to a circuit for phase matching with a synchronizing signal (subcode sync) having a frequency of 75 Hz included in the recording data.

A synchronizing signal SB for recording data is applied to the terminal 310.
SY comes in and the edge detector 312 detects the rising edge and supplies it to the phase difference detector 314. The terminal 316 also has a sync signal ATIP reproduced from the optical disc.
_syc comes in, and the edge detector 318 detects its rising edge and supplies it to the phase difference detector 314, the register 320, and the delay circuit 322. Further, the system clock CLK input from the terminal 324 is frequency-divided by the frequency divider 326 to be supplied to the phase difference detector 314 and the register 320.

The phase difference detector 314 detects the sync signal SBSY.
(Or ATIP _syc ) is loaded with zero at the rising _edge , and then the synchronization signal ATIP _syc or SBSY counts the phase difference until the rising edge with the 1/4 frequency dividing system clock,
The count value is supplied to the register 320. This count value is positive when ATIP _syc is slow, and negative when SBSY is slow. The register 320 is a synchronization signal ATIP.
The count value of the phase difference supplied at the rising _edge of _syc is stored and supplied to the comparator 328 and the register 272.

The comparator 328 has a clock signal PL.
A value ± 343 corresponding to one cycle of LCLK is supplied, and when the count value is less than -343 or exceeds +343 and the phase difference is larger than one cycle of PLLCLK, a trigger signal is supplied to the data generator 130. . On the other hand, when the count value is from -343 to less than +343, the phase difference is P
When it is within one cycle of LLCLK, the trigger signal is supplied to the register 272 together with the sign of the phase difference count value.

The register 272 is supplied with the count value of the output of the register 320 and the signal obtained by delaying the output of the edge detector 318 by the delay circuit 322.
An enable signal EN is supplied to the terminal 332 from a microprocessor (not shown) that controls the entire device. The register 272 outputs zero when the trigger signal is supplied when the enable signal EN is not supplied, and stores and outputs the output of the register 320 by the trigger signal of the comparator 328 when the enable signal EN is supplied.

That is, when the phase difference is within one cycle of PLLCLK, the count value of the phase difference counted by the phase difference detector 314 is supplied to the adder 270 and added to the reference value, whereby the reference signal Tref The generation timing is varied and servo is applied so that the synchronization signal ATIP _{sy c} is synchronized with the synchronization signal SBSY.

By the way, the data generator 330 has a terminal 3
An enable signal EN is supplied from 34. The data generator 330 generates zero when the trigger signal is supplied from the comparator 328 when the enable signal EN is not supplied, and when the enable signal EN is supplied, a predetermined value ± N from the trigger signal and the sign from the comparator 328. Is generated and supplied to the adder 246. The sign of this predetermined value ± N is the sign supplied from the comparator 328, and N
Is a value previously written from the microprocessor, for example, N = 2, 3, or 4.

That is, when the phase difference exceeds one cycle of PLLCLK, the data generator 330 generates a predetermined value ± N and the adder 246 adds it to the reference value -1371 to load it on the counter 244. The value is changed, and servo is applied so that the synchronization signal ATIP _syc is synchronized with the synchronization signal SBSY.

Since the adder circuit 264 is an analog circuit, it is an external circuit of the semiconductor chip 36.
By the way, the above-mentioned microprocessor causes the switch 32 to select the WBL signal at the time of starting the apparatus, and when the rotation of the optical disk 20 becomes stable, the clock signal P is sent to the switch 32.
Select LLCLK. At this point, terminals 332, 3
In the recording mode, the clock signal PLLCLK is not supplied with the enable signal to the reference signal Tre.
After synchronizing with f etc., an enable signal is supplied to the terminals 332 and 334 to change the sync signal ATIP _syc to the sync signal SBSY.
Sync to.

In this way, the phase of the reference clock signal for detecting the phase error of the clock signal is varied based on the phase error of the synchronization signal reproduced from the recording medium, so that the servo loop of the phase system is apparently used. There is only one, and the servo signal is generated in a form in which the phase error of the clock signal and the phase error of the synchronization signal are superposed, and the phase errors of the above two systems can be corrected at the same time.

Further, by varying the frequency of the reference clock signal based on the phase error of the sync signal, the time required to correct the phase error of the sync signal can be shortened and the stable clock signal and sync signal can be reproduced at an early stage. Is possible. As described above, since the digital FSK demodulation circuit 26, the digital PLL circuit 30, and the digital spindle servo circuit 34 are all digital circuits, there is no need for external circuits, semiconductor integration is simple, and the operating speed is 1
When the master clock frequency is changed to double speed, double speed, or double speed, the frequency of the master clock is set to 1, 2, or 4 times, and it is possible to easily cope with the change without changing circuit characteristics.

[0057]

As described above, the invention according to claim 1 is
A digital demodulation circuit for performing digital demodulation by supplying a reproduced and binarized signal from an optical disc on which a digital modulation signal is recorded in advance, and a clock signal phase-synchronized with the demodulation signal output from the digital demodulation circuit are generated. It has a digital phase locked loop circuit and a digital servo circuit for controlling the rotation of the optical disk so as to correct the frequency shift and the phase shift between the clock signal and the reference clock signal.

As described above, the demodulation circuit, the PLL circuit, and the servo circuit are all digital circuits, which simplifies the semiconductor integration of each circuit. According to a second aspect of the present invention, in the optical disk device according to the first aspect, the digital demodulation circuit and the digital servo circuit are integrated on a single semiconductor chip.

By thus integrating all the circuits on the semiconductor chip, the device can be downsized. According to a third aspect of the present invention, in the optical disc device according to the first or second aspect, the digital demodulation circuit uses a master clock having a frequency corresponding to an operation speed as an edge interval of the supplied binarized signal. And outputs a demodulated signal of a level based on the measured value.

As described above, since the edge interval of the binarized signal is measured by using the master clock, the frequency of the master clock can be changed according to the operating speed to easily deal with the change in the operating speed. it can.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a signal waveform diagram for explaining the present invention.

FIG. 3 is a block diagram of a digital FSK demodulation circuit.

FIG. 4 is a block diagram of a digital PLL circuit.

FIG. 5 is a signal waveform diagram for explaining the present invention.

FIG. 6 is a block diagram of a digital spindle servo circuit.

FIG. 7 is a signal waveform diagram for explaining the present invention.

FIG. 8 is a block diagram of a conventional FSK demodulation circuit.

[Explanation of symbols]

20 optical disk 22 spindle motor 24 optical pickup 26 FSK demodulation circuit 30 digital PLL circuit 32 switch 34 digital spindle servo circuit 42, 182, 242, 278, 312, 318 edge detector 50, 52 timing generator 46, 242, 274, 286 , 288 counters 48, 58, 62, 66, 250, 270, 290, 2
92,320 register 54 comparator 56,60,80 multiplexer 64 decoder 68,154 digital low-pass filter 70 threshold value generating circuit 72,328 comparator 74,148,156,160,170,246,25
8,270 Adder 76 Hysteresis generator 142 Edge counter 146 1T generation circuit 150,74 Multiplier 152,58 Constant generator 162 NCO 168 Latch circuit 172 Integrator 252,296 Averaging circuit 254 Oversampling circuit 256,280 Multiplier circuit 260, 298 PWM circuit 294 Subtractor 300 Tri-state buffer 314 Phase difference detector 322 Delay circuit 326 Frequency divider 330 Data generator

Claims (3)

[Claims] 1. A digital demodulation circuit for performing digital demodulation by supplying a reproduced and binarized signal from an optical disc on which a digital modulation signal is recorded in advance, and a phase synchronization with a demodulation signal output from the digital demodulation circuit. An optical disc apparatus comprising: a digital phase-locked loop circuit for generating a clock signal; and a digital servo circuit for controlling the rotation of the optical disc so as to correct the frequency shift and the phase shift between the clock signal and the reference clock signal. . 2. The optical disk device according to claim 1, wherein the digital demodulation circuit and the digital servo circuit are integrated on a single semiconductor chip. 3. The optical disc device according to claim 1, wherein the digital demodulation circuit measures an edge interval of the supplied binarized signal using a master clock having a frequency corresponding to an operating speed, and a measured value. An optical disk device, which outputs a demodulated signal of a level based on.