JP2792054B2 - Clock extraction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus for recording / reproducing a digital signal, and more particularly to a clock extracting circuit for a demodulated digital signal.

[Conventional technology]

An example of a conventional clock extraction circuit is shown in FIG.

In the figure, 21 is an input terminal to which a digital signal demodulated by an equalizer (not shown) is input, 22 is an output terminal from which a data output is obtained, and 23 is an output terminal from which a clock output is obtained. 24 and 25 are buffers, 26 is a resonator consisting of a coil and a capacitor (variable capacitance diode), 27 is a comparator that receives the output of this resonator 26 as input, and 28 is a PLL (Phase Lock) that receives the output of this comparator 27 as input. Lo
op) circuit, 29 is a latch circuit, 30 and 31 are buffers.

Next, the operation will be described. A digital signal demodulated by the equalizer is latched through a buffer 24.
The signal is input to the resonator 24 via the buffer 25. Then, the resonance frequency of the resonator 26 is adjusted to the clock, and after extracting and amplifying the clock component from the digital signal, this is used as the reference input of the PLL circuit 28 to obtain the PLL.
The clock is taken out of the circuit 28 via the buffer 31.

[Problems to be solved by the invention]

In the conventional clock extracting circuit described above, since the resonator is used for extracting the clock component, there is a problem that the resonance frequency of the resonator must be adjusted every time the clock frequency changes. Another problem is that the constant of the resonance circuit fluctuates with temperature, thereby changing the clock phase and the latch timing.

[Means for solving the problem]

A clock extraction circuit according to the present invention includes a gate for receiving a digital signal at the time of reproduction, a resonator including a coil for receiving the output of the gate and a variable capacitance diode, a comparator for receiving the output of the resonator, and an output of the comparator. A PLL circuit as a reference, a latch circuit that uses a digital signal at the time of reproduction as input data and a clock at the output of the PLL circuit, a first edge detection circuit that detects a rise of the digital signal at the time of reproduction, and the latch circuit. A second edge detection circuit for detecting the fall of the output of
And an edge trigger phase detector that receives each output of the second edge detection circuit as an input, a low-pass filter that receives the output of the edge trigger phase detector, and an input that receives the output of the low-pass filter as an input and outputs the control voltage to the resonator. It consists of a supply amplifier.

[Action]

In the present invention, the phase difference between the demodulated signal and the signal latched by the clock is compared.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock extraction circuit according to the present invention.

In the figure, reference numeral 1 denotes an input terminal to which a digital signal (data input) demodulated by an equalizer (not shown) is input during reproduction, 2 denotes an output terminal from which a data output is obtained, and 3 denotes an output terminal from which a clock output is obtained.

4 is a buffer gate for receiving a digital signal during reproduction,
Reference numeral 5 denotes a resonator comprising a coil receiving the output of the buffer gate 4 and a variable capacitance diode; 6, a comparator receiving the output of the resonator 5; 7, a PLL circuit using the output of the comparator 6 as a reference; A latch circuit for receiving a digital signal as input data and clocking the output of a PLL circuit 7, a rising edge detecting circuit 9 for detecting a rising edge of the digital signal during reproduction, and a latch circuit 8 for latching.
Falling edge detection circuit that detects the falling of the output of
Reference numeral 11 denotes an edge trigger phase detector by an RS flip-flop which receives each output of the rising and falling edge detection circuits 9 and 10, 12 denotes a low-pass filter receiving the output of the edge trigger phase detector 11, and 13 denotes a low-pass filter.
An amplifier which receives the output of 12 as an input and supplies the output as a control voltage to the resonator 5, and an inverter 14 inverts the output of the PLL circuit 7.

2A and 2B are time charts for explaining the operation of FIG. 1, wherein FIG. 2A shows an input digital signal, that is, data input, FIG. 2B shows an output of the comparator 6, and FIG. Clock output, (d) data output,
(E) shows the output of the rising edge detection circuit 9, (f) shows the output of the falling edge detection circuit 10, and (g) shows the output of the edge trigger phase detector 11.

FIG. 3 is an explanatory diagram showing characteristics of the edge trigger phase detector 11 in FIG.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.
This will be described with reference to the drawings.

First, a digital signal demodulated by an equalizer (not shown) during reproduction (see data input in FIG. 2A)
Is entered. The demodulated digital signal (data input) is applied to a resonator 5 via a buffer gate 4. In the resonator 5, a clock component is extracted from the digital signal, a waveform is shaped by a comparator 6, and a PLL circuit 7 is formed. Is the reference input.

Here, a variable capacitance diode is used as a capacitor of the resonator 5, and the output of the amplifier 13 changes the phase of the output of the resonator 5. When the clock frequency and the resonance frequency match, the output phase of the resonator 5 becomes the same phase as the input, and when the clock frequency decreases, the output phase delays, and when the clock frequency increases, the output phase advances.

Next, the demodulated digital signal and the output of the PLL circuit 7 whose phase is inverted by the inverter 14 are input to the latch circuit 8, and data is output from the latch circuit 8 (see FIG. 2 (d)). Then, the rising edge detection circuit 9 detects the rising of the demodulated digital signal. Further, the falling edge of the output of the latch circuit 8 is detected by the falling edge detecting circuit 10. Each output of the rising and falling edge detection circuits 9 and 10 is input to an edge trigger phase detector 11 based on RS flip-flop,
An error signal corresponding to the phase difference between the two input signals is output. The output of the edge trigger phase detector 11 is smoothed by a low-pass filter 12 and then amplified by an amplifier 13 to become a control voltage for the resonator 5.

Then, as shown in FIG. 3, the output of the edge trigger phase detector 11 becomes V / 2 when the phase difference of the input signal becomes 180 °.

At this time, by adjusting the clock frequency and the resonance frequency so that they match, the phase difference between the input data of the latch circuit 8 (see FIG. 2A) and the clock is 90 ° as shown in FIG. Become. Where the edge trigger phase detector
The output of 11 averages V / 2 over a long period of time, maintaining the resonance frequency. When the clock frequency decreases, the output phase of the resonator 5 delays, and the output of the edge trigger phase detector 11 drops below V / 2, so that the resonance frequency of the resonator 5 works so as to match the clock frequency.

Thus, even if the clock frequency of the input varies, the phase difference between the input of the latch circuit 8 and the clock is always 90 °.

〔The invention's effect〕

As described above, the present invention has the effect of always obtaining optimum clock and data phases by comparing the phase difference between the demodulated signal and the signal latched by the clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a clock extraction circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 shows the characteristics of an edge trigger phase detector in FIG. FIG. 4 is a block diagram showing an example of a conventional clock extraction circuit. 4 ... buffer gate (gate), 5 ... resonator, 6 ...
... Comparator, 7 ... PLL circuit, 8 ... Latch circuit,
9 rising edge detection circuit, 10 falling edge detection circuit, 11 edge trigger phase detector, 12 low-pass filter, 13 amplifier.

Claims (1)

(57) [Claims] A gate for receiving a digital signal during reproduction;
A resonator including a coil receiving the output of the gate and a variable capacitance diode, a comparator receiving the output of the resonator, and the output of the comparator as reference
A PLL circuit, a latch circuit that uses the digital signal at the time of reproduction as input data and a clock of the output of the PLL circuit, a first edge detection circuit that detects a rise of the digital signal at the time of reproduction, and an output of the latch circuit. A second edge detection circuit for detecting a falling edge, an edge trigger phase detector receiving the outputs of the first and second edge detection circuits as inputs, a low-pass filter receiving the output of the edge trigger phase detector; A clock extraction circuit comprising an amplifier that receives an output of a low-pass filter and supplies the output as a control voltage to the resonator.