JPS61294667A - Synchronous field detecting circuit - Google Patents

Abstract

PURPOSE:To eliminate the influence of temperature, power source, etc., and to detect synchronous fields having no error without any adjustment by counting a write clock signal and deciding the period of each pulse of an MFM modulated signal, and detecting the shortest period and detecting the synchronous fields. CONSTITUTION:The MFM modulated signal 2 is inputted to a rise generating circuit 21, which outputs a leading edge signal 41 to an FF 27 as an input clock; and a delay circuit 22 generates a delay signal 42. A counting circuit 23 is reset with every signal 42 to count the write clock signal 19. Its counted value 43 is sent to decision circuits 24-26 and the circuits 24-26 output signals 44-46 of H while the counted value 43 is 1, 2, or 3. The decision signal 44 is supplied to an FF 30 through an OR gate 29 and when a next delay signal 24 is also supplied, the FF 30 outputs a synchronous field detection signal 16 of H. Then, a detection signal 16 is obtained with the signals 45 and 46.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a circuit for demodulating an MFM modulated signal read from a magnetic disk device, etc., and particularly relates to a circuit for demodulating an MFM modulated signal read from a magnetic disk device, etc. This invention relates to a synchronous field detection circuit used for synchronization.

[Background of the invention]

Conventionally, in magnetic disk drives, MFM modulation (Modified
Frequency modulation) method is used. According to this method, a clock is extracted from the reproduced MF'M modulated signal, and the M FM modulated signal can be demodulated using this clock. A circuit for generating such a clock and demodulating the MFM modulation signal will be explained with reference to FIG.

In the figure, a reproduced signal from a magnetic head 1 is amplified and waveform-shaped by a readout circuit 2, and becomes an MFM modulated signal 3. This MFM modulation signal 3 is demodulated into an NRZ signal 18 by an MFM demodulation circuit 17 using a CO clock 9 synchronized with this MFM modulation signal 3. vCO clock 9 M
In order to synchronize with the FM modulation signal 6, a P L consisting of a switching circuit 5, a phase comparison circuit, a filter 7 and VCOs is used.
L (Phase Locked Loop) and
A synchronous 7+- field detection circuit 10 is provided.

On the other hand, in magnetic recording on magnetic disks and the like, normally, as shown in FIG. 5, a recording signal is composed of a synchronization field/ID field, a synchronization field, and a DATA field as one unit, which are repeated. During the synchronous field period, the VCO 8, the phase comparator circuit 6.
A PLL consisting of a filter 7 is forcibly synchronized to an MFM modulation signal 5. In this case, the gain of the PLL is generally high during the synchronization field.

Incidentally, even in a state where the MFM modulation signal 3 is not normally reproduced, such as when the head 1 is moving in the radial direction of the magnetic disk, v008 continues to oscillate. Signal 511CPLL
It is inappropriate to synchronize tL. Therefore, during this period, the clock source 4 for magnetic recording writing is used as another oscillation source.
In many cases, the clock signal 19 from the PLL is provided to the PLL. A switching circuit 5 switches the clock signal 19 and the MFM modulated signal 3 to the phase comparison circuit 6, and the switching command signal for the switching circuit 5 is the output of the synchronous field detection circuit 10. A synchronous field detection signal 16 is used. That is, the synchronization field detection circuit 10 detects that the MFM modulation signal 3 is in the synchronization field period, and thereafter synchronizes the PLL with the MFM modulation signal 3, and uses the CO clock signal 9 obtained thereby to perform the MPM.
The modulated signal 3 is demodulated into an N-2 signal 18.

The synchronization field of the MFM modulation signal 3 consists of pulse repetitions of the shortest synchronization in the MFM modulation signal 3. now,
Assuming that the write clock signal 190 period is 1, there are six types of ratios of the period of the pulse constituting the MFMyR1l signal to this, 2, 5, and 4. Therefore, the period of the pulse of the period field is 2, which is the shortest.

A synchronous field detection circuit 10 for detecting a synchronous field from an MFM modulated signal 6 is composed of a monostable oscillator 11 and a 7-lip 70-tube 14.

The monostable oscillator 11 is retriggerable and its oscillation period is set equal to 2.5 pulse periods of the MFM modulation signal 5. The clip 70 tube 14 receives the output 15 of the monostable oscillator 11 as a D input, uses each pulse of the MFM modulation signal 5 as a clock input, and its Q output becomes the synchronous field detection signal 16.

Next, using FIG. 6, this synchronous field detection circuit 10
The period other than the 30-cycle field of the OMFM modulation signal, which explains the synchronization field detection operation of Triggered by the rising edge of each pulse, its output 15 goes H' (high level), but goes back to L' (low level) before receiving the next pulse.
becomes. At this time, the rising edge of the output 15 is slightly delayed from the rising edge of the pulse of the MFM modulation signal 3. Therefore, in the clip block 14, the 'L' part of the output 15 of the monostable oscillator 11, which is the D input, is sampled at the rising edge of the pulse of the MFM modulation signal 3, which is the input clock, so that the output of the flip-flop 14! '!
, 'L'.

On the other hand, in the synchronous field period of the MFM modulation signal 3, the pulse period is 2, so when the monostable oscillator 11 is triggered by the first pulse of this period, the output 15 changes from H' to L'. The pulses are applied sequentially before inverting to , so that the output 15 is held at H'. Therefore, in the 7 lip-flop 14, 2 of the synchronous field period is
The H' output 15 of the monostable oscillator 11 is sampled from the th pulse, and the output of the flip-flop 14 is held at H'. In this way, the synchronous field detection circuit 10 detects the synchronous field of the MFM modulated signal 5 and
' synchronization 7 (- field detection signal 16 is obtained.

In this way, the conventional synchronous field detection circuit 10 was constructed using the monostable oscillator 11, but the monostable oscillator 1
1 requires a resistor 12 and a capacitor 13, and since it is an analog circuit element, it is easily affected by temperature and power supply, and requires adjustment to set the cycle accurately. There was a problem.

[Purpose of the invention]

An object of the present invention is to provide a synchronous field detection circuit that eliminates the problems of the prior art described above, prevents the effects of temperature, power supply, etc., and enables error-free detection of synchronous fields without the need for adjustment. be.

[Summary of the Invention] To achieve this object, the present invention determines the period of each pulse of the MFM modulation signal by counting the write clock signal, detects the shortest period, and detects the synchronization field. The feature is that the synchronous field is detected by digital processing.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the synchronous field detection circuit according to the present invention, in which 21 is a rising edge generation circuit, 22 is a delay circuit, 23 is a counter, 24, 25,
26 is a determination circuit, 27 is a clip flop, 28 is an AND gate, 29 is an OR gate, and 30 is a flip 70 block.

In the figure, the MFM modulation signal 3 is supplied to a rising edge generation circuit 21, and the write clock signal 19 from a clock source 4 (FIG. 4) is supplied to a counter 26, respectively. counter 2
5 repeats the write clock signal 190 counts between every pulse of the MFM modulation signal 3. When the count value 43 of the counter 25 is 1, the determination circuit 24 outputs a determination signal 4 that becomes 'H'.
The judgment circuit 25 outputs a judgment signal 45 which becomes H' when the count value 45 is 2, and the judgment circuit 26 outputs a judgment signal 46 which becomes H' when the count value 43 is 3 or more.
Output.

Next, the operation of this embodiment will be explained using FIG. 2 and FIG. will be explained using FIG.

The MFM modulation signal 3 is supplied to a rising edge generation circuit 21, and a rising edge signal 41 representing the rising edge is generated. This rising edge signal 41 is used as an input clock to a flip-flop 270 and is delayed by a delay circuit 22 to generate a delayed signal 42.

The counter circuit 25 is reset every delay signal 42 and counts the write clock signal 19. For this reason, the count value 43 of the counter 23 starts counting from 0 every time it is reset by the delay signal 42, and the count value 43 changes from 0. This count value 43 is supplied to the determination circuits 24, 25, and 26, but during the period when this count value 43 is 1, the determination circuit 2
4 outputs the H' judgment signal 44, and during the period when the count value 43 is 2, the judgment circuit 25 outputs the H' judgment signal 45, and during the period when the count value 43 is 3 or more, the judgment circuit 26 outputs the H' judgment signal A determination signal 46 is output.

Here, assuming that the write clock signal 190 period is 1, the pulse period in the synchronous field period is as follows:
2, therefore, when the count value 43 of the counter 23 is 5 or more, the MFM modulated signal 3 is not in the synchronous field period. Therefore, the determination circuit 26 outputs the determination signal 4 of H'.
6, this resets the 7 lip-flop 30 and the synchronous field detection signal 16 is not obtained. Determination signal 44 in which the count value 43 is 1 during period 11H1
is supplied to the clip 70 tube 50 via the OR gate 29, and at this time, when the next delayed signal 42 is also supplied, the flip-flop 30 outputs the 1H' synchronous field detection signal 16. This means that when the next delayed signal 42 is generated, the count value 43 of the counter 25 is 1 and M
represents that the pulse period of the FM modulation signal 6 is 2,
Since it is the synchronous field that has this pulse period, the 1H' synchronous field detection signal 16 is obtained from the 7 lip-flop 30. On the other hand, the count value 43 of the counter 23 is 2. Usually, the pulse period of the MFM modulated signal 3 is 3 or more, and therefore the synchronous field detection signal 16 of H' should not be obtained.

However, the phase relationship between the MFM modulation signal 5 and the write clock signal 19 is not limited to the relationship shown in FIG. 2, but may also be the phase relationship shown in FIG. 6. In such a case, the synchronization field The counter 23 counts up to 2 even though the period is 2 and the pulse period is 2.

Therefore, if the 1H' synchronous field detection signal 16 is not always generated when the count value 43 of the counter 25 becomes 2, the synchronous field will not be detected erroneously.

By the way, once the phase relationship between the MFM modulation signal 3 and the write clock signal is set, it does not change during operation, and unlike other periods, the pulse period is constant during the synchronization field period, so the MFM modulation signal 6 Assuming that the count value 45 of the counter 23 immediately before resetting in a series of pulse periods is always 2, the period of these pulse periods is a synchronization field period. Based on this point, flip 7
The 0 knob 27 and the AND gate 28, together with the flip 70 knob 30, prevent the synchronous field from being missed.

That is, when the judgment signal 45 of the judgment circuit 25 becomes H', the rising edge generating circuit 21 outputs the rising edge signal 41, and the 7-rib flop 27 outputs the rising edge signal 41 as a clock. The judgment signal 45 of
The count value 45 changes sequentially from 0, but when the count value 45 reaches 2, the determination signal 45 of the determination circuit 25 becomes H', and the output 48 of the AND gate 28 becomes H'.

This H' output 48 passes through the AND gate 29 and becomes the D input of the 7-lip 70-tube 60. During the period when this D input is H', the delay signal 42 of the delay circuit 22 is used as a clock input to provide the 7-lip 70-tube 60 input. When supplied to flip 70
The knob 30 outputs a synchronous field detection signal 16 of H'.

This means that the counter 23 counts up to 2 in a certain pulse period of the MFM modulation signal 5 (this is stored in 7 lip 70 tabs 27), and the counter 23 counts up to 2 in the next pulse period.
has counted up to 2 (this is determined by the flip 70 block 30), the flip 70 block 50 has determined that the MFM modulated signal 5 is in the synchronous field period.

If at least one of the count values of the counter 23 in these two pulse periods is 1 or 3 or more, 7
Lip 70 tube 30 does not sample H input data.

As described above, no matter what the phase relationship between the MFM modulation signal 6 and the write signal 19 is, the period in which the counter 25 counts up to 1 in the pulse period of the MFM modulation signal 6, and the period in which the counter 23 counts up to 1 in the pulse period of the MFM modulation signal 5, 7 lip-flops 6 o
The output becomes -H', and when the counter 25 counts 5 or more in the pulse period of the MP'M modulation signal 5, the output of the 7-rip 70-tube 30 becomes L'. In this way, at 17,
The synchronization field of the MFM modulated signal 5 can be detected accurately.

According to this embodiment, no circuits that are affected by temperature or power supply are used, and no circuits that require adjustment are used. Therefore, the synchronization field will be detected accurately without any adjustment.

〔Effect of the invention〕

As explained above, according to the present invention, a synchronous field can be detected using a completely digital circuit, so components that are affected by temperature, such as resistors and capacitors, are not required, and there is no need for components that are affected by temperature or power supply. It is possible to perform stable operation, which is difficult to achieve.
In addition, it is possible to achieve small size and low cost through integration, and
No adjustment is required, and it is possible to provide a synchronous field detection circuit with superior functionality not found in the prior art.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the synchronous field detection circuit according to the present invention, FIGS. 2 and 6 are timing charts for explaining its operation, and FIG. 4 is a MF
M weird! ! 14 (A block diagram showing an example of a clock generation means for No. 1 demodulation, FIG. 5 is a schematic diagram showing the configuration of an MFM modulation signal, and FIG. 6 is a timing chart for explaining the operation of a conventional synchronous field detection circuit. Chart 0 21... Rising edge generation circuit, 22... Delay circuit, 23... Counter, 24, 25, 26... Judgment circuit, 27... 7 Rig 7a Tub, 28... And gate, 29...or gate, 30...flip flop.

Claims (1)

[Claims] a counting means for counting a clock signal of a constant period for each pulse period of an MFM modulated signal reproduced from a magnetic medium; A synchronous field detection signal is generated when the count values in two consecutive pulse periods are both equal to a second value larger than the first value, and the count value of the counting means in the pulse period is equal to the second value. synchronous field detection signal generation means for stopping generation of the synchronous field detection signal when the synchronous field detection signal is equal to or greater than a third value, detects the synchronous field of the MFM modulated signal and outputs the synchronous field detection signal. A synchronous field detection circuit characterized in that it is configured to enable.