JPH0526273B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock demodulation circuit for demodulating a clock synchronized with an intermittent clock in high-density modulated data.

Recently, as a modulation method for high-density digital recording,
Those that have self-clock information in their data, such as MFM, M ² FM, MNRZI, 3PM, and interleaved NRZI, have been put into practical use. The clock for this modulation method is generally not input continuously, but intermittently, but in order to demodulate the modulated data, it is necessary to input this clock from the intermittent clock included in the data. It is necessary to demodulate a continuous clock that is synchronized with the For this reason, conventionally, for example, a phase locked loop circuit (hereinafter referred to as a PLL circuit) that has a phase comparator and a voltage controlled oscillator that is synchronized with the extracted pulse by extracting the state change point of the MFM using a differentiating circuit. The output is gated with intermittent pulses, and the gated pulses are used as the phase comparison input of the PLL circuit to demodulate the continuous clock. However, in this demodulation method, the comparison pulse is gated by an intermittent clock and the phase comparison is performed intermittently, so the MFM signal may be affected by the phase comparison due to scratches on the recording medium or cracks in the waveform due to noise in the transmission system. There is a problem in that this has an adverse effect, resulting in a shift in the reproduced clock frequency.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a clock demodulation circuit suitably configured to stably obtain a continuous clock synchronized with an intermittent clock in data.

The present invention provides a first clock generating means for extracting an intermittent clock from data including the intermittent clock, a second clock generating means for generating a continuous clock synchronized with the intermittent clock, and a time domain for determining the intermittent clock. a first edge determined based on the edge portion of the continuous clock; and a first edge determined based on the edge portion of the intermittent clock when the intermittent clock is detected within the time domain; and a second edge determined based on the edge portion of the continuous clock when the clock is not detected; and a phase comparison means for performing a phase comparison with the continuous clock, and the second clock generation means is controlled based on the comparison output of the phase comparison means to change the oscillation frequency of the continuous clock. .

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an example of a clock demodulation circuit according to the present invention. A modulation signal including an intermittent clock such as an MFM modulation signal is supplied to a differentiating circuit 1, and its differentiated output is supplied to a clock input terminal of a D-type flip-flop (hereinafter abbreviated as D-F/F) 2. The D terminal of D-F/F2 is fixed at L level, and the output is passed through delay circuit 3 to D-
Supplied to the clock input terminal of F/F4. D-
The D terminal of the F/F 4 is fixed at L level, and its Q output is supplied to one input terminal of the phase comparator 6 of the PLL circuit 5. In this example, the PLL circuit 5 includes the phase comparator 6 and a low-pass filter 7 that receives its output.
and a voltage controlled oscillator 8 whose clock oscillation frequency is controlled based on the output of the low-pass filter 7. The output of the voltage controlled oscillator 8 is supplied to the other input terminal of the phase comparator 6, and is also supplied to a differentiating circuit 9 for differentiation, and the differentiated output is applied to the D-F/F.
2 and 4, respectively. Further, the output of the voltage controlled oscillator 8 is supplied to the clear terminal of the DF/F 2 via the delay circuit 10 and also to one input terminal of the OR gate 11. The output of DF/F2 is supplied to the other input terminal of this OR gate 11, and 4 of this OR gate 11 is supplied to the clear terminal of DF/F4.

The operation of the clock demodulation circuit shown in FIG. 1 will be explained below with reference to the signal waveform diagrams shown in FIGS. 2A to 2H. When a signal as shown in FIG. 2B is input to the differentiating circuit 1 as a modulation signal, the differential output is as shown in FIG. 2C. On the other hand, the rising portion of the output of the voltage controlled oscillator 8 shown in FIG. 2A is cut out by the differentiating circuit 9, resulting in a pulse waveform as shown in FIG. Supplied. Therefore, these D-F/Fs 2 and 4 are set in synchronization with the falling of the differential output of the differentiating circuit 9, that is, the rising of the output of the voltage controlled oscillator 8. After D-F/F2 is set by the output of the differentiating circuit 9, it is reset by the rising edge of the output of the differentiating circuit 1 supplied to its clock input terminal, but the clear terminal receives the output of the voltage controlled oscillator 8. is input through the delay circuit 10, so when there is no differentiated output waveform from the differentiating circuit 1, it is reset at the falling edge of the delayed output of the voltage control generator 8. Therefore, the Q output of D-F/F2 has the waveform shown in FIG. 2E, and this signal passes through the delay circuit 3 to match the phase with the output of the voltage controlled oscillator 8, as shown in FIG. 2F. It is delayed and supplied to the clock input terminal of DF/F4,
At the rising edge of the signal, the differential output of the differentiating circuit 9 sets the D-F/F in the same way as D-F/F2.
Reset 4. In addition, the output of the D-F/F2 (Fig. 2 E) and the output of the voltage controlled oscillator 8 (Fig. 2 A) are supplied to the OR gate 11, which synchronizes with the fall of the output of the voltage controlled oscillator 8. A signal as shown in Figure 2G is used as a reset pulse D-
Since it is supplied to the clear terminal of F/F4, when the differential output waveform of differential circuit 1 is not input to D-F/F2, it is reset by this reset pulse. Therefore, the Q output of the D-F/F4 has the waveform shown in FIG. By comparing the phase of
A phase error signal between the intermittent clock shown in FIG. 2C and the output of the voltage controlled oscillator 8 shown in FIG. 2A is obtained. This phase error signal is input to a voltage controlled oscillator 8 via a low pass filter 7, whereby the output of the voltage controlled oscillator 8 is controlled to be synchronized with the intermittent clock.

As is clear from the above, in the past, the output of the voltage controlled oscillator was gated with an intermittent clock to perform phase comparison while maintaining the intermittent waveform, but in this embodiment, on the contrary, the intermittent clock Even when the clock is not input, phase comparison is performed continuously by apparently inputting a clock. That is, DF/F2 generates a gate signal (E in FIG. 2) for detecting an intermittent clock, and DF/F4, which is set by the differential output of differential circuit 9, is delayed by delay circuit 3. D-
It is reset by the output of F/F2, but if the clock information shown in FIG. It is reset by a reset pulse. Therefore, if the intermittent clock information shown in FIG. 2C exists within the gate signal range, this intermittent clock information acts as an input to the phase comparator 6; The output, that is, the output of the voltage controlled oscillator 8 is input to the phase comparator 6.

The present invention enables continuous phase comparison by apparently inserting a clock even when an intermittent clock is not input, and demodulates a stable continuous clock synchronized with the intermittent clock included in the modulation signal. can do.

Note that the present invention is not limited to the above-mentioned example, and can be modified or changed in many ways. For example, in the above example, the storage means is D-
Although F/F is used, it is not necessarily limited to this, and any register may be used as long as it has a storage function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an example of a clock demodulation circuit according to the present invention, and FIGS. 2A to 2H are signal waveform diagrams for explaining the operation thereof. 1, 9... Differential circuit, 2, 4... D type flip-flop (D-F/F), 3, 10... Delay circuit, 5... Phase locked loop (PLL) circuit, 6... ...Phase comparator, 7...Low pass filter, 8...Voltage controlled oscillator, 11...OR gate.

Claims (1)

[Claims] 1. A first clock generation means for extracting an intermittent clock from data including the intermittent clock, a second clock generation means for generating a continuous clock synchronized with the intermittent clock, and a gate generation means for determining the time domain in which the intermittent clock is detected. a first edge determined based on an edge portion of said continuous clock; and a first edge determined based on an edge portion of said intermittent clock if said intermittent clock is detected within said time domain; a third clock generating means for generating a clock consisting of a second edge determined based on the edge portion of the continuous clock when the clock is not detected; A clock demodulation device comprising: phase comparison means for performing a phase comparison; the second clock generation means is controlled based on the comparison output of the phase comparison means, and the oscillation frequency of the continuous clock is changed. circuit.