JPS6195647A - Digital signal reader - Google Patents

Abstract

PURPOSE:To prevent oscillation of a circuit at the absence of a digital signal by detecting the digital signal and applying a clock signal to a circuit discriminating and reading logical '1' or '0' in place of the digital signal when no digital signal exists. CONSTITUTION:An input terminal 1 of the digital signal reader 7 is provided with a detection circuit 40 detecting whether or not the digital signal is inputted with a prescribed state and the output changes over a switch 41. The switch 41 outputs selectively alternatively either a master clock signal fed from an inverse amplifier consisting of an inverter 42, and resistors 43, 44 or a digital signal fed from an inverter 10. A resistor 45 and a capacitor 46 constitute a low-pass filter. When the switch 41 is thrown to the position of the inverter 42, a master clock outputted, it is compared with a reference value by an inverter 13 to lock a PLL circuit 6 of the post-stage by using the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal reading device for a digital audio disc player or the like.

[Conventional technology]

In digital audio discs and the like, digital signals are FM modulated and recorded.

In this FM modulation method, the level is inverted at both ends of each bit cell of the digital signal that is the modulated signal, and when the bit is in logic LL I I+, the level is inverted at the center of the bit cell, and the bit is When the logic is II OI+, modulation is performed based on the conversion rule that the level is not inverted in that bit cell. As a result, the modulated signal according to this modulation method has the characteristic that the high level and low level periods are equal, and therefore does not contain a DC component, and can be demodulated by a self-clock.

FIG. 5 shows a block diagram of a conventional digital signal reading device for reading digital signals recorded or transmitted after being modulated by such a modulation method. A digital signal input from an input terminal is input to a comparator 2 via a coupling capacitor 1. The output of the comparator 2 is supplied to a data terminal of a delayed flip-flop 3 and also to a time rate detection circuit 4. The time rate detection circuit 4 detects the average time rate of the high level and low level of the output of the comparator 2, and relatively controls the comparison level of the comparator 2 in accordance with the time rate. . Reference numeral 5 denotes an edge detection circuit that detects rising and falling edges of the output of the comparator 2 and supplies the edge information to the PLL circuit 6. The output of the PLL circuit 6 is output as a clock signal to various circuits and means (not shown), and is also supplied to the delayed flip-flop 3.

The operation will be explained with reference to FIG.

The input digital signal is distorted compared to the original modulated signal (a) and has a waveform close to a sine wave (b) because the transmission system and recording/reproducing system have finite frequency characteristics. The input signal is compared with a predetermined comparison level by the comparator 2, and its output becomes a rectangular wave signal (c). Ideally, this signal (c) is in phase with the original signal (a), but
In reality, the signal differs slightly from the original signal (a) due to jitter, noise, etc. The rising and falling edges of the signal (c) are detected by the edge detection circuit 5, and a pulse signal (d) synchronized with the timing of the edges is applied to the PLL circuit 6. Since this pulse signal (d) includes a clock component, the PLL circuit 6 oscillates in synchronization with the clock and outputs a clock signal (e). The delayed flip-flop 3 to which this clock signal (S) is applied to its clock terminal outputs a signal (f) at a level corresponding to the level of the signal (c) supplied to its data terminal at the timing of the falling edge. do.

Incidentally, as the signal (b) passes through various routes, a drift occurs in the signal (b), and its upper and lower peaks are not symmetrical. Therefore, if the comparison level of the comparator 2 is set to a predetermined fixed level, the timing of the edge detected by the edge detection circuit 5 does not necessarily exactly match the timing of the original signal (a).

The PLL circuit 6 will no longer be able to accurately extract the clock signal. Therefore, the time rate detection circuit 4 detects the high level time and low level time of the output of the comparator 2, and relatively controls the comparison level according to the difference between the two (by giving an offset to the input signal). ). As mentioned above, the signal (c) is originally modulated so that its high level and low level times are equal, so if we set the level at which the time rates of both levels are equal as the reference threshold, we can determine the correct timing. You can extract the clock with . The details are in the patent application filed by the applicant in 1982-21.
It is disclosed in the specification of No. 5207.

FIG. 7 shows another conventional example of the circuit 7 consisting of the comparator 2 and the time rate detection circuit 4 shown in FIG. In the figure, 1o to 14 are C-MOS inverters, and the first two are used as inverting amplifiers by resistors 15, 16, 17, 18, 19, and 20, respectively. It is used as a comparator with a threshold value of 2.5 V). The resistor 21 and the capacitor 22 and the resistor 23 and the capacitor 24 each constitute a low-pass filter to extract the DC component. The difference between the DC output components of each port-pass filter is determined by the differential amplifier 25, the resistor 26 .
27, and a fully integral differential amplifier circuit consisting of capacitors 28 and 29. 30 is a resistor that adds the output of the differential amplifier 25 to the input of the inverter 10.

Its operation will be explained with reference to FIG. The digital signal (b) input from the input terminal via the capacitor 1 is amplified by an inverting amplifier made up of inverters 1o and 11.12, and compared with a reference potential (2.5V) by a comparator made up of an inverter 13. . As a result, the output becomes a rectangular wave signal as shown in FIG. 8(c). This signal (
c), for example, if the original threshold of the input signal (b) is offset below 2.5V, as shown by the broken line in FIG. ) is shorter than . Therefore, the signal (d) obtained by inverting the signal (c) by the inverter 14 has a low level time when the original signal (a
) will be shorter. Therefore, when the DC components of signals (c) and (d) are obtained by removing high frequencies higher than the slew rate of the differential amplifier 25 using a low-pass filter consisting of a resistor 21 and a capacitor 22, and a resistor 23 and a capacitor 24, the signal ( The DC level of signal (c) is lower than the DC level of signal (d). As a result, the differential amplifier 25 raises its output level since the level of its inverting input becomes lower than the level of its non-inverting input.

This high level signal is transmitted to the inverter 10 via the resistor 3o.
Since the input signal (b) is added to the input of , the input signal (b) is offset upward. Therefore, the servo is adjusted so that the level of the DC component of the input and output of the inverter 140 becomes equal.

[Problem that the invention seeks to solve]

However, in such conventional devices, if a high-speed or high-gain comparator is used to handle high-speed digital data, oscillations may occur due to jumps in input and output when no signal is input, or noise may be compared. There were drawbacks such as creating random data. When such oscillation occurs, the subsequent PLL circuit locks to that oscillation,
Furthermore, since the frequency of such oscillations varies widely, it becomes difficult to take measures against radiation. Furthermore, when random data is created, it becomes a disturbance and causes the voltage controlled oscillator to oscillate at a frequency different from the original free run frequency, causing the PL
This will impede the capture operation of the L circuit.

[Means for solving problems]

FIG. 1 shows a block diagram of a digital signal reading device of the present invention, and parts corresponding to those in FIGS. 5 and 7 are given the same reference numerals, and detailed description thereof will be omitted. In the present invention, a digital signal (RF
A detection circuit 40 is provided to detect whether or not the multiplied signal is input in a predetermined state, and a switch 41 is switched by the output of the detection circuit 40. switch 41
is inverter 42. Either the master clock signal supplied from the inverting amplifier constituted by resistors 43 and 44 or the digital signal supplied from the inverter 10 is selectively output. The resistor 45 and capacitor 46 constitute a low-pass filter, which slightly slopes the rising and falling edges of the input mask clock signal. 47 is an addition resistor that adds the output from the differential amplifier 25 to the input of the inverter 42. The other configurations are the same as in FIG. 7.

[Effect]

The operation will now be explained. The detection circuit 40 detects the presence or absence of an input signal, for example, whether the RF multiplied signal level is higher than a predetermined reference value.If the level is higher than the reference value, it switches the switch 41 to the inverter 10 side; If so, each is switched to the inverter 42 side. When the switch 41 is switched to the inverter 10 side, the operation is similar to that described in FIG. 7.

When the switch 41 is switched to the inverter 42 side, the master clock is applied to the switch 41 via a low-pass filter consisting of a resistor 45 and a capacitor 46, an inverting amplifier consisting of the inverter 42, and resistors 43 and 44.
It is output from This clock signal is compared with a reference value by the inverter 13, but since its rising and falling edges are slightly sloped, the comparison operation is not difficult. Since what is input is a clock signal, what is output is also a clock signal, and the PLL circuit 6 connected at the subsequent stage is also locked to the clock signal.

〔Example〕

FIG. 2 shows an embodiment of the detection circuit 40 in FIG. In the figure, 50 is a capacitor connected in series to the signal line, and 51 and 52 are resistors and diodes connected in parallel to the output side thereof.

53 is a diode arranged in series with the signal line, and 54 and 55 are resistors and capacitors connected in parallel to its output. A comparator 56 compares the input signal with a reference potential divided by resistors 57 and 58. 59 is a resistor connected to the output terminal of the comparator 56.

When the RF multiplied signal input to the input terminal is negative, the diode 52 is turned on, so the signal line is approximately -0,
Clamped to 7V. When the RF multiplied signal is positive, the diode 52 is turned off and the diode 53 is turned on, so that the peak value is held in the capacitor 55. When this value is larger than the reference voltage divided by the resistors 57 and 58, the comparator 56 outputs a high level signal, and when it is smaller, it outputs a low level signal. In other words, this circuit detects the level (envelope) of the RF multiplied signal (digital signal),
When the value is greater than or equal to a predetermined value, the presence of the RF multiplied signal is detected. The capacitor 55 is selected to have a value such that it is not sufficiently charged by spike noise, but is sufficiently charged by the RF multiplied signal, and the resistor 54 is selected so that even if there is an RF multiplied signal dropout, the capacitor is The time constant is chosen such that the charge of 55 is not significantly discharged.

FIG. 3 represents another embodiment of the invention. In FIG. 1, the outputs of the inverter 10 and the inverter 42 are selected by the switch 41, but in this embodiment, a switch 60 is provided at the input stage of the inverter 10 to select the RF multiplied signal and the clock signal. That's what I do. In this case, it is necessary to prevent the clock signal from jumping to the input terminal of the RF signal. Therefore, for example, the fourth
As shown in the figure, another switch 61 is provided on the clock signal supply side, and when the switch 60 is switched to selectively output the clock, the switch 61 is also switched to output the clock signal to the switch 60. When the switch 60 selects the RF multiplied signal, the line may be grounded and the switch 61 may be switched so that the clock signal is not supplied to the switch 60.

Note that since the clock is a binary signal, the switch 61 may be a logic circuit such as an AND gate.

〔effect〕

As described above, in the present invention, the digital signal is detected, and when there is no digital signal, the clock signal is supplied to the circuit that discriminates and reads the logic u I I + or '0'' instead of the digital signal. This not only prevents the circuit from oscillating when no signal is present, making it difficult to take countermeasures against radiation, or causing malfunctions due to noise, but also prevents the circuit from oscillating when no signal is present.
Since the LL circuit is synchronized with the clock, it is equivalent to free-run oscillation, and its capture characteristics are not disturbed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the digital signal reading device of the present invention, FIG. 2 is a circuit diagram of an embodiment of the detection circuit, FIGS. 3 and 4 are circuit diagrams of other embodiments, and FIG. 5 is a conventional circuit diagram. FIG. 6 is a block diagram of the digital signal reading device, FIG. 6 is a waveform diagram thereof, FIG. 7 is a circuit diagram of another conventional embodiment, and FIG. 8 is a waveform diagram thereof. 1.22.24.28.29.46.50.55...
Capacitor 2.56...Comparator 3...Delayed flip-flop 4...Time rate detection circuit 5...Edge detection circuit 6...PLL circuit 10.
11.12.13.42...Inverter 15.16.
17.18.19.20.21.23.26.27.3
0.43, 44.45.47, 51.54.57.58
．． 59...Resistor 25...Differential amplifier 41.6o, 61...Switch or more

Claims (5)

[Claims] (1) A comparator that compares an input digital signal modulated using a method in which the time rate of high level and low level are approximately equal, with a predetermined comparison level, and the high level and low level of the output of the comparator. a time rate detection circuit that detects a time rate of and relatively controls the comparison level in accordance with the time rate;
comprising a detection circuit that detects the input digital signal, and a switch circuit that selectively selects either the digital signal or the clock signal and outputs it to the comparator,
A digital signal reading device characterized in that the switch circuit selectively outputs the digital signal when the detection circuit detects the digital signal, and selectively outputs the clock signal when the detection circuit does not detect the digital signal. (2) The digital signal reading device according to claim 1, wherein the clock signal is input to the comparator after its rising or falling edge is sloped. (3) Another switch circuit is provided on the path for supplying the clock signal to the switch circuit, and when the switch circuit selects the digital signal, the another switch circuit connects the switch circuit to the switch circuit. 3. The digital signal reading device according to claim 1, wherein a path for supplying the clock signal to the digital signal reading device is cut off. (4) The digital signal reading device according to claim 3, wherein the other switch circuit is a logic circuit. (5) The digital signal reading device according to any one of claims 1 to 4, wherein the detection circuit detects the level of the digital signal.