JP2000261316A - Phase synchronous circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably operate a PLL in a non signal mode, also to fast perform lock-in and to prevent the influence of capacitive discharge in a phase synchronous circuit responding to a regenerative digital signal of an optical disk. SOLUTION: In this phase synchronous circuit responding to a regenerative signal of an optical disk, a deciding means 28 generates a gain control signal in accordance with the magnitude of a phase error inputted to a loop filter, and a fast pulling operation and phase tracking whose noise is small are made possible by controlling coefficients (G, C1 and C2) deciding a response characteristic with it. Also, it is possible to suppress phase disturbance due to signal deficiency or the like and to perform phase pulling again satisfactorily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase synchronization circuit of a decoding device used for a reproducing device for reproducing digital data (signal) recorded on an optical disk such as a DVD and a CD.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Hei 8-167845 discloses a method of separating a loop filter in a PLL loop when there is no signal to stabilize the circuit when there is no signal. In this conventional example, the operation of a low-pass filter constituting a loop filter is stopped when there is no signal during data reproduction, the discharge of a capacitor that determines the time constant of the filter is suppressed, and a VCO (voltage controlled oscillator) when there is no signal. In this case, it is intended to prevent the oscillation frequency from being disturbed and to speed up lock-in from the absence of a signal.

[0003]

However, in order to suppress discharge during the period until no signal is detected, it is necessary to lower the gain of the loop filter and the loop gain of the PLL. There is a problem that it takes.

In order to increase the lock-in speed, the gain of the loop filter may be increased. However, a non-signal period is detected and the discharge until the loop is cut cannot be ignored. FIG. 7 is a configuration diagram of a general phase locked loop, and FIG. 8 is a configuration diagram of a general loop filter. The actual configuration includes a frequency loop and the like, but the description is omitted here. In FIG. 7, a phase comparator 50 detects a phase difference between the binarized input data and the bit clock as a phase error, and a signal of this phase error is input to a loop filter 52. The loop filter 52 smoothes the phase error signal and generates a drive voltage for the VCO 54.

[0005] When there is no input of a phase error signal, the loop filter 52 discharges with a time constant of CR2. On the other hand, Japanese Patent Application Laid-Open No. 8-167845 proposes to prevent discharge when there is no signal. However, with the technique proposed in the publication, discharge in an analog circuit cannot be completely suppressed, and the influence of noise when switching from no signal cannot be ignored.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and at the time of normal reproduction, the phase follow-up gain is reduced, and a PLL loop which is not affected by signal noise is formed. Is detected, the phase information is held accurately, and in the case of lock-in after no signal, the phase tracking gain is increased to provide a phase-locked loop capable of high-speed lock-in. , A gain control signal is generated in accordance with the magnitude of the phase error input to the loop filter, and the coefficient for determining the response characteristic is controlled accordingly.

That is, according to the present invention, there is provided a phase synchronization circuit for generating a bit synchronization clock for extracting a reproduction signal from a recording medium in which digital information is stored, comprising a gain control means and a coefficient setting means. A loop filter, and according to an output level of the loop filter,
A voltage-controlled oscillator having a variable oscillation frequency, and a determination unit for determining the magnitude of a phase error of a phase error signal input to the loop filter, and for determining a response characteristic of the phase locked loop circuit, According to the present invention, there is provided a phase locked loop circuit configured to control a gain and a coefficient of the gain control means and the coefficient setting means in the loop filter according to a determination result of the determination means.

Further, in addition to the above configuration, there is provided a no-signal section detecting means for detecting a no-signal section of the phase error signal,
The loop filter, holding means for holding the phase error data by the phase error signal, and the no-signal section detection means, when detecting a no-signal section longer than a predetermined section,
A preferred embodiment of the present invention is a phase synchronization circuit including: a control unit that controls the holding unit to hold the phase error data immediately before the detection of the no-signal section.

According to the present invention, a phase locked loop having excellent noise immunity can be formed without using a complicated circuit or operation, and a phase locked loop having excellent lock-in characteristics from no signal such as a signal dropout. A circuit can be provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a preferred embodiment of the phase locked loop of the present invention. In this embodiment, a phase comparator 30, a determining means 28, a no-signal section detecting means 29, a loop filter 52A, a VCO 54
Having. That is, the output terminal 30a of the phase comparator 30
Is output from the loop filter 52A.
Is supplied to the determination means 28, and the gain control signal generated by the determination means 28 is supplied to the loop filter 52A. The input signal edge (delayed clock) output from the output terminal 30b of the phase comparator 30 is supplied to the loop filter 52A and to the no-signal section detecting means 29, and is generated by the no-signal section detecting means 29. The phase hold signal is supplied to loop filter 52A. The output signal of the loop filter 52A is supplied to the VCO 54, and the output signal, that is, the VCO clock is supplied to the phase comparator 30 and the no-signal section detecting means 29, respectively.

FIG. 2 is a block diagram of a preferred embodiment of the loop filter 52A of the phase locked loop shown in FIG. In order to clarify the correspondence with FIG. 1, the same terminal numbers as those in FIG. 1 are used. When the filter is composed of digital elements and the phase comparison circuit and VCO are composed of analog elements, the A / D converter 10 is provided on the input side and the D / A converter 26 is provided on the output side, but all are digital or all are analog. In the case of using an element, it can be directly connected.

In any case, the delay element 22 can be constituted by a D-type flip-flop. FIG. 3 shows an example of a signal waveform indicating the operation of the phase detection (synchronization) circuit in the case of the analog configuration. An input signal as a reproduction signal from an optical disk or the like is binarized and input to the phase comparator 30, and the VCO
A phase comparison is made with the bit clock (VCO clock) from 54.

In this embodiment, a low level signal is output when the bit clock from the VCO 54 is advanced with respect to the phase of the input signal waveform, and a high level signal is output when the bit clock is delayed with respect to the phase of the input signal waveform. . A broken line in the waveform of the phase error signal is an output that has passed through a smoothing filter in order to convert the pulse width of the phase error signal into an amplitude for A / D conversion. This filter can be constituted by a simple CR filter.

A delay element 22, which is one of the components of the phase-locked filter of FIG. 2, operates using a rising edge and a falling edge of an input signal as clocks. Such an edge signal can be generated by an exclusive OR and a delay element. In FIG. 2, the output of the A / D converter 10 is supplied to a gain control circuit 14 via an on-off type switch 12, and the output signal is supplied to coefficient setting units 16 and 18. The output signal of the coefficient setting unit 16 is added to the output signal of the delay element 22 by the adder 20, and the addition result, that is, the output signal of the adder 20 is input to the delay element 22. The output signal of the coefficient setting unit 18 is supplied to an adder 24 together with the output signal of the delay element 22 and is added to each other. The addition result is supplied to a D / A converter 26. Note that the circuit in FIG. 2 constitutes a so-called PI controller that combines integral control and proportional control in control theory.

FIG. 4 is a block diagram of FIG.
FIG. 4 is a block diagram showing an example of a determination unit and a non-signal section detection unit which are processing circuits responding to an output signal of 0 in relation to a phase comparator and a loop filter;
As shown in FIG. 4, the determination means 28 includes an absolute value circuit 3
2, a smoothing circuit 34, an envelope detection circuit 36, a judgment value generation circuit 38, and a comparison circuit 40. Further, the no-signal detecting unit 29 includes a counter 42, a comparing circuit 44, and a determination value generating circuit 46. 4, the same numbers as the terminal numbers in FIG. 1 are used to clarify the correspondence with FIG.

The phase error signal from the phase comparator 30 is input to an absolute value circuit 32, and the absolute value signal is applied to a smoothing circuit 34. The output of the smoothing circuit 34 is peak-held by an envelope detection circuit 36, and the output signal thereof is compared with a predetermined judgment value from a judgment value generation circuit 38 by a comparison circuit 40. A control signal that lowers the loop gain, that is, a gain control signal, is output by the circuit (1).

Specifically, the gain control signal is
It is used as a signal for selecting one of a plurality of gains in the gain control circuit 14 and selecting one of a plurality of coefficients in the two coefficient setting units 16 and 18. In the embodiment shown in FIG. 2, the gain control signal is supplied to the gain control circuit 14 and the two coefficient setting units 16 and 18 to control all of them, but only the gain control circuit 14 is controlled. Do or 2
Only the two coefficient setting units 16 and 18 may be controlled. That is, the control of the gain control circuit 14 and the control of the two coefficient setting units 16 and 18 bring about the same result,
All of these adjustments are treated as coefficient controls in the present invention because they can be considered equivalent. The control of the gain and the coefficient can be performed in two or more appropriate plural stages.

According to the configuration shown in FIG. 2, since the loop gain is determined by controlling the coefficient, there is no problem caused by the gain switching, which is caused by the discharge of the capacitance which is a problem in the case of an analog filter.

In the block diagram of FIG. 4, a non-signal section detecting means 29 comprising a counter 42, a comparing circuit 44, and a judgment value generating circuit 46 shown below generates the phase hold signal shown in FIGS. This is the circuit part that performs. That is,
The counter 42 performs the counting operation of the VCO clock, and has a configuration in which the count value is cleared at the input signal edge. Since no clear signal is input to the counter 42 when there is no signal, the count value of the counter 42 is incremented. Here, the count value from the counter 42 and the judgment value from the judgment value generation circuit 46 are given to the comparison circuit 44, and when the count value exceeds the judgment value, a phase hold signal is output.

The phase hold signal, as shown in FIG.
This can be realized by controlling the on / off switch 12 on the output end side of the / D converter 10 to cut off the input of the loop filter, and furthermore, since the phase information is held in the delay element 22, it is similar to an analog filter. There is no problem due to the excessive discharge. Further, no switching noise occurs even when the hold state is released.

FIG. 5 shows the waveform of the VCO control signal observed when the loop gain switching circuit according to the present invention is not provided, and FIG. 6 shows the waveform of the VCO control signal when the loop gain switching circuit according to the present invention is provided. FIG. In both figures, the phase is synchronized at about 2.3, but as is clear from the comparison between FIG. 5 and FIG. 6, the case where the loop gain switching signal is applied (FIG. 6) is not applied (FIG. 5). ), The noise of the VCO control signal is greatly suppressed.

[0022]

As described above, according to the present invention, D
In a phase synchronization circuit that responds to a reproduction signal of an optical disk such as a VD or a CD, a coefficient for determining a response characteristic is controlled in accordance with the magnitude of a phase error input to a loop filter. Thus, phase tracking with less noise is possible. Further, according to the present invention, it is possible to suppress phase disorder due to signal loss or the like,
Re-phase pull-in can be performed well. A phase-locked loop having excellent noise-to-noise characteristics can be formed without using a complicated circuit or operation, and a phase-locked loop having excellent lock-in characteristics from no signal such as signal loss can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a preferred embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is a block diagram of an embodiment of a loop filter constituting the phase locked loop circuit of FIG. 1;

FIG. 3 is a signal waveform showing an operation of the phase comparator of the phase locked loop circuit shown in FIG. 1 according to the embodiment;

FIG. 4 is a block diagram of an embodiment including a circuit configuration of a determination unit and a no-signal section detection unit in the phase synchronization circuit of FIG. 1;

FIG. 5 shows V as a comparative example to show the effect of the present invention.
FIG. 4 is a diagram illustrating a time change of a phase error of a CO control signal.

FIG. 6 is a diagram showing a time change of a phase error of a VCO control signal in the embodiment of the present invention in order to show an effect of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional general phase locked loop circuit.

FIG. 8 is a block diagram showing a configuration of a loop filter according to a conventional example.

[Explanation of symbols]

 Reference Signs List 10 A / D converter 12 Switch (control means) 14 Gain control circuit (gain control means) 16, 18 Coefficient setter (coefficient setting means) 20, 24 Adder 22 Delay element (holding means) 26 D / A converter 28 Judgment Means 29 No-signal section detection means 30, 50 Phase comparator 32 Absolute value circuit 34 Smoothing circuit 36 Envelope detection circuit 38, 46 Judgment value generation circuit 40, 44 Comparison circuit 42 Counter 52, 52A Loop filter 54 VCO (voltage) Controlled oscillator)

Claims (2)

[Claims] 1. A phase synchronous circuit for generating a bit synchronous clock for extracting a reproduction signal from a recording medium storing digital information, comprising: a loop filter having gain control means and coefficient setting means; A voltage-controlled oscillator whose transmission frequency is variable according to the output level of the filter; and a determination unit that determines a magnitude of a phase error of a phase error signal input to the loop filter. A phase synchronization circuit configured to control a gain and a coefficient of the gain control means and the coefficient setting means in the loop filter according to a determination result of the determination means to determine a characteristic. 2. The phase-locked loop according to claim 1, further comprising: a no-signal section detecting unit for detecting a no-signal section of the phase error signal, wherein the loop filter includes a phase error data based on the phase error signal. Control means for holding the phase error data immediately before the detection of the no-signal section when the no-signal section detection means detects a no-signal section longer than a predetermined section. And a means.