JPS57147353A - Synchronization system - Google Patents

Abstract

PURPOSE:To eliminate a delay time for synchronization and to improve transmission efficiency by synchronizing surely a PLL synchronizing circuit in a terminal controller while the terminal controller sends polling frames. CONSTITUTION:When a polling instruction is supplied from a processor 14 to a control part 5 through a bus 13, the control part 5 sends polling frames to respective terminal equipments 2 and 3 from a transmitter and receiver 6 through line drivers 7 and 8 at timing T5. The control part 5 supplies selection information 15 to a selector 11 at timing T6 to select a line receiver 9, and then fetches a flag [F] sent from the terminal equipment 2 into a PLL circuit 12 as a synchronizing signal. On the other hand, the terminal equipment 2 having decoded an address field [A] in said polling frame transmits the address field [A], etc., to a terminal controller 1 at timing T7. Therefore, the PLL circuit 12 is synchronized at the timing T7, and a delay time required for sure establishment of synchronization is eliminated.