JP2985957B1 - Phase comparator and digital phase locked loop - Google Patents

Abstract

An object of the present invention is to cancel the influence of a DC offset in an RF signal and improve the pull-in characteristic of a digital phase locked loop. SOLUTION: When a repetition period of a reproduction synchronization clock signal is T, a delay element 11 delays an RF signal by nT time. The subtractor 12 subtracts the current-time RF signal D (t) from the RF signal D (t-nT) output from the delay element 11. The determination circuit 13 uses the RF signal D (t) and the RF signal D (t ± mT) at times before and after the current time t to determine whether the current time RF signal D (t) is at the rising point or the falling point. Is determined. Signal processing circuit 14
Detects the leading or lagging phase of the reproduction synchronous clock signal with respect to the input RF signal using the result of the decision by the decision circuit 13 and the result of the subtraction by the subtractor 12, and outputs a phase error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase synchronizing circuit for reproducing a clock signal synchronized with a reproduction signal on a recording medium on which digital data is recorded, and a phase comparator used for the digital phase synchronizing circuit. It is about.

[0002]

2. Description of the Related Art Optical disk recording devices (CD-ROM, D
When a signal recorded on a recording medium is reproduced in a VD-ROM, DVD-RAM, a magnetic recording / reproducing apparatus (magnetic disk), or the like, a clock signal synchronized with the reproduced signal is required. A phase synchronization circuit is a circuit for reproducing a synchronized clock signal, and includes an RF signal including data.
A (high frequency) signal is read from a recording medium, and a clock signal used for data reproduction is generated from the RF signal. As such a phase locked loop, a conventional analog phase locked loop (PLL: Phase Locked) is used.
Instead, a digital phase-locked loop is used.

FIG. 6 shows an example of a conventional digital phase locked loop circuit. First, an RF signal including data is read from a recording medium on which data is recorded, and input to a waveform equalization circuit 61 to perform waveform equalization so as to have desired characteristics. The output signal of the waveform equalization circuit 61 is converted to an automatic gain adjustment circuit (A
GC) 62 to adjust the gain so as to have a predetermined size. Next, the signal component gain-adjusted by the AGC 62 is input to a low-pass filter (LPF) 63, and the upper limit of the frequency band of the input RF signal is limited so as to be 以下 or less of the frequency of the reproduction synchronous clock signal. The RF signal is sampled by an analog / digital conversion circuit (ADC) 64 using the reproduction synchronous clock signal, and is converted into a digital RF signal. Where AD
The reproduction synchronization clock signal CLK used for C64 is generated by a voltage controlled oscillator (VCO) 68 described later.

[0004] The digital conversion signal sampled by the ADC 64 is input to a digital phase comparator 65,
The phase error with respect to the reference phase is digitally calculated by a method described later. Next, the phase error signal calculated by the digital phase comparator 65 is filtered by the digital loop filter 66. Then, it is converted into an analog signal by a digital / analog conversion circuit (DAC) 67,
Generate a VCO control signal. The VCO 68 is a DAC 67
The reproduction synchronous clock signal CLK is oscillated in response to the analog VCO control signal from the CPU. This reproduction synchronization clock signal CLK is used as a sampling signal in the ADC 64 described above.

Here, the operation of the digital phase comparator 65 for calculating the phase error signal will be specifically described. After detecting the zero-cross point when the phase is locked at the sampling point of the RF signal, the digital phase comparator 65 detects whether the zero-cross point corresponds to the rising or falling of the RF signal. Next, based on the detection result, a phase error signal Perr corresponding to the rising point or the falling point is generated using the value of the zero cross point of the RF signal. In the case of the rising point, the value of the zero cross point is used as the phase error signal Perr. In the case of the falling point, a value obtained by multiplying the value of the zero cross point by (−1) is used as the phase error signal Perr.

Here, as a method of detecting a zero crossing point, an absolute value of a difference signal from the zero level at two sampling points sandwiching the zero level is obtained, and a point having a smaller absolute value is determined as a zero crossing point. There is a way to do it. As a method of detecting the rising point and the falling point of the RF signal, there is a method of determining by using the sign of the sampling point of the RF signal. When the sign changes from-(minus) to + (plus), Can be identified as a rising point, and conversely, if it changes from + (plus) to-(minus), it can be identified as a falling point.

For example, a repetition period T as shown in FIG.
About 8 T for the reproduction synchronous clock signal CLK having
Let us consider a case where an RF signal having a period of? FIGS. 7A to 7C are waveform diagrams showing sampling points of the RF signal by the reproduction synchronous clock signal CLK in the ADC 64. FIG. Point A in the figure indicates a zero cross point at the rising edge of the RF signal, and point B indicates a zero cross point at the falling edge of the RF signal. Here, A point value respectively DT (t _A) of the RF signal at point B, and DT (t _B).

(1): When there is no phase error as shown in FIG. 7 (a), DT (t _A ) た め 0 because point A, which is the zero crossing point of the rising edge of the RF signal, is on the zero level. The phase error signal at point A is Perr (t _A ) ≒ 0
Becomes Similarly, point B, which is the zero-crossing point at the falling edge of the RF signal, also has DT (t _B ) ≒ 0, so that the phase error signal at point B is Perr (t _B ) ≒ 0. (2); When the reproduction synchronous clock signal CLK has a phase lag with respect to the RF signal as shown in FIG.
The zero crossing point A at the rise of the signal is a negative value DT
(T _A ), the zero-cross point B at the fall of the RF signal takes a positive value DT (t _B ). In this case, R
The error signal at point A, which is the rising point of the F signal, is P
err (t _A ) = DT (t _A ), and the phase error signal at point B, which is the falling of the RF signal, is Perr (t _B )
= −DT (t _B ), and the values of the phase error signals at the points A and B both take negative values with respect to the delay phase. (3): As shown in FIG. 7C, when the reproduction synchronization clock signal CLK is advanced in phase with respect to the RF signal, the RF
The zero-cross point A at the rising edge of the signal is a positive value DT
(T _A ), the zero-crossing point B at the fall of the RF signal takes a negative value DT (t _B ). In this case, R
The error signal at point A, which is the rising point of the F signal, is P
err (t _A ) = DT (t _A ), and the phase error signal at point B, which is the falling of the RF signal, is Perr (t _B )
= −DT (t _B ), and the values of the phase error signals at the points A and B both take positive values with respect to the leading phase.

With the above operation, the digital phase comparator 6
5 generates a phase error signal, and operates a digital phase locked loop circuit based on the signal to obtain a reproduced synchronous clock signal CLK.

[0010]

However, as shown in FIG. 8, when the input signal of the digital phase comparator 65 has a DC offset component with respect to the zero level, the detection of the zero cross point in the digital phase comparator 65 is performed. In this case, an erroneous determination occurs. When this erroneous determination occurs, the phases are synchronized at other stable points as shown in FIG. 9, and the phase error is not fed back. Therefore, there is a problem that the phase control cannot be performed properly.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has been made in consideration of the above-described problems, and has been made in view of the above circumstances. A comparator,
It is an object of the present invention to realize a digital phase locked loop circuit using the phase comparator.

[0012]

In order to solve this problem, the present invention according to claim 1 of the present application scans a recording medium on which digital data is recorded, and obtains an RF signal obtained from the recording medium.
When generating a reproduction synchronization clock signal of digital data to be reproduced from a signal, the RF signal is converted to a digital RF signal.
A phase comparator for converting the reference frequency of the digital RF signal into a signal and detecting a phase error between the reference point of the digital RF signal and the reproduction synchronization clock signal, wherein a maximum frequency of the RF signal is f, and a repetition period of the reproduction synchronization clock signal is To T (T ≦ 1 / (2
f)), a delay element for delaying the digital RF signal by nT (n is an integer) time, and a digital RF signal D (t-nT) output from the delay element from the digital RF signal D (t-tT) at the current time. ), And a digital RF signal D (t) at the current time and a digital RF signal D (t ± mT) (m is an integer) at a time before and after the current time t. A judgment circuit for judging whether the RF signal D (t) is at a rising point or a falling point; a judgment result of the judgment circuit and a subtraction result D (t−nT) −D (t) of the subtractor ) Using the input RF
A signal processing circuit for detecting whether the reproduction synchronous clock signal is in a leading phase or a lagging phase with respect to a signal, and outputting a detection result as a phase error signal. is there.

According to a second aspect of the present invention, there is provided a digital phase shifter for scanning a recording medium on which digital data is recorded and generating a reproduction synchronous clock signal of digital data to be reproduced from an RF signal obtained from the recording medium. A synchronization circuit for reducing a waveform distortion of an RF signal obtained from the recording medium, and an output signal of the waveform equalization circuit, wherein the output signal of the waveform equalization circuit is 1/1 of a repetition frequency of the reproduction synchronization clock signal.
A low-pass filter for limiting the band to 2 or less, a DC control circuit for removing a DC offset component included in the RF signal output from the low-pass filter, and an RF signal output from the DC control circuit using the reproduction synchronization clock signal. An analog / digital conversion circuit that samples and converts the signal into a digital RF signal; a maximum frequency of the RF signal is f;
When (T ≦ 1 / (2f)), a delay element that delays the digital RF signal by nT (n is an integer) time, and a digital RF signal D (t−nT) output from the delay element, A subtracter for subtracting the digital RF signal D (t); a digital RF signal D (t) at the current time;
The digital RF signal D (t ± mT) (m
Is an integer) using the digital RF signal D (t) at the current time.
A determination circuit for determining whether the current state is a rising point or a falling point, and an input using a determination result of the determination circuit and a subtraction result D (t−nT) −D (t) of the subtractor. A signal processing circuit for detecting whether the reproduction synchronization clock signal is in a leading phase or a lagging phase with respect to an RF signal, and outputting a detection result as a phase error signal; and a phase error output from the signal processing circuit. A digital / analog conversion circuit for converting a signal into an analog signal, and oscillating the reproduction synchronous clock signal having a frequency corresponding to the analog phase error signal converted by the digital / analog conversion circuit, And a voltage-controlled oscillation circuit to be provided.

[0014]

(Embodiment 1) A phase comparator according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of the phase comparator according to the present embodiment. This phase comparator 10 is a digital RF signal D (t) digitized by an analog / digital conversion circuit.
And digitally calculates the phase error signal Perr. The phase comparator 10 includes a delay element 11, a subtractor 12, a determination circuit 13, and a signal processing circuit 14.

Assuming that the current time is t, the delay element 11 delays the digital RF signal D (t-nT) inputted at the previous time t-nT (n is an integer) by a time nT, and at time t, the digital RF signal D (t-nT). The subtractor 12 outputs the digital RF signal D output from the delay element 12.
From (t-nT), the digital RF signal D (t) at the current time is obtained.
Is subtracted. The determination circuit 13 uses the digital RF signal D (t) at the current time and the digital RF signals D (t ± mT) (m is an integer) at times before and after the current time t to determine the digital RF signal D at the current time. It is to determine whether (t) is in the rising point or the falling point. The signal processing circuit 14 determines the determination result of the determination circuit 13 and the subtraction result D (t−nT) −D of the subtractor 12.
(T) is used to detect whether the reproduction synchronous clock signal is in a leading phase or a lagging phase with respect to the input digital RF signal, and output the detection result as a phase error signal Perr.

In the conventional method, the phase error signal is generated using the zero-cross point of the RF signal. However, the phase comparator 10 according to the present embodiment uses the intermediate point in the waveform of the RF signal to generate the phase error signal. Is generated.
Here, at least 4T with respect to the reproduction synchronous clock signal CLK having a repetition cycle of 1T as shown in FIG.
It is assumed that a digital RF signal D (t) having only one local maximum value or local minimum value and having the maximum frequency component as f is input at the time. Also, the LPF 63 shown in FIG.
Set the passband of. Here, the delay time of the delay element 11 is 2T. As a configuration method of the delay element 11, there is a method of using two D-flip-flops operating on the reproduction synchronization clock CLK. When a phase error signal is generated using the difference signal at the midpoint of the digital RF signal, that is, D (t−2T) −D (t), the difference signal in the lower half of the RF waveform is multiplied by (−1). By taking these values, it is possible to generate a phase error signal corresponding to the delay phase and the advance phase. A method for generating the phase error signal will be described with reference to FIG.

FIGS. 3A to 3C are waveform diagrams showing sampling points of the RF signal in the analog / digital conversion circuit (corresponding to the ADC 64 in FIG. 6) using the RF signal and the reproduction synchronous clock signal CLK. A point A1 in the figure is an intermediate point in the rising edge of the upper half of the RF signal, and A2
The point is the midpoint of the fall in the upper half of the RF signal,
Point B1 indicates an intermediate point at the fall in the lower half of the RF signal, and point B2 indicates an intermediate point at the rise in the lower half of the RF signal. The contents of these sampling points are determined by the determination circuit 13. Here, A1 point, A2
The values of the RF signals at point B1, point B2 and point B2 are respectively represented by DT
(T _A1 ), DT (t _A2 ), DT (t _B1 ), DT (t _B2 )
And

(1): When there is no phase error as shown in FIG. 3A, the difference signal obtained by subtracting the point A2 from the point A1 in the upper half of the RF signal by the subtractor 12 is DT
(T _A1 ) −DT (t _A2 ) ≒ 0. At this time, the signal processing circuit 14 as a phase error signal in the upper half of the RF signal, and outputs the _{Perr = DT (t A1) -DT} (t A2) ≒ 0. The difference signal obtained by subtracting the point B2 from the point B1 in the lower half of the RF signal by the subtractor 12 is also DT.
(T _B1 ) −DT (t _B2 ) ≒ 0. As a phase error signal in the lower half of this time, the signal processing circuit 14 is an RF signal, Perr = - outputting a _{{DT (t B1) -DT (} t B2)} ≒ 0.

(2); As shown in FIG. 3B, when the phase of the reproduced synchronous clock signal CLK is delayed with respect to the RF signal, the subtractor 12 causes the upper half of the RF signal to be at points A1 to A2. Is DT.
(T _A1 ) −DT (t _A2 ) <0. At this time, the signal processing circuit 14 as a phase error signal in the upper half of the RF signal, and outputs the _{Perr = DT (t A1) -DT} (t A2) <0. The difference signal obtained by subtracting the point B2 from the point B1 in the lower half of the RF signal by the subtractor 12 is DT.
(T _B1 ) −DT (t _B2 )> 0. As a phase error signal in the lower half of this time, the signal processing circuit 14 is an RF signal, Perr = - outputting a _{{DT (t B1) -DT (} t B2)} <0. Therefore, a phase error signal having a negative value with respect to the delay phase is generated.

(3); As shown in FIG. 3C, when the phase of the reproduced synchronization clock signal CLK is advanced with respect to the RF signal, the subtractor 12 causes the A1 point to the A2 point in the upper half of the RF signal. Is DT.
(T _A1 ) −DT (t _A2 )> 0. At this time, the signal processing circuit 14 as a phase error signal in the upper half of the RF signal, and outputs the _{Perr = DT (t A1) -DT} (t A2)> 0. The difference signal obtained by subtracting the point B2 from the point B1 in the lower half of the RF signal by the subtractor 12 is DT.
A _{(t B1) -DT (t B2} ) <0. As a phase error signal in the lower half of this time, the signal processing circuit 14 is an RF signal, Perr = - outputting a _{{DT (t B1) -DT (} t B2)}> 0. Therefore, a phase error signal having both positive values with respect to the leading phase is generated.

When the phase comparator 10 is operated as described above, a phase error signal is generated by the difference signal between the RF signals,
The DC offset, which has been a problem in the conventional method, can be canceled, and a phase error signal free from the influence of the DC offset can be generated.

(Embodiment 2) Next, an example in which the phase comparator of Embodiment 1 is applied to an optical disk recording apparatus will be described. FIG. 4 is a configuration diagram of a digital phase locked loop circuit according to Embodiment 2 of the present invention, which is used for an optical disk recording device. As shown in the figure, the optical disk recording device includes an optical disk 401 as an
01, and an RF signal read through the optical pickup 402,
And a digital phase synchronization circuit 400 for extracting a reproduction synchronization clock signal.

FIG. 6 shows a digital phase locked loop circuit 400.
Similarly, the waveform equalizer 403, the automatic gain controller (AGC) 404, the low-pass filter (LP)
F) 405, analog / digital conversion circuit (ADC) 4
07, digital phase comparator 408, digital loop filter 409, digital / analog conversion circuit (DAC) 4
10. A voltage-controlled oscillation circuit (VCO) 411 is provided, which is the same as the conventional example.
Detailed description is omitted. The digital phase-locked loop 400 of the present embodiment has an LPF in addition to the above blocks.
A DC error removal circuit 406 for removing a DC offset of the output signal of the ADC 405 and a DC error detection circuit 4 for detecting a DC offset component included in the output signal of the ADC 407
12 and D which is converted from an output signal of the DC error detection circuit 412 into an analog signal and supplied to the DC error removal circuit 406.
AC413 is newly provided. Here, a DC error removal circuit 406, a DC error detection circuit 412, and a DAC
Reference numeral 413 functions as a DC control circuit that removes a DC offset component included in the RF signal.

The RF signal read from the optical disk 401 includes a synchronization pull-in pattern (VF) as shown in FIG.
O pattern) is included in sector units. The optical disk recording device shown in FIG.
When used as a RAM, data must be reproduced even in the case of high-speed scanning. Since the reproduction speed differs for each sector of the optical disk 401, a synchronization pull-in signal is recorded in the VFO pattern.

The RF signal recorded on the optical disk 401 is read out using the optical pickup 402, and the signal is input to the waveform equalization circuit 403 to perform waveform equalization so as to have desired characteristics. Then, the waveform equalization circuit 403
Is input to the AGC 404, and the gain is adjusted so as to have a predetermined amplitude. Next, the signal component whose gain has been adjusted by the AGC 404 is input to the LPF 405, and the upper limit of the frequency band of the RF signal is limited to be not more than の of the repetition frequency of the reproduction synchronous clock signal. And D
The DC error in the RF signal is
Control to minimize the offset. The output signal of the DC error removing circuit 406 is sampled by the ADC 407 using the reproduced synchronous clock signal, and is converted into a digital signal. Here, the reproduction synchronous clock signal CLK to be used is generated by a VCO 411 described later.

The digital conversion signal sampled by the ADC 407 is converted to a digital phase comparator 408 of the present invention.
Is input to Here, as described above, the phase error with respect to the reference phase is digitally calculated. The phase error signal Perr calculated here is converted to a digital loop filter 40.
9 to convert the signal into a VCO control signal in a range in which the VCO 411 operates. The digital VCO control signal is converted into an analog VCO control signal by the DAC 410 and input to the VCO 411. The VCO 411 generates a reproduction synchronization clock signal CLK having a frequency according to the value of the VCO control signal. This reproduction synchronization clock signal CLK is used as a sampling signal in the ADC 407 described above.

On the other hand, the DC error detection circuit 412
A DC error component is detected as a DC offset from the digital conversion data sampled by C407.
The detection of the DC error component is performed by averaging the values of the sampling points of 8T or more. And DC
After generating a digital signal corresponding to the DC control voltage of the error removing circuit 406, the digital signal is converted into an analog signal by the DAC 413. The DC error elimination circuit 406 is provided by the DAC 41
3 to control the DC component of the RF signal in accordance with the value of the analog DC control signal from
The DC level of the signal is converted.

When a conventional phase comparator is used in such a digital phase-locked loop circuit, when an RF signal having a DC offset is input, pseudo-locking occurs at another stable point. For this reason, the DC control circuit controls the DC in the VFO pattern as shown in FIG.
After removing the offset, the digital phase comparator 408
Is working. In this case, a limited length VFO
Since two operations, DC control and phase synchronization, must be performed using the pattern, sufficient time cannot be obtained for phase synchronization. In particular, in a digital phase locked loop, compared to an analog phase locked loop,
Since the delay time in the phase locked loop is long, the capture range of the frequency at which the phases can be synchronized tends to be narrow.

Therefore, the phase comparator 10 or 408 according to the present invention cancels the influence of the DC offset, so that two operations of DC control and phase synchronization in the VFO pattern can be performed simultaneously. Therefore, all VFO patterns having a limited length can be used for phase synchronization. For this reason, the time for the phase synchronization can be secured more sufficiently than in the case of the conventional phase comparator, and the pull-in characteristic of the digital phase locked loop can be improved.

[0030]

As described above, according to the phase comparator of the first aspect of the present invention, it is possible to cancel the influence of the DC offset in the RF signal and output an accurate phase error signal.

According to the digital phase-locked loop of the second aspect of the present invention, the synchronization pull-in pattern recorded fragmentarily on the recording medium is used, and the DC of the synchronization pull-in pattern is used.
The reproduction synchronization clock signal can be generated at high speed without being affected by the components.

When such a digital phase-locked loop is applied to an optical disk recording apparatus, synchronization can be easily pulled in even when a track on the optical disk is searched at high speed. In this way, data access at the time of variable speed reproduction is more reliable.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a phase comparator according to Embodiment 1 of the present invention.

FIG. 2 is a waveform diagram showing an example of a relationship between an RF signal and a reproduction synchronization clock signal.

FIG. 3 is an RF showing points for generating a phase error signal in the phase comparator according to the embodiment of the present invention;
FIG. 4 is a waveform diagram of a signal.

FIG. 4 is a configuration diagram of a digital phase locked loop circuit according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of intermittent reproduction data having a synchronization pull-in pattern (VFO pattern).

FIG. 6 is a configuration diagram of a digital phase locked loop circuit including a conventional phase comparator.

FIG. 7 is a waveform diagram showing points for generating a phase error signal in a conventional phase comparator.

FIG. 8: R with DC offset to zero level
It is a waveform diagram of F signal.

FIG. 9 is a waveform diagram showing a stable point in an RF signal having a DC offset in a conventional phase comparator.

[Explanation of symbols]

10,408 Digital phase comparator 11 Delay element 12 Subtractor 13 Judgment circuit 14 Signal processing circuit 401 Optical disk 402 Optical pickup 403 Waveform equalization circuit 404 Automatic gain adjustment circuit (AGC) 405 Low pass filter (LPF) 406 DC error removal circuit 407 Analog / digital conversion circuit (ADC) 409 Digital loop filter 410, 413 Digital / analog conversion circuit (DA
C) 411 Voltage-controlled oscillation circuit (VCO) 412 DC error detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/06 G11B 20/14 351 H04L 7/033

Claims (2)

(57) [Claims] When scanning a recording medium on which digital data is recorded and generating a reproduction synchronization clock signal for digital data to be reproduced from an RF signal obtained from the recording medium, the RF signal is converted into a digital RF signal. Converted,
A phase comparator for detecting a phase error between a reference point of the digital RF signal and the reproduction synchronous clock signal, wherein a maximum frequency of the RF signal is f, and a repetition period of the reproduction synchronous clock signal is T (T ≦ T 1 / (2f)), a delay element that delays the digital RF signal by nT (n is an integer), and a digital RF signal D (t−n) output from the delay element.
T) subtracts the digital RF signal D (t) at the current time from T), the digital RF signal D (t) at the current time, and the digital RF signal D (t ± mT) at a time before and after the current time t ( m is an integer), a determination circuit for determining whether the digital RF signal D (t) at the current time is in a rising point or a falling point, and a determination result in the determination circuit and the subtractor Using the subtraction result D (t-nT) -D (t), it is detected whether the reproduction synchronous clock signal is in a leading phase or a lagging phase with respect to the input RF signal, and the detection result is represented by a phase error. A signal processing circuit that outputs the signal as a signal. 2. A digital phase locked loop circuit for scanning a recording medium on which digital data is recorded and generating a reproduction synchronous clock signal of digital data to be reproduced from an RF signal obtained from the recording medium, A waveform equalization circuit for reducing waveform distortion of an RF signal obtained from a recording medium; a low-pass filter for band-limiting an output signal of the waveform equalization circuit to １ ／ or less of a repetition frequency of the reproduction synchronization clock signal; A DC control circuit that removes a DC offset component included in the RF signal output from the low-pass filter; and an analog that samples the RF signal output from the DC control circuit with the reproduction synchronization clock signal and converts the RF signal into a digital RF signal. / Digital conversion circuit; and let the maximum frequency of the RF signal be f, and repeat the reproduction synchronization clock signal. When the return period is T (T ≦ 1 / (2f)), said digital RF signal nT (n is an integer) delay elements for time delay, the output digital RF signals D (t-n of the delay elements
T) subtracts the digital RF signal D (t) at the current time from T), the digital RF signal D (t) at the current time, and the digital RF signal D (t ± mT) at a time before and after the current time t ( m is an integer), a determination circuit for determining whether the digital RF signal D (t) at the current time is in a rising point or a falling point, and a determination result in the determination circuit and the subtractor Using the subtraction result D (t-nT) -D (t), it is detected whether the reproduction synchronous clock signal is in a leading phase or a lagging phase with respect to the input RF signal, and the detection result is represented by a phase error. A signal processing circuit that outputs a signal, a digital / analog conversion circuit that converts a phase error signal output from the signal processing circuit into an analog signal, and an analog phase error converted by the digital / analog conversion circuit. Digital phase locked loop circuit the oscillation of the reproduction synchronization clock signal having a frequency, characterized by comprising a voltage controlled oscillator to be supplied to the analog / digital converter circuit in accordance with the Patent.