JPH09219067A - Digital information reproducer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the pull-in operation of a PLL by detecting the phase from the input side of an equalizer thereby reducing the loop delay of the PLL and to pull-in the PLL with a correct phase by correcting a phase deviation even in the case of causing the phase deviation in the equalizer. SOLUTION: The reproduced signal of a magnetic disk 11 is subjected to an A/D conversion in an A/D converter 15, and the obtained digital reproduced before an equalization is supplied to a phase comparison input changeover unit 22 via an FIR filter for phase deviation correction 21. At the time of the initial pull-in of a phase, a feedback control loop for pulling in of the phase is formed without interposing an equalizer 16 by supplying the output of the FIR filter 21 for phase deviation correction to a phase difference detector 23. The FIR filter 21 corrects the phase deviation between the digital reproduced signal before equalization and the digital reproduced signal equalized by the equalizer 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information reproducing apparatus, and more specifically, when establishing phase synchronization based on a preset repetitive pattern, an initial phase based on a signal before waveform equalization of a reproduced signal. The present invention relates to a digital information reproducing apparatus capable of early establishing phase synchronization without being affected by the loop delay of the waveform equalizer by pulling in the signal.

[0002]

2. Description of the Related Art In a digital information reproducing apparatus, a reproduction signal read from a recording medium is a high frequency analog signal (RF signal). In order to take out digital data from this reproduction signal, it is necessary to generate a data read clock (hereinafter referred to as a synchronous clock) synchronized with the position of the correct data existing point. Sampling points for extracting data from the reproduction signal are defined based on this synchronous clock. A feedback control system called a phase-locked loop (PLL) circuit section is generally used to generate a synchronous clock. P
The LL circuit unit has a sampling point based on sample data indicating a data existing point included in the reproduction signal, and a PL point.
A phase error from a sampling point based on a synchronous clock obtained by free running the voltage controlled oscillator in the L circuit section is detected, and the detected phase error is detected by a voltage controlled oscillator (VCO: Volt
age controlled oscillator) to correct the phase of the synchronous clock.

FIG. 8 is an explanatory diagram showing an example of a recording / reproducing format. As shown in FIG. 8A, a known data string called a preamble is written at the beginning of the sector. The preamble is composed of a phase synchronization pattern for matching the phases of the synchronization clocks and a data synchronization pattern for indicating the head of the user data. Here, the pattern length of the phase synchronization pattern is set in consideration of the time required for the PLL to pull the phase of the synchronization clock within the prescribed range. The phase synchronization pattern is 1,1, -1, -1, -called 4T pattern.
Repeated data of 1 is often used.

The above specified range, that is, the allowable range of phase shift is determined from the viewpoint that it does not affect the error rate of the digital data extracted based on the synchronization clock. Further, the length of the data synchronization pattern and the detection method are selected so that the false detection probability and the non-detection probability are sufficiently smaller than the data error rate.
FIG. 8B shows the timing of opening the read gate. FIG. 8C shows a reproduced signal and a data existing point in the reproduced signal, that is, a point at which the data should be sampled.

FIG. 9 is a block diagram of the essential parts of a conventional digital information reproducing apparatus. Conventional digital information reproducing apparatus 1
00 is the analog filter 101 and the A / D converter 10
2, a digital equalizer 103, and a PLL circuit unit 104.

R is read from a recording medium (not shown) through a read head (not shown) and, if necessary, R (not shown).
The reproduced signal amplified by the F amplifier is the analog filter 1
It is supplied to the A / D converter 102 via 01. The analog filter 101 extracts a signal component in a required band from the reproduction signal. The A / D converter 102 samples the output signal of the analog filter 101 at a sampling point defined based on the synchronous clock output from the PLL circuit unit 104 and converts it into digital data. A / D
The digital reproduction signal output from the converter 102 is supplied to the digital equalizer 103. Digital equalizer 103
Is composed of, for example, a 3-tap FIR filter, and digitally waveform-equalizes the digital reproduction signal and outputs the digital reproduction signal. The digital reproduction signal after equalization is supplied to, for example, a maximum likelihood (Viterbi) decoder or the like.

The PLL circuit section 104 includes a phase error detector 1
05, the D / A converter 106, and the loop filter 107.
And a voltage controlled oscillator (VCO)
llator) 108 and. Phase error detector 105
Calculates the phase error between the synchronous clock generated by the VCO 108 and the digital reproduction signal after equalization, that is, the amount of phase shift by digital calculation, and outputs the calculated phase error data. The D / A converter 106 generates a voltage signal related to the phase error corresponding to the phase error data. The voltage signal related to the phase error is supplied to the phase control voltage input terminal 108a of the VCO 108 via the loop filter 107 having the low-pass type frequency characteristic. VCO108
Is a clock within a preset frequency range and generates and outputs a synchronous clock of a phase specified based on the voltage signal related to the phase error after passing through the filter, which is supplied to the phase control voltage input terminal 108a. .

When the read gate (not shown) is opened, the PLL circuit section 104 first enters an acquisition (learning) mode. In this acquisition mode, the PLL circuit unit 10
4 uses the phase synchronization pattern shown in FIG. 8A to indicate the data existence point and PLL of the digital reproduction signal after equalization.
The pulling is performed from the state in which the phase of the synchronous clock generated in the circuit unit 104 is shifted to the state in which the phase is substantially matched. Next, the data synchronization pattern detection circuit (not shown) detects the data synchronization pattern shown in FIG. 8A, and when the data synchronization pattern detection output is supplied from the data synchronization pattern detection circuit, the PLL circuit unit 104 causes the tracking. Switch to mode. In this tracking mode, the PLL circuit unit 104 performs fine adjustment so that the phase of the data existing point of the equalized digital reproduction signal and the phase of the synchronous clock do not shift.

[0009]

In such a feedback control system, the smaller the loop delay is, the more the phase margin is increased, and stable and fast tracking control is possible. Therefore, the circuit configuration is such that the loop delay is as small as possible. Is the ideal.

Since the 4T pattern, which is a phase synchronization pattern, is as close as possible to a sine waveform, the waveform does not change even through the digital equalizer 103. Therefore, in order to make the loop delay as small as possible, a circuit configuration in which a phase error is detected based on the digital reproduction signal before equalization in the acquisition mode can be considered.

FIG. 10 is a block diagram of the essential parts of a digital information reproducing apparatus for reducing the loop delay in the acquisition mode. The digital information reproducing apparatus 110 shown in FIG. 10 is provided with a phase error detection input switching circuit 111 before the phase error detector 105. The phase error detection input switching circuit 111 supplies the digital reproduction signal before equalization to the phase error detector 105 to specify the mode when the acquisition mode is specified by the mode specifying signal supplied to the input terminal 111a. When the tracking mode is designated by the signal, the equalized digital reproduction signal is supplied to the phase error detector 105. As described above, in the acquisition mode, the loop delay is reduced by the configuration in which the digital reproduction signal before equalization is supplied to the phase error detector 105.

However, when a digital FIR filter is used for the digital equalizer 103, the data existence point phase may change before and after equalization due to the change in the group delay amount depending on the tap coefficient of the digital FIR filter. .

When the phase of the data existing point changes before and after equalization, the phase of the synchronization clock is adjusted based on the digital reproduction signal before equalization during the acquisition mode. The phase of the synchronization clock is synchronized with the phase that is out of phase with the digital reproduction signal. Therefore, there is a high possibility that a phase shift has occurred immediately after switching to the tracking mode.

On the contrary, if the operation in the acquisition mode is performed based on the digital reproduction signal after the equalization, there is no phase shift between the data existence point and the synchronous clock, but the digital equalizer is provided in the feedback control system. Since 103 will be inserted, the loop delay will increase by the amount of the digital equalizer 103 inserted. When the loop delay becomes large, the stability of the control system deteriorates and pull-in becomes slow. It becomes necessary to lengthen the section length of the phase synchronization pattern according to the delay of pull-in, which leads to deterioration of the recording format efficiency on the recording medium, that is, the recording efficiency of user data.

As described above, in the digital information reproducing apparatus 110 shown in FIG. 10, from the viewpoint of the loop delay of the feedback control system, the phase of the synchronous clock is pulled in based on the digital reproduced signal before equalization. The phase is pulled in quickly and is stable. However,
Since the digital reproduction signal before equalization and the digital reproduction signal after equalization may be out of phase with each other, the phase is not correctly pulled in with respect to the digital reproduction signal after equalization.

The present invention has been made to solve such a problem. Even if a phase shift occurs in the equalizer, the phase of the synchronizing clock is adjusted based on the digital reproduction signal before equalization. It is an object of the present invention to provide a digital information reproducing device that can be correctly performed.

[0017]

In a digital information reproducing apparatus according to the present invention, a reproduction signal read from a recording medium is reproduced by A
A digital reproduction signal is obtained by D / D conversion, the digital reproduction signal is waveform equalized by a digital equalizer, and the equalized digital reproduction signal is output. Phase error detection input of the phase error detector is performed so that phase error detection is performed based on the digital reproduction signal before equalization, and phase error detection is performed based on the digital reproduction signal after equalization after the initial phase pull-in operation is completed. An error detection input switching unit and a phase shift correction unit that corrects a sampling phase shift included when a phase error is detected based on a digital reproduction signal before equalization are provided.

In this digital information reproducing apparatus, the phase shift correcting means can be constructed by providing the phase shift correcting filter in the preceding stage of the phase error detector. Further, by providing a correction adder that corrects and adds the phase shift amount to the phase error detection output of the phase error detector, the phase shift correction means can be configured. Furthermore, the amount of phase shift between the digital reproduction signal after waveform equalization by the digital equalizer and the digital reproduction signal before equalization is a fixed value that is uniquely determined by the filter coefficient of the digital equalizer.
When phase detection is performed based on the digital reproduction signal before equalization, the digital reproduction signal after equalization is corrected by correcting the phase shift amount of a fixed value that is uniquely determined by the filter coefficient of the digital equalizer. It is possible to obtain the same result as when the phase detection is performed based on

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a phase shift correction FI according to the present invention.
It is a block diagram of a digital information reproducing apparatus provided with an R filter. The digital information reproducing apparatus 1 includes a magnetic disk 11 as a recording medium and a magnetic reproducing head 12 for reading digital information recorded on the magnetic disk 11.
An RF amplifier 13 for amplifying an RF (high frequency) signal read by the magnetic reproducing head 12, an analog filter 14 for extracting a signal component in a required band from a reproduction signal output from the RF amplifier 13, and an analog filter 14. An A / D converter 15 for sampling / quantizing an output signal based on a synchronous clock, and digitally waveform-equalizing the A / D-converted digital reproduction signal to generate and output the digital reproduction signal. It comprises a digital equalizer 16 and a PLL circuit section 20 for generating a synchronization clock synchronized with the phase of the correct data existence point based on the digital reproduction signal before equalization and the digital reproduction signal after equalization.

The PLL circuit section 20 includes a phase shift correction FIR filter 21, which is a phase shift correction unit, a phase error detection input switch 22, a phase error detector 23, a D / A converter 24, and a loop filter. 25 and a voltage controlled oscillator (VCO) 26.

The digital reproduction signal before equalization is supplied to one input terminal 22a of the phase error detection input switch 22 via the phase shift correction FIR filter 21. The digital reproduction signal after equalization is supplied to the other input terminal 22b of the phase error detection input switch 22. The phase error detection input switch 22 includes a switching control input terminal 22 from the input terminal 22d.
Based on the mode designation signal supplied to c, one of the input terminals 22a and 22b is selected and output from the output terminal 22e. The phase error detection input switch 22 is
When the mode designation signal 22d indicates the acquisition (learning) mode, the phase shift correction FIR
An output signal of the filter 21 (hereinafter referred to as a phase shift correction digital reproduction signal) is supplied to one phase error detection input terminal 23a of the phase error detector 23. When the mode designation signal indicates the tracking mode, the phase error detection input switch 22 outputs the equalized digital reproduction signal to one of the phase error detection input terminals 23 of the phase error detector 23.
supply to a.

The mode designation signal is supplied from a mode determination unit (not shown). The mode determination unit (not shown)
A mode designating signal 22d indicating that the mode is the acquisition mode is supplied at a timing synchronized with the reproduction timing of the phase synchronization pattern shown in FIG. 8A, and a mode designating signal 2 indicating that the mode is the tracking mode in other periods.
Supply 2d.

The phase error detector 23 obtains the phase error of the output signal of the phase error detection input switch 22 by digital calculation, and obtains the obtained phase error data 23c by D / A.
Supply to the converter 24. In this phase error detector 23,
For example, the determination result Y _n sampled values y _n of the input data and the sampling value y _n of the input _{data, Δτ n = -y n · Y} n-1 + y n-1 · Y n ··· (1) comprising computing The phase error Δτ _n is calculated by the equation (1).

The D / A converter 24 generates a voltage signal related to the phase error corresponding to the phase error data. The voltage signal related to the phase error is supplied to the phase control voltage input terminal 26a of the VCO 26 via the loop filter 25 having the low-pass type frequency characteristic.

The VCO 26 generates a synchronous clock having a phase within a preset frequency range and having a phase specified on the basis of a voltage signal relating to a phase error after passing through the filter, which is supplied to the phase control voltage input terminal 26a. And output.

The digital reproduction signal before equalization and the digital reproduction signal after equalization are out of phase by a fixed amount defined by the configuration of the digital equalizer 16. The phase shift correction FIR filter 21 receives the digital reproduction signal before equalization and outputs a phase shift correction digital reproduction signal having the same phase as the equalized digital reproduction signal waveform-equalized by the digital equalizer 16. Configured to do so.

Here, the digital reproduction signal before equalization is supplied from the magnetic disk 11 to the phase error detector 23 via the phase shift correction FIR filter 21 and the phase error detection input switch 22 as shown in FIG. Only the timing at which the phase synchronization pattern including the 4T pattern shown is read. Since the 4T pattern is as close as possible to a sine wave,
The waveform shape does not change even through the digital equalizer 16. That is, since the phase shift correction FIR filter 21 needs to correct only the 4T pattern and corrects only the phase of the 4T pattern, the number of taps can be reduced as compared with the digital equalization filter 16, and the number of taps can be reduced. By doing so, the delay can be reduced.

As described above, the phase shift correction FIR filter 21 has a smaller number of taps than the digital equalizer 16, and the delay of the phase shift correction FIR filter 21 is the digital equalizer 16. It is configured to be smaller than the delay of.

Next, a specific example in which the digital equalizer 16 has a 3-tap configuration and the phase shift correction FIR filter 21 has a 2-tap configuration will be described. When a 4T pattern is sampled at a certain phase, A, B, -A, -B,
Outputs of A, B, -A ... Are obtained. here,
A, B, -A, -B are quantized values (digital data) of the digital reproduction signal obtained by A / D converting the reproduction signal by the A / D converter 15.

The digital data y _n of the digital reproduction signal after equalization which is the output of the digital equalizer 16 is y _n = k _{1 when} the filter coefficients of the digital equalizer 16 are k ₁ , 1, k _2. a _{· x n + x n-1} + k 2 · x n-2 ··· (2). Here, x _n , x _n-1 , and x _n-2 are the above-mentioned A,
As with B and -A, the reproduced signal is A / D converted by the A / D converter 15.
It is a quantized value (digital data) of the digital reproduction signal obtained by conversion.

Using the above assumption, since x _n-2 = -x _n , if k ₁ = k ₂ , the input sequence is output as it is and the phase does not change. If k ₁ ≠ k _2, then x
Substituting _n−2 = −x _n , y _n = (k ₁ −k ₂ ) · x _n + x _n−1 (3) holds. Therefore, in this case, in order to equalize only the 4T pattern, the coefficient of 1 (k ₁ −k ₂ ) is 2
It is sufficient to use the phase shift correction FIR filter 21 having the tap structure. In addition, there is no noise signal mentioned above,
The precondition that there is no phase change is not strictly satisfied, but random noise components are canceled, so
It does not have a big impact.

FIG. 2 is a block diagram showing a concrete example of the FIR filter for phase shift correction. Phase shift correction F
The IR filter 21 has a two-tap configuration and includes a unit delay element 211 that delays the digital reproduction signal before equalization by one cycle of the synchronization clock based on the synchronization clock, and a filter coefficient () for the digital reproduction signal before equalization. a multiplier 212 for multiplying k ₁ −k ₂ ) and an adder 21 for adding the unit delay output of the unit delay element 211 and the multiplication output of the multiplier 212.
3.

Next, the operation of the digital information reproducing apparatus 1 shown in FIG. 1 will be described. At the timing of reading the phase synchronization pattern in the digital information recorded on the magnetic disk 11 in sector units, the mode control signal indicating the acquisition mode is the switching control input terminal 22c of the phase error detection input switch 22. Is supplied to. As a result, the phase error detection input switch 22 selects the phase shift correction digital reproduction signal output from the phase shift correction FIR filter 21 and supplies it to one input terminal 23 a of the phase error detector 23.

Therefore, in the acquisition mode in which the synchronization clock is pulled in based on the phase synchronization pattern consisting of the 4T pattern, the phase with the delay smaller than that of the digital equalizer 16 does not go through the digital equalizer 16 with a large delay. Using the shift correction FIR filter 21, the phase of the data existing point in the phase synchronization pattern composed of the 4T pattern becomes the same as the phase of the data existing point in the digital reproduction signal after equalization output from the digital equalizer 16. A phase shift correction digital reproduction signal corrected so that the phase error is detected by the phase error detector 23, the detected phase error data is converted into a voltage signal related to the phase error by the D / A converter 24, The voltage signal related to the phase error is passed through the loop filter 25 to the phase control voltage input terminal 2 of the VCO 26. It is supplied to the a, a feedback control so that the phase synchronized clock phase data present point in the phase synchronization pattern matches are made.

As described above, since the digital information reproducing apparatus 1 according to the present invention can form the feedback control loop for the phase pull-in without the intervention of the digital equalizer 16 having a large delay, the PLL circuit section 20 is Fast and stable phase pull-in is possible. Therefore, the pattern length of the phase synchronization pattern arranged at the head of the sector for phase pull-in can be shortened, and the efficiency of the recording format, that is, the user data ratio can be improved.

In the tracking mode after the phase pull-in based on the phase synchronization pattern is completed, the phase error detection input switch 22 selects the equalized digital reproduction signal and supplies it to the phase error detector 23. Feedback control is continued so that the phase of the synchronous clock that has been phase-locked based on the equalized digital reproduction signal does not shift.

In the acquisition mode, the phase correction shift correction FIR filter 21 is used to generate a phase shift correction digital reproduction signal corrected to have the same phase as the data existing point in the equalized digital reproduction signal. Phase shift correction Since the phase of the synchronous clock is pulled in based on the digital reproduction signal, the phase error detector 2
Even in the tracking mode after switching the input of 3 to the digital reproduction signal after equalization, the phase of the data existence point in the digital reproduction signal after equalization and the phase of the synchronization clock are stable and stable. Data reproduction continues.

In FIG. 1, the phase shift correction FIR filter 21 is provided separately from the digital equalizer 16, but the digital equalizer 16 is used for the phase shift correction F.
The IR filter may be shared by time division. In this case, in the acquisition mode, the equalization characteristic of the digital equalizer 16 is the phase shift correction FIR filter 2
The filter coefficient is switched so as to be equivalent to 1, and the intermediate calculation result is supplied to the phase error detector 23. With the configuration in which the digital equalizer 16 is shared as a phase shift correction FIR filter in a time division manner, an increase in hardware can be almost ignored.

As described above, in FIG. 1, the phase error detector 2
The phase shift correction F is provided on the front side of 3 as phase shift correction means.
The configuration is shown in which the IR filter 21 is provided to correct the phase shift between the digital reproduction signal before equalization, the digital reproduction signal after equalization, and the data existing point in each reproduction signal. Next, a configuration for correcting the phase shift of the data existing point in each reproduction signal on the subsequent stage side of the phase error detector 23 will be described.

FIG. 3 is a block diagram of a digital information reproducing apparatus having a phase shift correcting adder according to the present invention. In the digital information reproducing apparatus 2 shown in FIG. 3, the configuration of the PLL circuit section 30 is different from that shown in FIG. The PLL circuit section 30 includes a phase error detection input switch 32, a phase error detector 23, a correction adder 33 that constitutes a phase shift correction unit, and a correction addition value supplied to the correction adder 33 in each mode. A correction addition value switch 34 for switching according to
The A converter 24, the loop filter 25, and the VCO 26 are provided.

When the mode designation signal indicates the acquisition mode, the phase error detection input switch 32 selects the digital reproduction signal before equalization to detect one phase error of the phase error comparator 23. When the mode designation signal is supplied to the input terminal 23a and indicates that the mode is the tracking mode, the equalized digital reproduction signal is selected and one of the phase error detection input terminals 2 of the phase error comparator 23 is selected.
Supply to 3a.

The correction adder 33 is the phase error detector 23.
The correction addition value supplied from the correction addition value switching unit 34 is added to the phase error data output from, and the addition result is supplied to the D / A converter 24.

When the mode designation signal indicates the acquisition mode, the correction addition value switch 34 includes the phase error data when the phase error is detected based on the digital reproduction signal before equalization. The offset value Δk for correcting the phase shift amount that is being output is output, and a value of zero is output when the mode designation signal indicates the tracking mode.

FIG. 4 is a graph showing the measurement result of the phase error detection output of the phase error detector. The horizontal axis is the number of samples (bit). The vertical axis represents the digital output data value of the phase error detector. The solid line shows the output when the phase error is detected from the digital reproduction signal after equalization, and the dotted line shows the output when the phase error is detected from the digital reproduction signal before equalization.
The measurement was performed by superimposing sinusoidal jitter on the reproduced signal of the phase synchronization pattern composed of the 4T pattern. The sine wave has a period of 400 samples, an offset of 0, and an amplitude of 0.1 bit.
(Zero-peak), and 0 when the phase can be detected correctly
It should be a sine wave that is vertically symmetrical with respect to.

As shown in FIG. 4, when phase error detection is performed based on the equalized digital reproduction signal, the time change characteristic of the phase error data output from the phase error detector 23 is as follows. The characteristics are vertically symmetrical with respect to the dotted line indicating the position of 0, but when phase error detection is performed based on the digital reproduction signal before equalization, the time change characteristics of the phase error data output from the phase error detector 23. Does not have a vertically symmetrical characteristic with respect to the dotted line indicating the position where the phase error data is 0, and the characteristic (dotted line) when the phase error is detected based on the digital reproduction signal before equalization is equalized. The characteristic is such that an offset is added to the characteristic (solid line) when the phase error is detected based on the subsequent digital reproduction signal.

Therefore, in the acquisition mode in which the phase error is detected based on the digital reproduction signal before equalization,
In the phase error data output from the phase error detector 23,
By adding the value Δk that cancels the offset, it is possible to supply the D / A converter 24 with substantially the same phase error data as that when the phase error is detected based on the digital reproduction signal after the equalization.

With the above configuration, the digital information reproducing apparatus 2 shown in FIG. 3 sends the digital reproduction signal before equalization to the phase error detector 23 via the phase error detection input switch 32 in the acquisition mode. The phase and phase difference detection is performed by supplying the phase difference data, and the correction addition value Δk supplied from the correction addition value switching unit 34 is added by the adder 33 to the phase error data which is the detection output, thereby performing digital reproduction after equalization. It is possible to supply the phase error data corrected to a value almost equal to that when the phase error is detected based on the signal to the D / A converter 24.

In the digital information reproducing apparatus 1 shown in FIG. 1, the digital reproduction signal before equalization is converted into the FIR for phase shift correction.
The phase error detector 23 is supplied via the filter 21, that is, the phase shift correction FIR filter 21 is provided in the feedback control loop for phase acquisition in the acquisition mode. There is a delay of the filter 21. On the other hand, the digital information reproducing apparatus 2 shown in FIG.
Since the digital reproduction signal before equalization is directly supplied to the phase error detector 23, the delay of the feedback control loop for phase pull-in can be further reduced, and faster and more stable phase pull-in can be performed. For example, the digital equalizer 16 has a 3-tap FI.
In the case of the R filter, a delay of about 3 to 4 tap delay can be reduced. Further, since it is only necessary to newly provide the correction adder 33 and the correction addition value switch 34, the circuit scale is slightly increased.

FIG. 5 is a graph showing the measurement results of the phase detection characteristics when the phase shift correction digital FIR filter is used and when the phase shift correction adder is used. The horizontal axis represents the phase offset on a bit scale. The vertical axis represents the digital output data value of the phase error detector.

The solid line shows the phase error detection output characteristic based on the digital reproduction data after equalization, and the dotted line shows the phase shift correction FI.
When the R filter 21 is used, that is, the PL shown in FIG.
The phase error detection output characteristic of the L circuit section 20 is shown, and the alternate long and short dash line shows the phase error detection output characteristic of the PLL circuit section 30 shown in FIG. 3 when the phase shift correction value Δk is added.

The conditions used for the measurement are as follows. The filter coefficient of the digital equalizer 16 is k ₁ , 1, k ₂ , and the filter coefficient of the phase shift correction FIR filter 21 is (k ₁
-K ₂ ) and the phase shift correction value Δk is 2 · (k ₁ −k ₂ ) ·
It is ref_level.

That is, from the above equation (1) of the phase error Δτ _n in the phase error detector 23 and the equation (2) of the phase shift correction FIR filter 21, the phase error output after equalization is − (K ₁ · x _n + x _n-1 + k ₂ · x _n-2 ) · Y _n-1 + (k ₁ · x _n-1 + x _n-2 + k ₂ · x _n-3 ) y _n-1 · Y
_n , and the phase error output before equalization is −x _n · X _n−1 + x _n−1 · X _n , so if Y _n ≈X _n and the difference between the two is taken, − (k ₁ · the _{x n + k 2 · x n} -2) · X n-2 + (k 1 · x n-1 + k 2 · x n-3 · X n-1 and comprising .4T phase synchronization pattern, x _n = - Since x _n-2 and x _n-1 = −x _n-3 are established, by substituting these, − (k ₁ −k ₂ ) × _xn · X _n-2 + (k ₁ −k ₂ ) _{· x n-1 · X n} -1 = (k 1 -k 2) · (-x n · X n-2 + x n-1 · X n-1) is a ... (4), the premise of 4T Therefore, since x _n · X _n−2 = −x _n x _n−1 · X _n−1 = x _n−1 , the formula (4) is (k ₁ −k ₂ ) · (x _n + x _{n −1} ) and (x _n + x _{n −1} ) / 2 = ref_level, the phase shift correction value Δk is 2 · (k ₁ −k ₂ ).
・ Ref_level.

As described above, both the phase error detection output characteristics when the phase shift correction FIR filter 21 is used and when the phase shift correction value Δk is added, the phase based on the digital reproduction signal after equalization is obtained. It almost agrees with the error detection output characteristic. Therefore, it is understood that even if the phase pull-in is performed based on the digital reproduction signal before equalization, the operation equivalent to that when the phase pull-in is performed based on the digital reproduction signal after equalization is possible.

FIG. 6 is a block diagram of another digital information reproducing apparatus equipped with the phase shift correcting adder according to the present invention. The digital information reproducing device 3 shown in FIG.
Two sets of phase error detectors 41 and 42 are provided in the circuit unit 40. One of the phase error detectors 41 detects a phase error between the digital reproduction signal before equalization and the synchronization clock. The correction addition value Δk is added to the output phase error data by the correction adder 33 to obtain the addition result. The other phase error detector 42 detects the phase error between the equalized digital reproduction signal and the synchronization clock. The phase error detection output selection switch 43 supplies the addition result to the D / A converter 24 in the acquisition mode based on the mode designation signal, and outputs the phase error data output from the other phase error detector 42 in the tracking mode. It is supplied to the D / A converter 24.

P of the digital information reproducing apparatus 3 shown in FIG.
In the LL circuit section 40, it is not necessary to switch the correction addition value Δk given to the correction adder 33, and the loop delay in the tracking mode is reduced.

FIG. 7 is a block diagram of a digital information reproducing apparatus provided with the correction voltage superimposing means according to the present invention.
PLL circuit unit 50 of digital information reproducing apparatus 4 shown in FIG.
Is provided with an analog adder 51 as a correction voltage adding means on the output side of the D / A converter 24. In the acquisition mode, the correction voltage is corrected with respect to the voltage signal related to the phase error based on the digital reproduction signal before equalization. The phase shift is corrected by superimposing the correction voltage supplied from the supply unit 52. The correction voltage supply unit 52 is configured to supply a correction voltage (ΔV) for canceling the offset when in the acquisition (learning) mode based on the mode designation signal, and to supply a correction voltage of 0 volt in the tracking mode. doing.

PL of the digital information reproducing apparatus 4 shown in FIG.
Since the L circuit section 50 is configured to correct the phase shift in the analog circuit system after D / A conversion, fine adjustment is possible. Correction adder 33 shown in FIGS. 3 and 6
In the configuration in which the correction addition value is added by using, the delay occurs by the addition processing time when the addition processing is performed by software. In the configuration in which the voltage correction is performed by the analog system shown in FIG. 7, there is no delay for the addition processing, and therefore the delay of the feedback control system can be further reduced.

[0059]

As described above, the digital information reproducing apparatus according to the present invention detects the phase error based on the digital reproduction signal before equalization during the initial phase pull-in operation by the repetitive pattern reproduction. Since the configuration is provided with the phase shift correction means for correcting the shift of the sampling phase included when the phase error is detected based on the digital reproduction signal of, the initial phase pull-in operation does not pass through the equalizer with a large delay. The phase can be detected. Therefore, the delay of the feedback control system of the PLL can be reduced, and the phase can be pulled in quickly and stably. Therefore, the pattern length of the phase synchronization pattern arranged at the head of the sector for phase pull-in can be shortened, and the efficiency of the recording format, that is, the user data ratio can be improved.

[Brief description of drawings]

FIG. 1 is a digital FIR for phase shift correction according to the present invention.
It is a block configuration diagram of a digital information reproducing apparatus provided with a filter.

FIG. 2 is a block diagram showing a specific example of an FIR filter for phase shift correction.

FIG. 3 is a block configuration diagram of a digital information reproducing apparatus including a phase shift correcting adder according to the present invention.

FIG. 4 is a graph showing measurement results of phase detection characteristics before and after equalization.

FIG. 5 is a graph showing the measurement results of the phase detection characteristics when the digital FIR filter for phase shift correction is used and when the adder for phase shift correction is used.

FIG. 6 is a block configuration diagram of another digital information reproducing apparatus including the phase correction adder according to the present invention.

FIG. 7 is a block diagram of a digital information reproducing apparatus provided with a correction voltage adding means according to the present invention.

FIG. 8 is an explanatory diagram showing an example of a recording / reproducing format.

FIG. 9 is a block diagram of a main part of a conventional digital information reproducing apparatus.

FIG. 10 is a block diagram of a main part of an improved conventional digital information reproducing apparatus for reducing the loop delay in the acquisition mode.

[Explanation of symbols]

1, 2, 3, 4 Digital information reproducing device, 11 magnetic disk, 12 magnetic reproducing head, 15 A / D converter, 16 digital equalizer, 20, 30, 40,
50 PLL circuit section, 21 Phase shift correction FIR filter, 22, 32 Phase error detection input switcher, 2
3, 41, 42 Phase error detector, 24 D / A converter, 25 loop filter, 26 VCO, 33
Correction adder, 34 correction addition value switcher, 43
Phase error detection output selection switch, 51 analog adder,
52 Correction voltage supply unit

Claims (7)

[Claims] 1. A reproduction signal read from a recording medium is A /
D conversion to obtain a digital reproduction signal, waveform equalization of this digital reproduction signal by a digital equalizer, and output of the equalized digital reproduction signal. Equalization during initial phase pull-in operation by repetitive pattern reproduction Phase error is detected based on the previous digital reproduction signal, and after completion of the initial phase pull-in operation, phase error detection is switched based on the digital reproduction signal after equalization. A digital information reproducing apparatus comprising: a detection input switching unit and a phase shift correcting unit that corrects a sampling phase shift included when a phase error is detected based on a digital reproduction signal before equalization. 2. The phase shift correction means comprises a phase shift correction FIR filter having a smaller number of taps and a smaller delay than the digital equalizer, and a digital reproduction signal before equalization is processed by the phase shift correction FIR filter. 2. The digital information reproducing apparatus according to claim 1, wherein the phase error detection input switching means is supplied via the phase error detection input switching means. 3. The digital equalizer has 2n-1 taps, and tap coefficients thereof are k ₁ , ..., K _n , k _{n + 1} ,
.., k _2n−1 , the FIR for phase shift correction
The tap coefficients of the filter are k ₁ -k _2n-1 , K ₂ -K _2n-2 ,
..., digital information reproducing apparatus according to claim 2, characterized in that the _{K n-1 -k n + 1} , k n. 4. The digital information reproducing apparatus according to claim 1, wherein the phase shift correcting means is composed of a correcting adder for correcting and adding a phase shift amount to a phase error detection output of the phase error detector. apparatus. 5. The phase shift correction means is a phase shift amount for a voltage signal relating to a phase error obtained by D / A converting the phase error detection output of the phase error detector by a D / A converter. 2. The digital information reproducing apparatus according to claim 1, wherein the digital information reproducing apparatus is constituted by a correction voltage adding means for adding or subtracting the offset correction voltage corresponding to. 6. The digital information reproducing apparatus according to claim 1, wherein the recording medium is a magnetic recording medium, and a magnetic reproducing head for reproducing a signal recorded on the magnetic recording medium is provided. . 7. Digital data encoded by a precoder is recorded on the recording medium, a reproduction signal read from the recording medium is D / A-converted, and the D / A-converted signal is digital equalizer. 2. The digital information reproducing apparatus according to claim 1, wherein the information transmission path from the waveform equalization to the output of the digital reproduction signal after equalization is constituted by a partial response system.