KR100694055B1 - Wobble phase loop locked - Google Patents

Abstract

The present invention relates to a wobble phase locked loop that detects a wobble signal on an optical recording medium and outputs a PLL clock signal that reduces a phase difference error with the detected wobble signal. The wobble signal and the output phase PLL clock read from the optical recording medium are described. An operation unit outputting a counter control signal by performing an operation using the signal; A counter unit for outputting a frequency control signal of an output PLL clock by a counter control signal output from the calculating unit; And a storage unit configured to output a PLL clock signal phase-locked with an input wobble signal by a frequency control signal of the counter unit.

According to the present invention, data recording and reproducing on the optical recording medium can be performed more correctly by generating a PLL clock signal which reduces the phase difference with the wobble signal on the optical recording medium.

Wobble, PLL

Description

Wobble phase loop locked}

1 shows a partial disk structure of a DVD-RAM, which is a type of optical recording medium according to the prior art.

FIG. 2 is a block diagram of a conventional wobble PLL for generating a reference clock using a wobble signal on an optical recording medium as shown in FIG.

3 is a block diagram showing the configuration of a wobble PLL according to an embodiment of the present invention.

4 is a graph showing a change in the value of S _4A (kT) according to the phase difference ωpT value between the input wobble signal S (kT) and the output signal S ₁ (kT) of the first storage unit.

Figure 5 is the output signal S ₉ (kT), the output signal of the comparator S ₁₀ (kT), the output signal of the second counter S ₁₁ (kT), and a first storage output of the first counter at the wobble PLL according to the invention Timing diagram showing signal S ₁ (kT).

<Description of Main Parts of Drawings>

101: band pass filter 102: analog / digital conversion unit

103: multiplier 104: first delay portion

105: subtraction unit 106: first addition unit

107: second delay unit 108: first constant setting unit

109: second constant setting unit 110: divider

111: second addition unit 113: comparator

114: first counter 115: second counter

116: first storage unit 117: second storage unit

118: oscillator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical recording medium reproducing and recording apparatus, and more particularly, to a wobble phase locked loop that detects a wobble signal on an optical recording medium and outputs a PLL clock signal which reduces a phase difference error with the detected wobble signal. (wobble Phase Loop Locked, hereinafter referred to as 'wobble PLL').

In general, in the case of recording and reproducing data from optical recording media such as DVD-RAM, DVD-ROM, etc., the wobble PLL circuit operates as a reference signal for recording and reproducing in response to the wobble signal on the optical recording media. Generate and output a signal.

1 shows a partial disk structure of a DVD-RAM, which is a kind of optical recording medium according to the prior art.

On the surface of a disc of a general optical recording medium including a DVD-RAM, a concentric track is formed from the center of the disc to enable recording. In order to record data at a desired position on the surface of the disc, a function of following the track of the data recording portion and recording the data at the desired portion is required. To implement this function, a series of tasks are needed to find out where the disk pickup is located. To make this possible, a single frequency signal called a wobble is created on the disk surface. As shown in Fig. 1, the wobble signal is recorded along the track. Between the wobble signals, a header which records the position information of the disc in a certain rule is inserted, and the current position or address can be known by reading the header.

2 is a block diagram schematically illustrating a configuration of a conventional wobble PLL 20 that generates a reference clock using a wobble signal on an optical recording medium as shown in FIG. 1.

The wobble signal read out from the optical recording medium such as a DVD-RAM or the like is filtered by the band pass filter 10 to remove noise components and the like, and then the digital signal by the analog-to-digital converter 11. Is converted to.

The phase detector 22 slices the wobble signal converted into the digital signal by the A / D converter 11 to a preset reference level and binarizes it to a high or low level to generate and output a digitized wobble signal. In addition, the phase difference between the wobble signal converted into the digital signal and the PLL clock output from the digital voltage-controlled oscillator (DCO) 24 is compared and calculated and output to the loop filter 23.

The loop filter 23 adjusts the voltage value input to the digitally controlled oscillator 24 based on the phase error value output from the phase detector 22.

The digitally controlled oscillator 24 includes a counter for generating and outputting a fixed frequency signal according to the voltage value output from the loop filter 23.

In addition, to compensate for the phase difference between the wobble signal and the PLL clock, a bidirectional phase error compensator 21 is included to synchronize the wobble signal and the PLL clock together with the loop filter 23 and the digitally controlled oscillator 24. do.

The PLL clock generated and output by the wobble PLL 20 constructed and operated as described above is applied to the bit detector 15 to which the A / D converted wobble signal is input, and in the bit detector 15, the PLL clock is applied. The clock is used to detect and convert the A / D converted wobble signal into a bit stream having a value of 1 or 0.

However, the conventional wobble PLL includes some jitter in the PLL clock output from the digitally controlled oscillator 24 due to the jitter characteristic of the input wobble signal itself.

In addition, since the input wobble signal includes noise having a constant value, a part of the information may be lost in the step of binarizing the input wobble signal, which may result in a larger phase error.

In addition, the frequency of the PLL clock generated in the conventional wobble PLL is limited. Because of this, if the frequency of the actual wobble signal is between two frequencies output from the PLL clock generator, the conventional wobble PLL does not generate a PLL clock synchronized to the frequency of the actual wobble signal, and one of the two adjacent frequencies. Will output the PLL clock signal. In other words, the precision of the output PLL clock frequency is poor.

In addition, the conventional phase error correction apparatus has a problem of being sensitive to asymmetry of the input wobble signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a wobble PLL which reduces a phase difference between an input wobble signal and an output PLL clock signal in a reproducing and recording apparatus of a high density optical recording medium. have.

According to an aspect of the present invention, a wobble PLL includes: a first storage unit configured to output a sine wave signal having the same frequency as a wobble signal read from an optical recording medium;
A multiplier for multiplying the wobble signal read out from the optical recording medium and a sine wave signal output from the first storage unit, a first delay unit for delaying and outputting the signal output from the multiplier, and an input signal by one clock period Subtracts the output signal of the first delay unit from the second delay unit for delaying output, the first adder for adding the output signal of the multiplier and the output signal of the second delay unit, and the output signal of the first adder; A subtractor for outputting to the second delay unit, a divider for dividing a signal output from the second delay unit into a predetermined constant value, and a second adder for adding and outputting a predetermined constant value to a signal output from the divider; And a counter control signal by performing an operation using the read wobble signal and a sine wave signal output from the first storage unit. Power unit for;
A counter unit for outputting a signal for controlling the frequency of the PLL clock signal by the counter control signal output from the calculating unit; And
And a second storage unit configured to output a PLL clock signal phase-locked with the wobble signal according to the frequency control signal output from the counter unit.

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The counter unit may include: a first counter configured to output a signal whose magnitude and frequency are controlled depending on a counter control signal output from the calculator; A comparator for comparing a counter control signal with an output signal of the first counter and outputting a counter hold signal; And a second counter part which is held by the counter hold signal of the comparator and outputs a signal for controlling the frequency of the PLL clock.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a wobble PLL according to an embodiment of the present invention.

As shown, a wobble PLL according to an embodiment of the present invention uses a band pass filter 101, an analog-to-digital converter (ADC) 102, and a wobble signal read from an optical recording medium. An operation unit 110 for outputting a counter control signal by performing a predetermined operation, a counter unit 120 for outputting a frequency control signal of an output PLL clock based on the counter control signal, and an input wobble signal according to the frequency control signal; And a storage unit 130 for outputting a phase locked PLL clock.

The calculator 110 may include a multiplier 111, a first delay unit 112, a subtraction unit 113, a first adding unit 114, a second delay unit 115, a first constant setting unit 116, It is comprised including the 2nd constant setting part 117, the divider 118, and the 2nd addition part 119. FIG. In addition, the counter unit 120 includes a comparator 121, a first counter 122, a second counter 124, and an oscillator 123, and the storage unit 130 includes a first storage unit ( 131, and a second storage unit 132.

The bandpass filter 101 filters noise components included in an input wobble signal.

The analog / digital converter 102 converts the wobble signal filtered by the band pass filter 101 into a digital signal.

The operation unit 110 controls the counter unit 120 by performing a predetermined operation using the wobble signal output from the analog / digital conversion unit 102 and the PLL clock signal output from the storage unit 130. Outputs a counter control signal S ₈ (kT).

Specifically, the first storage unit 131 of the storage unit 130 generates and outputs a sinusoidal signal having the same frequency as the input wobble signal, and the multiplier 111 is the analog / digital converter. A signal obtained by multiplying the wobble signal output from 102 and the sine wave signal output from the first storage unit 131 is output.

The first delay unit 112 delays and outputs the signal output from the multiplier 111 by a time corresponding to a multiple of a predetermined clock period.

The second delay unit 115 delays the input signal by one clock period 1T and outputs the delayed signal.

The first adder 114 sums and outputs the output signal of the multiplier 111 and the output signal of the second delay unit 115.

The subtractor 113 subtracts the output signal of the first delay unit 112 from the signal output from the first adder 114 and outputs the output signal to the second delay unit 115.

The divider 118 divides the signal output from the second delay unit 115 into a constant value C ₁ set by the first constant setting unit 116 and outputs the divided signal.

The second adder 119 outputs a counter control signal by adding a predetermined constant value C ₂ set by the second constant setting unit 117 to the signal output from the divider 118.

The first counter 122 controls the clock signal from the oscillator 123 to control the frequency of the PLL clock signal. As described later, the first counter 122 controls a clock signal from the oscillator 123 to output a signal whose magnitude and frequency are controlled depending on the value of the counter control signal output from the calculator 110. .

The comparator 121 compares the output signal of the second adder 119 with the output signal of the first counter 122 to control the first counter 122 and the second counter 124. Outputs a counter hold signal that controls.

The second counter 124 is held by the count holder signal of the comparator 121 and outputs a signal for controlling the frequency of the PLL clock to the storage unit 130.

The first storage unit 131 generates a sine wave signal having the same period as that of the output signal of the second counter 124 and feeds it back to the multiplier 111.

The second storage unit 12 is controlled by a signal output from the second counter 124 and outputs a PLL signal which is phase-locked with the input wobble signal.

Hereinafter, the operation of the wobble PLL according to the present invention will be described in detail using specific formulas.

The wobble signal read from the optical pickup device (not shown) of the optical recording medium recording and reproducing apparatus is input to the band pass filter 101, and the band pass filter 101 filters the input wobble signal to signal-to-noise ratio (signal). -to-noise ratio The wobble signal output from the band pass filter 101 is converted into a digital signal by the analog / digital converter 102.

In this case, if the wobble signal output from the analog / digital converter 102 at any time kT is S (kT), S (kT) may be expressed by Equation 1 below.

In Equation 1, T denotes a period of a clock frequency output from the oscillator 123, ω denotes an angular frequency of an input wobble signal, and n (kT) denotes a noise component included in the wobble signal and a high frequency of the wobble signal. Upper harmonics.

On the other hand, if the output signal of the first storage unit 131 for generating a sinusoidal wave signal having an angular frequency equal to ω, the angular frequency of the input wobble signal, is S ₁ (kT), S ₁ (kT) is as follows. It can be approximately expressed by Equation 2 below.

이다. 다만, 상기 수학식 2에서 표현된 상기 S₁(kT)는 근사적인 표현이고, 그 구체적인 표현은 계속해서 설명되는 수식의 설명에 따라 후술하기로 한다. In Equation 2, φ represents the phase difference between the output signal and the input wobble signal of the first storage unit 131,

to be. However, S ₁ (kT) expressed in Equation 2 is an approximate expression, and the specific expression will be described later in accordance with the description of the equation which will continue to be described.

When the output signal of the multiplier 111 that multiplies and outputs S (kT) and S ₁ (kT) is S ₂ (kT), S ₂ (kT) is represented by the following equation (3).

The output signal S ₂ (kT) of the multiplier 111 represented by Equation 3 is input to the first delay unit 112 and is delayed for a predetermined time and output, and the output signal of the first delay unit 112 is output. S ₃ (kT) is expressed by the following equation (4).

이고, f는 상기 발진부(123)에서 출력되는 클럭 신호의 주파수를 의미한다.here,

F denotes the frequency of the clock signal output from the oscillator 123.

와 같이 표현된다. 감산부(113)에서는 상기 제 1가산부(114)의 출력신호 S₅(kT)로부터 상기 제 1지연부(112)의 출력신호 S₃(kT)를 감산하여 출력하며, 이때 상기 감산부(113)의 출력신호 S₆(kT)는

이다. 그러면, 상기 제 2지연부(115)에서 출력되는 신호 S₄(kT)는 다음의 수학식 5와 같이 표현될 수 있다.The second delay unit 115 delays the input signal by one cycle (1T) of the clock signal and outputs the signal. The signal output from the second delay unit 115 is referred to as S ₄ (kT). The S ₄ (kT) signal is input to the first adder 114 and is added to the output signal S ₂ (kT) of the multiplier 111, where the output signal of the first adder 114 is added to S _5. (kT),

It is expressed as In the subtraction unit 113 and the first adder section outputs from the output signal S ₅ (kT) of 114 subtracts the output signal S ₃ (kT) of the first delay unit 112, wherein the subtraction unit ( 113 output signal S ₆ (kT)

to be. Then, the signal S ₄ (kT) output from the second delay unit 115 may be expressed by Equation 5 below.

Solving for S ₄ (kT) in Equation 5, Equation 6 below.

In Equation 6, S _4A (kT) and S _4B (kT) are represented by Equations 7,8, respectively.

4 is a diagram illustrating a phase difference φ between S (kT), an input wobble signal, and S ₁ (kT), a signal output from the first storage unit 131, that is, a value of S _4A (kT) according to a value of ωpT. A graph showing the change in.

As shown, the value of S _4A (kT) is the phase difference φ between the input wobble signal S (kT) and the sinusoidal signal S ₁ (kT) output from the first storage unit 131. The value changes with ωpT and is not affected by any time value kT. In particular, when the phase difference is π / 2, the value of S _4A (kT) becomes 0, which corresponds to the case where ideal synchronization is made.

Meanwhile, the value of S _4B (kT) represented by Equation 8 represents a synchronization error. The present invention can effectively remove the noise signal when the input wobble signal includes an asymmetric noise signal through the signal processing process represented by Equations 1 to 8.

For example, when the noise signal n (kT) is a harmonic form of cos (2ωkT), substituting n (kT) into Equation 8 gives S _4B (kT) Same as

In Equation 9, the value of S _4B (kT) is zero. This is because NT coincides with one period of the angular frequency ω of the input wobble signal. Therefore, the wobble PLL of the present invention is less susceptible to noise having an angular frequency component different from the angular frequency ω of the input wobble signal.

이다.The divider 118 divides the signal S ₄ (kT) output from the second delay unit 115 by the constant C ₁ set by the first constant setting unit 116. If the signal output from the divider 118 is S ₇ (kT),

to be.

이다.In addition, the second adder 119 outputs a counter control signal by adding a constant C ₂ set by the second constant setting unit 117 to S ₇ (kT). That is, if the counter control signal output from the second adder 119 is S ₈ (kT),

to be.

Figure 5 is the output signal S ₁₁ of the output signal S ₁₀ (kT), the second counter 124 in the output signal S ₉ (kT), the comparator 121 of the first counter 122 from the wobble PLL according to the present invention ( kT) and a timing diagram for illustrating the operation of the output signal S ₁ (kT) of the first storage unit 131.

The signal S ₉ (kT) output from the first counter 122 is a value of S ₉ ((k-1) T) which is a value before the period of S ₈ (kT) and S ₉ (kT). In accordance with the equation expressed by the following equation (10).

i) 인 경우,

i),

인 경우,ii)

If is

In the above Equation 10, the comparison of the value of S ₈ (kT) and the value of S ₉ ((k-1) T) is performed in the comparator 121. The comparator 121 compares S ₈ (kT) and S ₉ ((k-1) T) and outputs S ₁₀ (kT) represented by Equation 11 below.

i) 인 경우,

i),

인 경우,ii)

If is

The output signal S ₁₀ (kT) of the comparator 121 is input to the reset terminal of the first counter 122 to control the output of the first counter 122. That is, the comparator 121 resets the first counter 122 when the output value of the first counter 122 and the output value of the second adder 119 are the same. Outputs

As shown in FIG. 4, the first counter 122 outputs a signal S ₉ (kT) in the form of a saw-tooth, and as shown in Equation 10, S ₉ (kT). The size and the frequency of are dependent on the value of S ₈ (kT) output from the second adder 119. For example, the second larger the value of the adder S ₈ (kT) outputted from the (119), since the S ₉ (kT) is the increase in time to reach the S ₈ (kT) the S ₉ ( The magnitude of kT) increases and the period increases so that the frequency decreases.

Meanwhile, S ₁₁ (kT), which is an output signal of the second counter 124, is output according to Equation 12 below.

i) 인 경우,

i),

이고,

인 경우,ii)

ego,

If is

인 경우,iii)

If is

과 같이 표현된다. 또한, 본 발명에 따른 워블 PLL의 출력값인 PLL 클럭의 최대 각주파수는 상기 ω_max와 같으며, 상기 ω_max는 입력되는 워블 신호가 가질 수 있는 최대 주파수를 초과해야 한다. 상기 조건을 만족하는 양의 정수 M의 값을 얻기 위하여, 상기 ω_max에 관한 식을 M에 관하여 정리하면,

이다.In Equation 12, M means a positive integer. At this time, the maximum angular frequency ω _max of the output signal S ₁₁ (kT) of the second counter 124 is

It is expressed as In addition, the maximum angular frequency of the PLL clock, which is the output value of the wobble PLL according to the present invention, is equal to ω _max, and ω _max should exceed the maximum frequency that the input wobble signal may have. In order to obtain the value of the positive integer M that satisfies the above condition, the equation for ω _max is summarized with respect to M,

to be.

Meanwhile, the counter hold signal S ₁₀ (kT) for holding the output of the comparator 121 is input to the clock disable terminal of the second counter 124. The counter hold signal S ₁₀ (kT) of the comparator 121 slows the frequency of the output signal S ₁₁ (kT) of the second counter. That is, when the value of S ₁₀ (kT) is 1, the output of S ₁₁ (kT) is as shown in the illustrated sections a, b, and c (freezing section, hereinafter referred to as 'freezing section'). Since the value of S ₁₀ ((k-1) T), which is a value before the clock period, is maintained, the angular frequency of S ₁₁ (kT) becomes small. However, the freezing section (a, b, c) is not large enough to be recognized as shown, in Figure 4 is an enlarged representation to explain the freezing section (a, b, c).

Since the value of S ₁₀ (kT) for reducing the angular frequency of S ₁₁ (kT) is determined according to the output S ₈ (kT) of the second adder 119, the angle of S ₁₁ (kT) as a result. The frequency depends on the output S ₈ (kT) of the second adder 119. That is, as the value of the output S ₈ (kT) of the second adder 119 increases, the angular frequency of the output signal S ₁₁ (kT) of the second counter 124 becomes smaller, and the second adder As the value of the output S ₈ (kT) of 119 decreases, the angular frequency of the output signal S ₁₁ (kT) of the second counter 124 increases.

The first storage unit 131 includes N-M pieces of information about one period of one sinusoidal signal. N-M pieces of information included in the first storage unit 131 may be expressed by Equation 13 below.

In Equation 13, the value of l represents an integer value from 1 to NM. As shown in FIG. 5, the output S ₁ (kT) of the first storage unit 131 is determined according to the angular frequency and phase of the output S ₁₁ (kT) of the second storage unit 115. That is, as shown, the period of the S ₁₁ (kT) and the period of S ₁ (kT) coincide, and S ₁ (kT) in the freezing section (a, b, c) of the S ₁₁ (kT) Freezing section (d, e, f) will be shown. Therefore, instead of an approximate representation of S ₁ (kT) shown in Equation 1, the exact equation of S ₁ (kT) including the freezing section (d, e, f) is given by Equation 14 below.

In addition, the exact equation of the PLL clock frequency in consideration of the freezing period (d, e, f) is as shown in the following equation (15).

에서, ω_max의 값을 상기 수학식 15에 대입하여 정리하면, 다음의 수학식 16과 같다.remind

In Equation 15, the value of ω _max is substituted into Equation 15, where Equation 16 is given.

인 경우,

이 되는 것을 확인할 수 있다. 결과적으로, 상기 제 2상수 설정부(117)에서 설정되는 상수 C₂의 값은 워블 PLL의 초기 조건을 만족하기 위하여

이 되도록 설정되어야 한다.In Equation 16

If is

It can be confirmed that. As a result, the value of the constant C ₂ set by the second constant setting unit 117 may satisfy the initial condition of the wobble PLL.

Should be set to

On the other hand, in order to obtain the minimum possible frequency change of the output signal S ₁₁ (kT) of the second counter 124, the derivative of ω _PLL (kT) of Equation 16 by S ₈ (kT) is expressed by Equation 17 below. Same as

은 대략

이 된다.Assuming that M = 1 and NM ≒ N in Equation 17, the minimum frequency change

Is approximately

Becomes

이고, 가능한 최소 주파수 변화는

이다.In the wobble PLL according to the present invention, if the digit capacitor of the second counter 124 is equal to the digit capacitor of the digital controlled oscillator 24 mentioned in the prior art, the frequency of the digital controlled oscillator 24 Is

And the minimum possible frequency change is

to be.

Therefore, the minimum frequency change value in the wobble PLL according to the present invention is about 1 / N times the minimum frequency change value according to the prior art. This means that the minimum frequency step of the PLL clock output from the wobble PLL according to the present invention is N times smaller than in the prior art. As a result, in the wobble PLL according to the present invention, the frequency and phase changes of the output PLL clock are reduced by N times as compared with the related art.

Further, the phase difference ωpT between the output signal S ₁ (kT) and the input wobble signal of the first storage unit 131 has a value of approximately π / 2 during the stabilization operation of the wobble PLL circuit. However, sometimes it may occur that various phase differences are required between the input wobble signal and the output PLL clock signal.

Therefore, preferably, a function stored in the second storage unit 132 for generating the PLL clock signal to have an arbitrary phase difference from the input wobble signal can be appropriately selected.

(l은 1 부터 N-M까지의 정수)와 같이 한 정현파 신호에 대한 N-M개의 정보를 저장하도록 할 수 있다. 또한, 입력 워블 신호 주파수의 2배를 갖는 PLL 클럭을 발생하기 위해서 상기 제 2저장부(132)는

형태의 함수를 선택할 수 있다. 상기한 실시예 이외에도 상기 제 2저장부(132)에 적절한 함수를 선택 저장함으로써 비정현파 신호를 발생시킬 수도 있다.For example, the second storage unit 132 may output the PLL clock having the same phase as the input wobble signal.

(l is an integer from 1 to NM) can store NM information about one sinusoidal signal. In addition, in order to generate a PLL clock having twice the frequency of the input wobble signal, the second storage unit 132

You can choose the type of function. In addition to the above embodiments, a non-sinusoidal signal may be generated by selecting and storing an appropriate function in the second storage unit 132.

According to the present invention, data recording and reproducing on the optical recording medium can be performed more correctly by generating a PLL clock signal which reduces the phase difference with the wobble signal on the optical recording medium.

Claims (4)

A first storage unit outputting a sine wave signal having the same frequency as the wobble signal read out from the optical recording medium; A multiplier for multiplying the wobble signal read out from the optical recording medium and a sine wave signal output from the first storage unit, a first delay unit for delaying and outputting the signal output from the multiplier, and an input signal by one clock period Subtracts the output signal of the first delay unit from the second delay unit for delaying output, the first adder for adding the output signal of the multiplier and the output signal of the second delay unit, and the output signal of the first adder; A subtractor for outputting to the second delay unit, a divider for dividing a signal output from the second delay unit into a predetermined constant value, and a second adder for adding and outputting a predetermined constant value to a signal output from the divider; And a counter control signal by performing an operation using the read wobble signal and a sine wave signal output from the first storage unit. Power unit for; A counter unit for outputting a signal for controlling the frequency of the PLL clock signal by the counter control signal output from the calculating unit; And And a second storage unit configured to output a PLL clock signal phase-locked with the wobble signal according to the frequency control signal output from the counter unit. delete The method of claim 1, wherein the counter unit, A first counter outputting a signal whose magnitude and frequency are controlled in dependence on a counter control signal output from the calculation unit; A comparator for comparing a counter control signal with an output signal of the first counter and outputting a counter hold signal; And And a second counter held by the counter hold signal of the comparator and outputting a signal for controlling the frequency of the PLL clock. delete

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