JP4067530B2 - PLL circuit and disk reproducing apparatus - Google Patents

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit and a disk reproducing apparatus, and is particularly suitable for use in a digital PLL circuit and a disk reproducing apparatus incorporating the same.

  Conventionally, an analog PLL circuit has been used as a PLL circuit of a disk reproducing apparatus. However, an analog PLL circuit is susceptible to noise and has a drawback of being vulnerable to environmental changes such as temperature changes. On the other hand, the digital PLL circuit is not easily affected by noise, and the characteristics are hardly affected by environmental changes such as temperature changes. Further, it has an advantage that it is easy to achieve high integration and is advantageous when mounted on an LSI.

  However, the digital PLL circuit has a drawback that the pull-in frequency range is narrow and the pull-in speed is slow compared to the analog method. This problem becomes prominent especially when the disk rotation state is unstable, such as when the disk is started or immediately after a jump of the playback position, and may contribute to the drive performance.

On the other hand, in the invention described in Patent Document 1 below, the above-described problem is solved by using an analog PLL circuit and a digital PLL circuit together. In the present invention, the PLL is first pulled in by an analog PLL circuit, and then the PLL is performed by using a digital PLL circuit. As a result, the frequency lock range is expanded and the pull-in speed is increased.
Japanese Patent No. 3350349

  However, according to such a conventional technique, since two circuit configurations of an analog PLL circuit and a digital PLL circuit are required, the circuit configuration becomes complicated and the circuit scale increases.

  It is an object of the present invention to provide a PLL circuit and a disk reproducing apparatus that can solve such problems and can easily expand the pulling range and increase the pulling speed with a simple configuration.

  In view of the above problems, the present invention has the following features.

  According to a first aspect of the present invention, in a PLL circuit that compensates a phase difference of a data acquisition position with respect to a reproduction signal, a phase difference detection unit that detects a phase difference of the data acquisition position with respect to a reproduction signal, and the phase difference detection unit A reading position changing unit that changes a cycle of the data acquisition position based on the detected phase difference, a binarized data generating unit that generates binarized data from the reproduction signal, and the binarized data generating unit Depending on whether the signal pattern acquired based on the binarized data generated by is included in a frequency range in which a predetermined frequency width is given to a single frequency for a certain period or longer, the reproduced signal has a single frequency. A section detection unit that detects whether the signal pattern is a continuous section, and a signal that detects the signal pattern from the data string of the binarized data generated by the binarized data generation unit A turn detection unit, a frequency distribution detection unit that detects a frequency distribution of a signal pattern detected by the signal pattern detection unit based on a reproduction signal of a section detected by the section detection unit, and a frequency distribution detection unit It is grasped as having a period correction part which corrects the amount of change of the period in the reading position change part based on the detected distribution state.

  In the first aspect, the period correction unit generates a correction amount for correcting the period change amount in the reading position changing unit based on the frequency distribution, and the reading position changing unit is configured to detect the phase difference. The period of the data acquisition position is changed based on the correction amount supplied from the period correction unit to the phase difference detected by the unit.

  More specifically, the period correction unit generates a correction amount for shortening the period when the frequency distribution detected by the frequency distribution detection unit is biased to a higher frequency side than the single frequency, and the frequency distribution detection When the frequency distribution detected by the unit is biased to the lower frequency side than the single frequency, a correction amount that lengthens the period can be generated.

  According to a second aspect of the present invention, in a PLL circuit that compensates a phase difference of a PLL clock with respect to a reproduction signal, a phase difference detection unit that detects the phase difference of the PLL clock with respect to the reproduction signal, and the phase difference detection unit detects the phase difference. A binarized data for generating binarized data based on a clock signal changing unit that changes the frequency of the clock based on the phase difference and a sample signal obtained when the reproduction signal is sampled by the PLL clock. The signal pattern acquired based on the binarized data generated by the generating unit and the binarized data generating unit is included in a frequency range in which a predetermined frequency width is given to a single frequency for a certain period or more. Depending on whether or not the reproduced signal is a section in which a signal pattern of a single frequency is continuous, and the binarized data generator A signal pattern detection unit for detecting a signal pattern based on the generated data string of the binarized data, and a signal pattern detection unit detected based on a reproduction signal in the section detected by the section detection unit A frequency distribution detection unit that detects a frequency distribution of a signal pattern; and a frequency correction unit that corrects a frequency change amount in the clock frequency change unit based on the frequency distribution detected by the frequency distribution detection unit. Be grasped.

  In the second aspect, the frequency correction unit generates a correction amount for correcting a frequency change amount in the clock frequency changing unit based on the frequency distribution, and the clock frequency changing unit is configured to detect the phase difference. The frequency of the PLL clock is changed based on the phase difference detected by the unit and the correction amount supplied from the frequency correction unit.

  More specifically, the frequency correction unit generates a correction amount for shifting the PLL clock to a high frequency side when the frequency distribution detected by the frequency distribution detection unit is biased to a higher frequency side than the single frequency, When the frequency distribution detected by the frequency distribution detector is biased to the lower frequency side than the single frequency, a correction amount for shifting the PLL clock to the lower frequency side can be generated.

  According to a third aspect of the present invention, in a PLL circuit that compensates for a phase difference of a data interpolation position with respect to a reproduction signal, a phase difference detection unit that detects a phase difference of the data interpolation position with respect to the reproduction signal, and the phase difference detection unit An interpolation position changing unit that changes a cycle of the data interpolation position based on the detected phase difference, and a binary value at the interpolation position by performing interpolation processing on sampling data when the reproduction signal is sampled by an asynchronous clock A binarized data generating unit that generates binarized data, and a signal pattern acquired based on the binarized data generated by the binarized data generating unit gives a predetermined frequency width to a single frequency. A section detection unit for detecting whether the reproduction signal is a section in which a signal pattern of a single frequency is continuous depending on whether the frequency range is included for a certain period or more. A signal pattern detection unit that detects a signal pattern based on a data string of binarized data generated by the binarized data generation unit, and the reproduction signal in the section detected by the section detection unit A frequency distribution detection unit that detects a frequency distribution of the signal pattern detected by the signal pattern detection unit, and a period change amount in the interpolation position changing unit is corrected based on the frequency distribution detected by the frequency distribution detection unit. It is grasped as having a period correction unit.

  In the third aspect, the cycle correction unit generates a correction amount for correcting the cycle change amount in the interpolation position changing unit based on the frequency distribution, and the interpolation position changing unit is configured to detect the phase difference. The frequency of the clock is changed based on the phase difference detected by the unit and the correction amount supplied from the period correction unit.

  More specifically, the period correction unit generates a correction amount for shortening the period of the interpolation position when the frequency distribution detected by the frequency distribution detection unit is biased to a higher frequency side than the single frequency, and the frequency When the frequency distribution detected by the distribution detection unit is biased to the lower frequency side than the single frequency, a correction amount that lengthens the period of the interpolation position can be generated.

  A fourth aspect of the present invention is grasped as a disk reproducing device including the PLL circuit according to any one of claims 1 to 9.

  In the fourth aspect, it may be configured to further include means for correcting the change amount when the rotational state of the disk is not in a steady state.

  In addition, the section detection unit detects a section in which a signal having a length of nT (n: natural number, T: unit mark length) is continuously recorded on the disc for a certain period of time (n ± m) T (m: It can be configured to detect whether a signal pattern within a range of (natural number) is continuously detected for a certain period or longer.

  According to the present invention, in addition to the phase difference, the PLL is drawn in consideration of the correction amount based on the frequency distribution of the signal pattern generated from the binarized data. In comparison, the pull-in frequency range of the PLL can be expanded, and the pull-in speed can be increased.

  Here, the amount of correction depends on how the frequency distribution of the signal pattern generated from the binarized data deviates from the original frequency (single frequency) in the interval where the signal pattern of single frequency is continuous. Therefore, for example, the binarized data generation circuit provided in the reproduction circuit system can be shared as it is for the generation of the correction amount. The correction amount can be generated easily and smoothly without any addition.

  Thus, according to the present invention, it is possible to easily and smoothly expand the pull-in range of the PLL circuit and increase the pull-in speed with a simple configuration.

  The effects and features of the present invention will become more apparent from the following description of embodiments.

  In the following embodiment, the disc reproducing apparatus according to the fourth aspect of the present invention is realized as an optical disc apparatus. Moreover, the embodiment shown in FIGS. 1 to 11 is shown as the embodiment of the second aspect, and the embodiment shown in FIGS. 12 to 14 is shown as the third aspect of the present invention. Note that the first aspect encompasses the second aspect and the first aspect.

  Further, the “frequency distribution of signal pattern” in the present invention is shown as a distribution of appearance frequencies of signal patterns (n−1) T, nT, and (n + 1) T in the following embodiments. Here, since the time length of the signal pattern has a relationship of (n−1) T <nT <(n + 1) T, the frequency has a relationship of (n−1) T> nT> (n + 1) T. Therefore, the frequency distribution of the signal pattern is more concentrated on the high frequency side as the appearance frequency of the signal pattern (n−1) T is higher, and the frequency distribution of the signal pattern is on the lower frequency side as the appearance frequency of the signal pattern (n + 1) T is higher. It will be overweight.

However, the following embodiment is merely an example for carrying out the present invention, and the meaning of the terms of the present invention or each component is limited to those described in the following embodiment. is not.

  FIG. 1 shows a configuration of an optical disc apparatus according to the embodiment. In the present embodiment, the present invention is applied to an optical disc apparatus that performs recording / reproduction with respect to a high density optical disc such as a DVD (Digital Versatile Disc) or a next generation DVD. In FIG. 1, only the reproduction system is shown, and the recording system is not shown. Also, servo systems such as a focus servo circuit and a tracking servo circuit are not shown.

  As shown in FIG. 1, the optical disk apparatus includes an optical pickup 20, an amplifier circuit 30, an analog BPF (Band Pass Filter) 40, an ADC (Analog-Digital Converter) 50, a digital PLL 60, a digital equalizer 70, 2 A value conversion circuit 80 and a frequency detection correction circuit 90 are provided.

  The optical pickup 20 records / reproduces data by irradiating the disk 10 with laser light. A spiral track is formed on the disk 10, and VFO sections are arranged on the track at regular intervals. In such a VFO section, marks and spaces having the same time length are continuously arranged. That is, when the unit time length of the mark and space is T, the mark and space having a length of nT (n: a predetermined natural number) are continuously arranged.

  The amplifier circuit 30 amplifies the reproduction RF signal supplied from the optical pickup 30 and outputs the amplified signal to the analog BPF 40. The analog BPF 40 removes a noise component of the reproduction RF signal and amplifies a predetermined frequency component and outputs the amplified frequency component to the ADC 50. The ADC 50 samples the reproduction RF signal at a sampling timing corresponding to the PLL clock (sampling clock) supplied from the digital PLL 60, converts the sample value into a digital signal, and outputs the digital signal to the digital PLL 60.

  The digital PLL 60 detects the phase difference between the sampling timing based on the PLL clock and the appropriate sampling timing relative to the reproduction RF signal based on the digital signal input from the ADC 50, and adjusts the frequency of the PLL clock so as to eliminate this phase difference.

  The digital equalizer 70 equalizes the waveform of the digital signal supplied from the ADC 50 and outputs it to the binarization circuit 80. The binarization circuit 80 decodes the digital signal supplied from the digital equalizer 70 to generate and output binary data of 1 and 0.

  The frequency detection correction circuit 90 generates a correction amount for the phase difference based on the binarized data supplied from the binarization circuit 80 and outputs the correction amount to the digital PLL 60. Such a correction amount is added to the phase difference by the digital PLL 60.

  FIG. 2 shows the configuration of the digital PLL 60.

  As illustrated, the digital PLL 60 includes a digital phase comparator 601, a loop filter 602, an adder 603, a DAC (Digital-Analog Converter) 604, and a VCO (Voltage Controlled Oscillator) 605.

  The digital phase comparator 601 determines the edge of the reproduced signal waveform based on the digital signal supplied from the ADC 50 and detects the phase difference between this edge and the PLL clock. Then, a digital signal (phase difference signal) corresponding to the phase difference is output to the loop filter 602. The loop filter 602 cuts off the high-frequency component of the phase difference signal and converts it to direct current, and outputs this to the adder 603.

  The adder 603 adds the phase difference signal supplied from the loop filter 602 and the correction signal (digital signal corresponding to the correction amount) supplied from the frequency detection correction circuit 905 and outputs the result to the DAC 604. The DAC 604 converts the digital signal supplied from the adder 603 into an analog signal (voltage value) and outputs it to the VCO 605. The VCO 605 changes the oscillation frequency of the PLL clock using the analog signal (voltage value) supplied from the DAC 604 as a control signal.

  FIG. 3 shows a timing chart when the optical pickup 20 is scanning the VFO section on the disk 10. In the figure, the time length (nT) of the mark and space in the VFO section is 3T.

  As shown in the drawing, since inter-waveform interference occurs in a reproduction signal in an optical disc of high-density recording, the reproduction signal waveform at the time of scanning a VFO section is a waveform in which a mark and a space interfere with each other as shown in FIG. . At this time, as shown in FIG. 6C, if the PLL clock has an appropriate phase (appropriate frequency), the equalized signal level of the reproduced RF signal sampled according to the PLL clock is shown in FIG. It will be a thing. When such an equalized signal level is decoded by the above-described binarization circuit 80, binary data in which three 1s and 0s are continuous is obtained as shown in FIG. Therefore, a signal pattern having a frequency corresponding to the time length of 3T is detected from the binarized data.

  FIG. 4 shows a timing chart when the PLL clock has a higher frequency than the appropriate frequency. In this case, the equalized signal level of the reproduced RF signal sampled according to the PLL clock is as shown in FIG. When such an equalized signal level is decoded by the above-described binarization circuit 80, binary data in which four 1s and zeros are consecutive is obtained as shown in FIG. Therefore, a signal pattern having a frequency corresponding to the time length of 4T is detected from the binarized data.

  FIG. 5 shows a timing chart when the PLL clock has a frequency lower than the appropriate frequency. In this case, the equalized signal level of the reproduced RF signal sampled according to the PLL clock is as shown in FIG. When such an equalized signal level is decoded by the above-described binarization circuit 80, binary data in which two 1s and zeros are continuous is obtained as shown in FIG. Therefore, a signal pattern having a frequency corresponding to the time length of 2T is detected from the binarized data.

  FIG. 6 shows the tendency of the appearance frequency of the signal patterns (n−1) T, nT, and (n + 1) T when the VFO section (time length of mark and space: nT) is scanned.

  When the PLL clock has an appropriate frequency (see FIG. 3A), as described with reference to FIG. 3, the appearance frequency (detection) of the signal pattern having the same time length as the time length nT of the mark and space in the VFO section Frequency) increases peakly. At this time, since the phase of the PLL clock fluctuates from the appropriate phase, the signal patterns of the time lengths (n−1) T and (n + 1) T before and after are also detected simultaneously.

  On the other hand, when the PLL clock is faster than the appropriate frequency (see FIG. 4B), as described with reference to FIG. 4, the distribution of the appearance frequency is a signal pattern of time length (n + 1) T. The frequency of occurrence (detection frequency) is more biased. When the PLL clock is slower than the appropriate frequency (see FIG. 5C), as described with reference to FIG. 5 above, the appearance frequency distribution is a signal pattern of time length (n−1) T. The frequency of occurrence (detection frequency) is more biased.

  From the tendency of the appearance frequency of these signal patterns, when the distribution of the appearance frequency is biased toward (n + 1) T, it can be determined that the PLL clock is faster than the appropriate frequency, and the appearance frequency distribution is (n− 1) If it is biased toward T, it can be determined that the PLL clock is slower than the appropriate frequency. The frequency detection / correction circuit 90 described above detects the degree of unevenness of the distribution and performs correction so that the PLL clock approaches the appropriate frequency according to the detection result.

  FIG. 7 shows a configuration example of the frequency detection correction circuit 90.

  As shown in the figure, the frequency detection correction circuit 90 includes a signal pattern detector 901, a frequency distribution measurement unit 902, a magnitude relationship detection unit 903, a frequency correction amount determination unit 904, a frequency correction output control unit 905, and an OR circuit. 906 and a signal pattern detection counter 907.

  The signal pattern detector 901 detects the signal pattern (n−1) T, nT, (n + 1) T from the binarized data supplied from the binarization circuit 80 and outputs the detection result to the frequency distribution measuring unit 902. To do. That is, when the signal pattern (n−1) T is detected, a detection signal is output to the (n−1) T counter 902a of the frequency distribution measuring unit 902, and when the signal pattern nT, (n + 1) T is detected. The detection signals are output to the nT counter 902b and the (n + 1) T counter 902c, respectively. When a signal pattern other than the signal patterns (n−1) T, nT, and (n + 1) T is detected, a signal for resetting the count value of each counter in the frequency distribution measuring unit 902 and the signal pattern detection counter 907 is used. Output.

  The frequency distribution measuring unit 902 includes an (n−1) T counter 902a, an nT counter 902b, and an (n + 1) T counter 902c. Based on the count values of these counters, the frequency distribution of the signal pattern described above is distributed. Measure.

  Based on the count values of the (n−1) T counter 902a, the nT counter 902b, and the (n + 1) T counter 902c, the magnitude relation detection unit 903 detects the degree of weight distribution of the appearance frequency of the signal pattern described above, The detection result is output to the frequency correction amount determination unit 904.

  The frequency correction amount determination unit 904 determines a correction amount fa for correcting the frequency of the PLL clock based on the detection result supplied from the magnitude relationship detection unit 903, and outputs this to the frequency correction output control unit 905. To do. Specifically, when the detection result supplied from the magnitude relationship detection unit 903 indicates that the distribution of appearance frequencies is biased toward (n + 1) T, the PLL clock is used as the correction amount fa. When the correction amount −Δf for decreasing the frequency of Δn is determined, and the distribution of appearance frequencies is biased toward (n−1) T, the frequency of the PLL clock is increased by Δf as the correction amount fa. The correction amount + Δf to be determined is determined. Here, Δf may be a value corresponding to the magnitude of the deviation, or may be set to a uniform value regardless of the magnitude of the deviation.

  The frequency correction output control unit 905 outputs the correction amount fa supplied from the frequency correction amount determination unit 904 to the adder 603 of the digital PLL 60 according to the detection signal from the signal pattern detection counter 907.

  The signal pattern detection counter 907 is reset by a reset signal from the signal pattern detector 901 and also by the detection signals of the signal patterns (n−1) T, nT, and (n + 1) T input via the OR circuit 906. Counts up by one. When the count value Kp is equal to or greater than a preset threshold value K0, the detection signal is output to the frequency correction output control unit 905, assuming that the VFO section is being scanned. That is, the signal pattern detection counter 907 determines whether the pickup is scanning the VFO section based on the continuity of the signal patterns (n−1) T, nT, and (n + 1) T. When the signal patterns (n−1) T, nT, and (n + 1) T continue for a threshold value K0 times or more, a detection signal is output assuming that the pickup is scanning the VFO section.

  FIG. 8 shows an operation flowchart of the frequency detection correction circuit 90.

  When the correction operation is started, each counter in the frequency distribution measuring unit 902 and the signal pattern detection counter 907 are reset (S101), and then each counter starts counting up (S102). Thereafter, when the count value Kp of the signal pattern detection counter 907 reaches the threshold value K0 (S103: YES), the frequency correction based on the count values of the (n−1) T counter 902a, the nT counter 902b, and the (n + 1) T counter 902c. The amount fa is output from the frequency correction output control unit 905 to the adder 603 of the digital PLL 60 (S104).

  On the other hand, if the count value Kp of the signal pattern detection counter 907 does not reach the threshold value K0, each counter counts up until a signal pattern other than the signal patterns (n−1) T, nT, and (n + 1) T is detected. It is performed (S105: NO → S102). When a signal pattern other than the signal patterns (n−1) T, nT, and (n + 1) T is detected (S105: YES), a reset signal is output from the signal pattern detector 901, and the frequency distribution measurement unit 902 And the signal pattern detection counter 907 are reset (S101). Thereafter, counting up of these counters is resumed (S102), and operations similar to the above are executed (S102 to S105).

  As described above, according to the present embodiment, the PLL clock frequency correction amount fa is added to the phase difference by the adder 603 of the digital PLL 60, so even if the PLL clock frequency shift amount with respect to the appropriate frequency is relatively large. The PLL clock can be quickly pulled to an appropriate frequency by the pulling action by the correction amount fa. Therefore, it is possible to measure the expansion of the lock range and the speeding up of the pull-in operation.

  In addition, this invention is not limited to the said embodiment, A various change is possible for others.

  For example, in the above embodiment, as shown in FIG. 7, the frequency of correction of fa frequency of the PLL clock is determined by comparing the appearance frequencies of the signal patterns (n−1) T, nT, and (n + 1) T. However, as shown in FIG. 9, the correction frequency fa of the frequency of the PLL clock may be determined by comparing the appearance frequencies of the signal patterns (n−1) T and (n + 1) T. Also in this case, since the deviation of the distribution of the appearance frequency of the signal pattern can be detected, the correction amount fa according to the deviation of the distribution can be determined as described above.

  Further, the frequency of appearance of the signal patterns (n−1) T, nT, and (n + 1) T was compared, but the signal patterns (n−2) T, (n−1) T, nT, and (n + 1) were compared. The comparison range of signal patterns may be further expanded, for example, by comparing the appearance frequencies of T and (n + 2) T. In this case, the signal pattern detector 901 detects each signal pattern included in the comparison range and outputs the detection result to the frequency distribution measurement unit 902. The frequency distribution measurement unit 902 is provided with a counter for counting the appearance frequency of each signal pattern according to each signal pattern. Furthermore, the magnitude relationship detection unit 903 compares the count values of the counters provided in the frequency distribution measurement unit 902. Further, the frequency correction amount determination unit 904 determines the frequency clock correction amount fa based on the comparison result.

  However, there is a demerit that if the comparison range is expanded in this way, the circuit scale increases accordingly. Also in this case, as shown in FIG. 9, the signal pattern nT may be excluded from the comparison target. Alternatively, the correction amount fa may be determined by weighting the appearance ratio of each signal pattern and then comparing the magnitudes.

  In the above embodiment, the correction amount fa is directly input from the frequency correction output control unit 905 to the adder 603. However, in order to avoid a sudden change in frequency, the correction amount fa is smoothed by a filter ( This may be input to the adder 603 after integration. In this way, although the pull-in speed of the PLL is slow, the PLL runaway due to a sudden frequency change can be prevented, and the pull-in operation can be stabilized.

  Further, as shown in FIG. 10, a switch 911 is arranged between the frequency correction output control unit 905 and the adder 603 so that the disk rotation state is not in a steady state such as when the disk is started or when the pickup is accessed, and the PLL pull-in operation is performed. The correction amount fa may be applied to the adder 603 only when it is difficult to perform the smoothing. In this way, the influence of the correction amount fa after the PLL lock can be avoided. In FIG. 10, in addition to the switch 911, a filter 910 for smoothing (integrating) the correction amount fa is arranged between the frequency correction output control unit 905 and the adder 603.

  In the above embodiment, as shown in FIG. 2, the digital phase comparator 601 and the loop filter 602 are digital, and the others are analog. However, as shown in FIG. 11, the loop filter 602 is analog. You may comprise as a system.

  Incidentally, in the above embodiment, the PLL clock is used as the sampling clock of the ADC 50. However, as shown in FIG. 12, an asynchronous clock is used as the sampling clock of the ADC 50, and the signal sampled thereby is subjected to data interpolation. The present invention can also be applied to a type of PLL circuit that interpolates in the circuit 621 and generates a read signal. In this case, referring to FIG. 13, a read signal at the data interpolation position (marked with ■ in the figure) is interpolated and generated based on the sample signal sampled with the asynchronous sampling clock (circled in the figure).

  Referring to FIG. 12, the data interpolation circuit 621 executes interpolation processing based on the sample signal from the ADC 50 as described above, and generates and outputs a read signal at the data interpolation position.

  The digital phase comparator 622 discriminates the edge of the reproduction signal waveform based on the read signal supplied from the data interpolation circuit 621, and between the normal read position set based on this edge and the data interpolation position. Detect phase difference. Then, a digital signal (phase difference signal) corresponding to the phase difference is output to the adder 623.

  The adder 623 adds the phase difference signal supplied from the digital phase comparator 622 and the correction signal (digital signal corresponding to the correction amount) supplied from the frequency detection correction circuit 90 and outputs the result to the loop filter 624. The loop filter 624 blocks a high-frequency component of the signal obtained by adding the correction signal and the phase difference signal, converts the signal into a direct current, and outputs this to the interpolation phase information generator 625.

  The interpolation phase information generator 625 outputs information for changing the cycle of the data interpolation position in accordance with the signal supplied from the loop filter 624 to the data correction circuit 621. Based on this signal, the data interpolation circuit 621 sets a data interpolation position, and calculates a read signal at the data interpolation position based on the sample signal from the ADC 50.

  In this embodiment, the frequency detection correction circuit 90 determines whether the cycle of the data interpolation position is faster or slower than the appropriate cycle, and accordingly, the correction amount fa for bringing the cycle of the data interpolation position closer to the appropriate cycle is set. Is set. That is, in FIG. 7, (n-1) T counter 902a, nT counter 902b, and (n + 1) T counter 902c count the appearance ratios of signal patterns (n-1) T, nT, (n + 1) T. When the appearance ratio is biased toward the signal pattern (n−1) T, the frequency correction amount determination unit 904 sets a correction amount + Δf that advances (shortens) the cycle of the data interpolation position. In addition, when the appearance ratio of each signal pattern is biased toward the signal pattern (n + 1) T, the correction amount −Δf that delays (longens) the cycle of the data interpolation position by the frequency correction amount determination unit 904 is obtained. Is set.

  Also in this embodiment, as described above, the correction amount fa of the interpolation position period is added to the phase difference by the adder 612 of the digital PLL 60, so even if the amount of deviation of the interpolation position period from the appropriate period is relatively large, The phase of the interpolation position can be quickly pulled to the appropriate phase by the pulling action by the correction amount fa. Therefore, it is possible to measure the expansion of the lock range and the speeding up of the pull-in operation.

  In the configuration example shown in FIG. 12, the correction amount is added to the phase difference and then input to the loop filter 624. However, after the phase difference is converted to direct current by the loop filter 624 as shown in FIG. It is also possible to add correction amounts.

  Further, in the configuration example of FIG. 12, the switch 911 and the filter 910 are arranged. However, as described above, these may be omitted as appropriate. Furthermore, in the above-described embodiment, the example in which the present invention is applied to the optical disk device has been described. However, the present invention can also be applied to other drive devices such as a magneto-optical disk device and a magnetic disk device.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims.

The figure which shows the structure of the optical disk apparatus which concerns on embodiment The figure which shows the structure of the digital PLL which concerns on embodiment The figure which shows the timing chart (at the time of a clock normal) which concerns on embodiment The figure which shows the timing chart (clock is early) which concerns on embodiment The figure which shows the timing chart (clock is slow) which concerns on embodiment The figure which shows the distribution tendency of the signal pattern appearance frequency which concerns on embodiment The figure which shows the structure of the frequency detection correction circuit which concerns on embodiment The figure which shows the operation | movement flow of the frequency detection correction circuit which concerns on embodiment The figure which shows the example of a change of the frequency detection correction circuit which concerns on embodiment The figure which shows the example of a change of the frequency detection correction circuit which concerns on embodiment The figure which shows the example of a change of the digital PLL which concerns on embodiment The figure which shows the example of a change of the digital PLL which concerns on embodiment The figure explaining operation | movement of the digital PLL which concerns on embodiment The figure which shows the example of a change of the digital PLL which concerns on embodiment

Explanation of symbols

60 Digital PLL
80 Binarization circuit 90 Frequency detection correction circuit 601 and 611 Digital phase comparator 601 and 614 Loop filter 603 and 612 Adder 604 and 613 DAC
605, 615 VCO
612 Data interpolation circuit 622 Digital phase comparator 623 Adder 624 Loop filter 625 Interpolation phase information generator 901 Signal pattern detector 902 Frequency distribution measurement unit 903 Size relationship detection unit 904 Frequency correction amount determination unit 905 Frequency correction output control unit 906 OR Circuit 907 signal pattern detection counter 910 filter 911 switch

Claims (12)

In the PLL circuit that compensates for the phase difference of the data acquisition position with respect to the reproduction signal,
A phase difference detection unit for detecting a phase difference of the data acquisition position with respect to a reproduction signal;
A reading position changing unit that changes the period of the data acquisition position based on the phase difference detected by the phase difference detecting unit;
A binarized data generating unit that generates binarized data from the reproduction signal;
Depending on whether the signal pattern acquired based on the binarized data generated by the binarized data generating unit is included in a frequency range given a predetermined frequency width for a single frequency for a certain period or more, A section detection unit for detecting whether the reproduction signal is a section in which a single frequency signal pattern is continuous ;
A signal pattern detection unit for detecting a signal pattern from a data string of binarized data generated by the binarized data generation unit;
A frequency distribution detection unit that detects a frequency distribution of the signal pattern detected by the signal pattern detection unit based on a reproduction signal of the interval detected by the interval detection unit;
A period correction unit that corrects a change amount of the period in the reading position change unit based on the distribution state detected by the frequency distribution detection unit;
A PLL circuit comprising: In claim 1,
The period correction unit generates a correction amount for correcting a period change amount in the reading position change unit based on the frequency distribution,
The reading position changing unit changes the period of the data acquisition position based on the correction amount supplied from the period correcting unit to the phase difference detected by the phase difference detecting unit.
A PLL circuit characterized by that. In claim 2,
The period correction unit generates a correction amount for shortening the period when the frequency distribution detected by the frequency distribution detection unit is biased to a higher frequency side than the single frequency, and is detected by the frequency distribution detection unit. Generating a correction amount that lengthens the period when the frequency distribution is biased to a lower frequency side than the single frequency,
A PLL circuit characterized by that. In a PLL circuit that compensates for a phase difference of a PLL clock with respect to a reproduction signal,
A phase difference detector for detecting a phase difference of the PLL clock with respect to a reproduction signal;
A clock frequency changing unit that changes the frequency of the clock based on the phase difference detected by the phase difference detecting unit;
A binarized data generating unit that generates binarized data based on a sample signal obtained by sampling the reproduction signal with the PLL clock;
Depending on whether the signal pattern acquired based on the binarized data generated by the binarized data generating unit is included in a frequency range given a predetermined frequency width for a single frequency for a certain period or more, A section detection unit for detecting whether the reproduction signal is a section in which a single frequency signal pattern is continuous ;
A signal pattern detection unit that detects a signal pattern based on the data string of the binarized data generated by the binarized data generation unit;
A frequency distribution detection unit that detects a frequency distribution of the signal pattern detected by the signal pattern detection unit based on a reproduction signal in the interval detected by the interval detection unit;
A frequency correction unit that corrects a frequency change amount in the clock frequency change unit based on the frequency distribution detected by the frequency distribution detection unit;
A PLL circuit comprising: In claim 4,
The frequency correction unit generates a correction amount for correcting a frequency change amount in the clock frequency change unit based on the frequency distribution,
The clock frequency changing unit changes the frequency of the PLL clock based on the phase difference detected by the phase difference detecting unit and the correction amount supplied from the frequency correcting unit.
A PLL circuit characterized by that. In claim 5,
The frequency correction unit generates a correction amount for shifting the PLL clock to a high frequency side when the frequency distribution detected by the frequency distribution detection unit is biased to a higher frequency side than the single frequency, and the frequency distribution detection Generating a correction amount for shifting the PLL clock to the low frequency side when the frequency distribution detected by the unit is biased to the lower frequency side than the single frequency;
A PLL circuit characterized by that. In the PLL circuit that compensates for the phase difference of the data interpolation position with respect to the reproduction signal,
A phase difference detection unit for detecting a phase difference of the data interpolation position with respect to a reproduction signal;
An interpolation position changing unit that changes a cycle of the data interpolation position based on the phase difference detected by the phase difference detecting unit;
A binarized data generating unit that performs sampling processing on sampling data when the reproduction signal is sampled with an asynchronous clock to generate binarized data at the interpolation position;
Depending on whether the signal pattern acquired based on the binarized data generated by the binarized data generating unit is included in a frequency range given a predetermined frequency width for a single frequency for a certain period or more, A section detection unit for detecting whether the reproduction signal is a section in which a single frequency signal pattern is continuous ;
A signal pattern detection unit that detects a signal pattern based on the data string of the binarized data generated by the binarized data generation unit;
A frequency distribution detection unit that detects a frequency distribution of the signal pattern detected by the signal pattern detection unit based on a reproduction signal in the interval detected by the interval detection unit;
A period correction unit that corrects a change amount of the period in the interpolation position change unit based on the frequency distribution detected by the frequency distribution detection unit;
A PLL circuit comprising: In claim 7,
The period correction unit generates a correction amount for correcting a period change amount in the interpolation position change unit based on the frequency distribution,
The interpolation position changing unit changes the frequency of the clock based on the phase difference detected by the phase difference detecting unit and the correction amount supplied from the period correcting unit,
A PLL circuit characterized by that. In claim 8,
The period correction unit generates a correction amount for shortening the period of the interpolation position when the frequency distribution detected by the frequency distribution detection unit is biased to a higher frequency side than the single frequency, and the frequency distribution detection unit Generating a correction amount that lengthens the period of the interpolation position when the frequency distribution detected by is biased to a lower frequency side than the single frequency,
A PLL circuit characterized by that. A disc reproducing apparatus comprising the PLL circuit according to claim 1. In claim 10,
Means for correcting the change amount when the rotational state of the disk is not in a steady state;
A disc player characterized by that. In claim 10 or 11,
The section detection unit detects a section in which a signal having a length of nT (n: natural number, T: unit mark length) is continuously recorded on the disc for a certain period of time (n ± m) T (m: natural number). ) To detect whether a signal pattern within the range of
A disc player characterized by that.

Images