CN115037430B - I, Q-path DAC synchronous design method - Google Patents

I, Q-path DAC synchronous design method Download PDF

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Publication number
CN115037430B
CN115037430B CN202210137718.XA CN202210137718A CN115037430B CN 115037430 B CN115037430 B CN 115037430B CN 202210137718 A CN202210137718 A CN 202210137718A CN 115037430 B CN115037430 B CN 115037430B
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dac
dacs
degrees
met
synchronous
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CN115037430A (en
Inventor
谷艳
陈雷
华璐
刘风华
王琰
刘亚鹏
行涛
谢应辉
王兆辉
乐立鹏
马城城
方新嘉
王伊卜
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses a I, Q-path DAC synchronous design method. In design, digital and analog conversion is needed to convert digital baseband signals with multiple levels into analog signals to be sent to an IQ vector modulator to form radio frequency signal transmission, IQ vector phase is needed to be guaranteed, two paths of DACs of I, Q are needed to work synchronously, but two independent MUXDACs are used in the paths I and Q, so that a way is needed to connect the two independent DACs, and whether synchronous work is achieved or not can be judged. The invention adopts the correlation characteristic of the output clocks of the two DACs and the data, compares the output clocks of the two DACs, judges whether the DAC works synchronously or not by using the 8-phase clock sampling of 2 times of the output clocks of the DACs, and can realize the processing of high-frequency data with lower frequency on design realization.

Description

I, Q-path DAC synchronous design method
Technical Field
The invention relates to a I, Q-path DAC synchronous design method which can be applied to the design of high-speed DAC interfaces of wireless, satellite and ground communication systems.
Background
In the data transmission design of the satellite communication system, digital and analog conversion is needed to convert digital baseband signals with multiple levels into analog signals to be sent to an IQ vector modulator to form radio frequency signals for transmission, IQ vector phase is needed to be ensured, two paths of DACs of I, Q are needed to work synchronously, but two independent MUXDACs are used in the paths of I and Q, a way is needed to connect the two independent DACs, and synchronous work can be realized through the method. If the working frequency is low, two DACs working independently can sample corresponding IQ data in the same clock period, but under the condition of high working rate, for example, when 1.5Gsps data is transmitted, the working frequency reaches 375MHz under the condition of DACMUX4, and the problem of IQ vector synchronization must be considered.
Disclosure of Invention
The invention solves the technical problems that: the I, Q-path DAC synchronous design method has the advantages that two independent DACs are connected by utilizing output clocks of the DACs, the DACs are enabled to synchronously work through clock comparison and judgment, the method is simple and easy to realize, meanwhile, 8-phase clock sampling with the frequency being 2 times of the output clock of the DACs is adopted, the high-frequency sampling requirement can be realized by using the frequency of 1/8, the time sequence difficulty in a circuit is reduced, the sampling precision is ensured, and the delay module adopts a feedback design method, so that the variation trend of delay under different voltages and different temperatures can be overcome while delay is regulated.
The specific solution of the invention is as follows: a I, Q-path DAC synchronous design method comprises the following steps:
(1) Setting the working modes of two DAC which work independently to be the same, and comparing the output clocks of the two DAC;
(2) Sampling the comparison result obtained in the step (1);
(3) And judging whether the DAC works synchronously or not according to the sampling result, if so, maintaining the working state, if not, generating a reset indication signal and counting, and if the counting reaches a preset value or cannot be synchronized, adjusting the delay module.
A two-way DAC of I, Q is required to operate synchronously and two independent MUXDACs are used for the I-and Q-ways.
The output clocks of the two DACs are compared using comparator CLKXOR 2.
The output clocks of the two independently operated DACs are equally delayed to the input of the comparator CLKXOR2, including off-chip and on-chip delays, and the shorter and better the delay is, to reduce delay differences caused under different voltage, different temperature conditions.
In the step (2), the comparison result obtained in the step (1) is sampled by adopting an 8-phase clock with the frequency being 2 times of the output clock of the DAC.
The 8-phase clocks include 8-phase clocks of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees.
The 8 phase clocks are equally delayed in sampling.
The implementation mode of judging whether the DAC works synchronously according to the sampling result in the step (3) is as follows: judging whether the DAC works synchronously according to the result of the step (2), switching to the same clock for judging, judging whether the synchronous requirement is met after accurate sampling, namely, judging whether the phases of two DAC output clocks are consistent, if the synchronous requirement is met, keeping the current state, if the synchronous requirement is not met, generating an indication signal, resetting the two DACs simultaneously, counting, if the rated number is met or the synchronous requirement is not met, adjusting a delay module, and repeating the step (2) and the step (3) until the synchronous requirement is met after the delay is adjusted.
The adjustment delay module, in particular the increase delay or the decrease delay, is adjusted stepwise with an accuracy of less than 80 ps.
Compared with the prior art, the invention has the following beneficial effects:
the invention adopts 8-phase clocks with the frequency being 2 times of the DAC input clocks to sample through CLKXOR2 comparison of two independent DAC output clocks, judges whether the results are synchronous or not under low frequency, has simple and easy realization, ensures the sampling precision, has relatively lower requirement on time sequence, and is an effective, convenient and practical design method.
Drawings
Fig. 1 is a schematic diagram of the principle of the present invention.
Fig. 2 is a schematic flow chart.
Detailed Description
The invention discloses a I, Q-path DAC synchronous design method, which comprises the following steps:
(1) Setting the working modes of two DAC which work independently to be the same, and comparing the output clocks of the two DAC;
(2) Sampling the comparison result obtained in the step (1);
(3) And judging whether the DAC works synchronously or not according to the sampling result, if so, maintaining the working state, if not, generating a reset indication signal and counting, and if the counting reaches a preset value or cannot be synchronized, adjusting the delay module.
A two-way DAC of I, Q is required to operate synchronously and two independent MUXDACs are used for the I-and Q-ways.
The output clocks of the two DACs are compared using comparator CLKXOR 2.
The output clocks of the two independently operated DACs are equally delayed to the input of the comparator CLKXOR2, including off-chip and on-chip delays, and the shorter and better the delay is, to reduce delay differences caused under different voltage, different temperature conditions.
In the step (2), the comparison result obtained in the step (1) is sampled by adopting an 8-phase clock with the frequency being 2 times of the output clock of the DAC.
The 8-phase clocks include 8-phase clocks of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, 315 degrees. The 8 phase clocks are equally delayed in sampling.
The implementation mode for judging whether the DAC works synchronously according to the sampling result is as follows: judging whether the DAC works synchronously according to the result of the step (2), switching to the same clock for judging, judging whether the synchronous requirement is met after accurate sampling, namely, judging whether the phases of two DAC output clocks are consistent, if the synchronous requirement is met, keeping the current state, if the synchronous requirement is not met, generating an indication signal, resetting the two DACs simultaneously, counting, if the rated number is met or the synchronous requirement is not met, adjusting a delay module, and repeating the step (2) and the step (3) until the synchronous requirement is met after the delay is adjusted.
The delay module is adjusted, in particular the delay is increased or decreased, and is adjusted stepwise with an accuracy of less than 80 ps.
The invention is described in further detail below with reference to figures 1, 2 and the accompanying detailed description:
(1) The two independent DAC working modes are set to be identical, the delays from the output clocks DA1 CLK and DA2 CLK of the two independent DACs to the input end of the comparator CLKXOR2 are equal, the delays comprise off-chip delay and on-chip delay, and the shorter the delay is, the better the delay is, so that delay differences caused under different voltage and different temperature conditions are reduced.
(2) The comparison result in the step 1 is sampled by using 8-phase clocks with the frequency being 2 times of the DAC output clock, wherein the 8-phase clocks comprise 8-phase clocks of 0 degree, 45 degree, 90 degree, 135 degree, 180 degree, 225 degree, 270 degree and 315 degree, namely CLK0, CLK45, CLK90, CLK135, CLK180, CLK225, CLK270 and CLK315 in the figure, and the clocks with 8 phases are required to be equal in delay in sampling in design.
(3) Judging whether DAC works are synchronous or not according to sampling results, namely, compact_0, compact_45, compact_90, compact_135, compact_180, compact_225, compact_270 and compact_315, switching to the same clock to judge whether synchronous requirements are met after correct sampling, if synchronous requirements are met, keeping the current state, if synchronous requirements are not met, generating indication signals, resetting two DACs at the same time, counting, and if a certain number of DACs are met or cannot be synchronized, adjusting a delay module, wherein the delay module can increase delay or reduce delay, and gradually adjusts with the accuracy of less than 80ps, and repeating the step (2) and the step (3) after adjusting delay until synchronous requirements are met.
Although the present invention has been described with respect to the preferred embodiments, it is not intended to be limited thereto, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the above embodiments according to the technical matters of the present invention fall within the scope of the technical solution of the present invention.

Claims (3)

1. A I, Q-path DAC synchronous design method is characterized by comprising the following steps:
(1) Setting the working modes of two DAC which work independently to be the same, and comparing the output clocks of the two DAC;
(2) Sampling the comparison result obtained in the step (1);
(3) Judging whether the DAC works synchronously or not according to the sampling result, if so, keeping the working state, if not, generating a reset indication signal and counting, and if the counting reaches a preset value or not, adjusting the delay module;
two-way DAC of I, Q is required to work synchronously, and two independent MUXDACs are used for the I-way and the Q-way;
comparing the output clocks of the two DACs by using a comparator CLKXOR 2;
the delays from the output clocks of the two independent DACs to the input end of the comparator CLKXOR2 are equal, including off-chip and on-chip delays, and the shorter and better the delays are, so as to reduce delay differences caused by different voltages and different temperature conditions;
in the step (2), an 8-phase clock with the frequency 2 times of the DAC output clock is adopted to sample the comparison result obtained in the step (1);
the 8-phase clocks comprise 8-phase clocks of 0 degree, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees and 315 degrees;
the 8 phase clocks are equally delayed in sampling.
2. The I, Q-path DAC synchronous design method of claim 1, wherein: the implementation mode of judging whether the DAC works synchronously according to the sampling result in the step (3) is as follows: judging whether the DAC works synchronously according to the result of the step (2), switching to the same clock for judging, judging whether the synchronous requirement is met after accurate sampling, namely, judging whether the phases of two DAC output clocks are consistent, if the synchronous requirement is met, keeping the current state, if the synchronous requirement is not met, generating an indication signal, resetting the two DACs simultaneously, counting, if the rated number is met or the synchronous requirement is not met, adjusting a delay module, and repeating the step (2) and the step (3) until the synchronous requirement is met after the delay is adjusted.
3. The I, Q-path DAC synchronous design method of claim 2, wherein: the adjustment delay module, in particular the increase delay or the decrease delay, is adjusted stepwise with an accuracy of less than 80 ps.
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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251971A (en) * 1988-03-31 1989-10-06 Toshiba Corp Digital waveform equalizing device
US6097234A (en) * 1997-02-14 2000-08-01 Hyundai Electronics Industries Co., Ltd. Three-phase clock signal generation circuit for LCD driver
CN1277719A (en) * 1998-09-11 2000-12-20 松下电器产业株式会社 Phase comparator and digital phase-locked circuit
EP1158457A1 (en) * 2000-05-26 2001-11-28 Sony Corporation Data synchronizer and data synchronization method
CN101237521A (en) * 2008-01-31 2008-08-06 华为技术有限公司 An extraction device and method for synchronous clock
CN101621296A (en) * 2009-08-06 2010-01-06 北京华力创通科技股份有限公司 High-speed DAC synchronization method and device
CN102768302A (en) * 2012-07-18 2012-11-07 北京无线电计量测试研究所 Double-channel digital phase noise detection device and phase noise detection method
CN103036670A (en) * 2011-12-27 2013-04-10 龙迅半导体科技(合肥)有限公司 Clock recovery circuit and parallel output circuit
CN104158515A (en) * 2014-07-29 2014-11-19 电子科技大学 Autosynchronous multichannel parallel storage DDS (direct digital synthesis) signal generator
CN105678203A (en) * 2015-12-31 2016-06-15 广州中大微电子有限公司 Generation method and system suitable for radio frequency identification (RFID) reader sampling clock
CN107147395A (en) * 2017-04-26 2017-09-08 西安空间无线电技术研究所 A kind of quadrature modulator output DAC synchronous circuits based on bicyclic frequency synthesis
CN111600823A (en) * 2020-05-12 2020-08-28 中国电子科技集团公司第五十四研究所 High-speed parallel OQPSK offset quadriphase shift keying demodulator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5214990B2 (en) * 2008-02-06 2013-06-19 ローム株式会社 Differential phase shift keying (Differential Phase Shift Keying) signal demodulating circuit and radio equipment using the same
JP5561010B2 (en) * 2010-08-09 2014-07-30 富士通株式会社 Successive comparison type AD converter and method of adjusting operation clock of successive approximation type AD converter

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251971A (en) * 1988-03-31 1989-10-06 Toshiba Corp Digital waveform equalizing device
US6097234A (en) * 1997-02-14 2000-08-01 Hyundai Electronics Industries Co., Ltd. Three-phase clock signal generation circuit for LCD driver
CN1277719A (en) * 1998-09-11 2000-12-20 松下电器产业株式会社 Phase comparator and digital phase-locked circuit
EP1158457A1 (en) * 2000-05-26 2001-11-28 Sony Corporation Data synchronizer and data synchronization method
CN101237521A (en) * 2008-01-31 2008-08-06 华为技术有限公司 An extraction device and method for synchronous clock
CN101621296A (en) * 2009-08-06 2010-01-06 北京华力创通科技股份有限公司 High-speed DAC synchronization method and device
CN103036670A (en) * 2011-12-27 2013-04-10 龙迅半导体科技(合肥)有限公司 Clock recovery circuit and parallel output circuit
CN102768302A (en) * 2012-07-18 2012-11-07 北京无线电计量测试研究所 Double-channel digital phase noise detection device and phase noise detection method
CN104158515A (en) * 2014-07-29 2014-11-19 电子科技大学 Autosynchronous multichannel parallel storage DDS (direct digital synthesis) signal generator
CN105678203A (en) * 2015-12-31 2016-06-15 广州中大微电子有限公司 Generation method and system suitable for radio frequency identification (RFID) reader sampling clock
CN107147395A (en) * 2017-04-26 2017-09-08 西安空间无线电技术研究所 A kind of quadrature modulator output DAC synchronous circuits based on bicyclic frequency synthesis
CN111600823A (en) * 2020-05-12 2020-08-28 中国电子科技集团公司第五十四研究所 High-speed parallel OQPSK offset quadriphase shift keying demodulator

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
一种基于片同步技术的高速ADC与FPGA互连方法;韩琦;葛飞;梁圣杰;张之卓;;航天控制(02);全文 *
基于FPGA的时钟数据恢复电路的研究和设计;任全会;赵雨虹;;郑州铁路职业技术学院学报(03);全文 *
基于光脉冲位置调制的异步时钟错位采样数据恢复技术;向劲松;陈雪莉;贾元明;张培;;激光与光电子学进展(12);全文 *
锁相倍频电路在电压信号DSP数据采集中的应用;张旭;黄细霞;孔祥品;代小磊;;电源学报(05);全文 *

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