CN101895334B - Timing synchronization device based on symbol rate adaptive-interpolation and synchronization method thereof - Google Patents
Timing synchronization device based on symbol rate adaptive-interpolation and synchronization method thereof Download PDFInfo
- Publication number
- CN101895334B CN101895334B CN2010102302807A CN201010230280A CN101895334B CN 101895334 B CN101895334 B CN 101895334B CN 2010102302807 A CN2010102302807 A CN 2010102302807A CN 201010230280 A CN201010230280 A CN 201010230280A CN 101895334 B CN101895334 B CN 101895334B
- Authority
- CN
- China
- Prior art keywords
- signal
- links
- adaptive
- interpolation
- symbol rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a timing synchronization device based on a symbol rate adaptive-interpolation and a synchronization method thereof, belonging to the wireless communication technical field. The device comprises a sampler, an adaptive-interpolation filter, a timing error detector, a loop filter, a controller, a multi-phase clock generator and a multiplexer, wherein, the sampler is connected with the adaptive-interpolation filter; the adaptive-interpolation filter is connected with the timing error detector; the timing error detector is connected with the loop filter; the loop filter is connected with the controller; the controller is connected with the adaptive-interpolation filter and the multiplexer; the multi-phase clock generator is connected with the multiplexer; and the multiplexer is connected with the sampler. The invention greatly lowers sampling frequency so as to reduce power consumption, obtains the result close to an ideal sampling value, reduces the number of multiphase clocks and lowers complexity.
Description
Technical field
What the present invention relates to is a kind of devices and methods therefor of wireless communication technology field, specifically is a kind of timing synchronization device and method for synchronous thereof based on symbol rate adaptive-interpolation.
Background technology
Along with the science and technology development and the arrival in information globalization epoch, modern communication technology is just towards digitlization, high speed, and directions such as low-power consumption develop.And along with the needs of multimedia application; Traditional bluetooth, wireless lan (wlan) and ultra broadband wireless communication technologys such as (UWB) can not satisfy the demand of user to the high speed wireless data transmission rate, and they can't provide the message transmission rate of comparing mutually with Gigabit Ethernet, high-definition media interface (HDMI).Therefore can realize that the high-speed radiocommunication system of Gigabit/s even number Gigabit/s transmission rate becomes the new focus of wireless communication field.
Numeral regularly simultaneous techniques is occupied important status in the digital communication receiving system; Be correctly the sample basis of judgement of receiver, the work of follow-up Digital Signal Processing part is all based on to the numeral of time continuous analog signal, discrete sampled value.And because the interference and the unsettled characteristic of oscillator of interchannel noise; Will make the data of transmitting terminal and receiving terminal on frequency or phase place, produce a little error; The accumulation of error is to certain phase; Will make receiving terminal can't guarantee sampling number accurately, perhaps can't sample constantly, thereby can't accomplish the correct recovery of signal at optimum sampling.Therefore, the quality of timing simultaneous techniques is with the performance that directly influences whole system.Existing numeral regularly simultaneous techniques is all to cross the receiver method that the signal that obtains carries out interpolation fitting of sampling is obtained the optimum sampling value mostly.Interpolation is through a controlled finite impulse response filter (adopting the Farrow structure) the discrete sampling value filtering to be realized more.Because the Digital Discrete value is a band-limited signal; In order to carry out undistorted interpolation; The sample rate that just needs to satisfy data is equal to or greater than Nyquist rate at least; Promptly require sample frequency to be equal to or greater than 2 times symbol rate, and sample frequency at a high speed will directly cause the increase of system power dissipation, this seems particularly outstanding in requiring the ultrahigh speed wireless communication system of Gigabit/s speed.Therefore, under the prerequisite that does not influence systematic function, reducing sampling rate, is a major issue that realizes low power dissipation design.In ultrahigh speed communication systems such as UWB, in order to reduce power consumption, sample frequency is the symbolization rate often, and under this condition, traditional numeral timing simultaneous techniques based on interpolation fitting just can't meet the demands.In order to realize low power dissipation design, satisfy the timing synchronisation requirement of ultrahigh speed communication system, just need a kind of timing simultaneous techniques of low symbol sampler rate.
Warp is found existing literature search, Jui-Yuan Yu, and people such as Ching-Che Chung and Chen-Yi Lee are at " IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS-II:EXPRESS BRIEFS " VOL.55; NO.9; 922-926, " the A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDMSystems (a kind of symbol rate time synchronization method that is used for the low-consumption wireless ofdm system, IEEE Circuits and Systems journal in 2008; the 9th phase; 922-926 page or leaf) " that delivers on 2008 proposed a kind of symbol rate time synchronization method that utilizes the multi-phase clock generator, and this method utilizes the multi-phase clock generator based on symbol rate to drive sample circuit; Completion is to the sampling of input signal, and then can reach the purpose that reduces the sampling power consumption.It is symbol rate and equiphase clock signal at interval that the multi-phase clock generator can provide a plurality of frequencies, when sampling, selects one of them suitable clock for use with MUX.But; The drawback of this time synchronization method is that its performance is very big to the dependence of clock number, when clock signal number more after a little while, residual clocking error can reduce the performance of regularly recovering greatly; And if the clock signal number is too many, can make that circuit complexity is too high.
Summary of the invention
The objective of the invention is to overcome the above-mentioned deficiency of prior art, a kind of timing synchronization device and method for synchronous thereof based on symbol rate adaptive-interpolation is provided.The present invention can accomplish regularly with the sampling rate of symbol rate and recover; To when sampling because the not enough issuable residual clocking error of multi-phase clock number; Adopt the method for RLS self-adaptive interpolation filter to eliminate this error; Thereby improved the performance of system greatly and reduced the number of clock phase, and cyclic system is simple in structure, be easy on numeric field hardware and realize.
The present invention realizes through following technical scheme:
The timing synchronization device that the present invention relates to based on symbol rate adaptive-interpolation; Comprise: sampler, adaptive interpolation filters, Timing Error Detector, loop filter, controller, multi-phase clock generator and MUX; Wherein: link to each other with the adaptive interpolation filters sampled signal of transmission symbol of sampler; The adaptive interpolation filters signal after the transmission symbol rate interpolation processing that links to each other with Timing Error Detector; The Timing Error Detector transmit timing error signal that links to each other with loop filter; The loop filter signal of timing error after the transmission process that links to each other with controller, the controller residual clocking error signal of transmission that links to each other with adaptive interpolation filters, controller links to each other with MUX and transmits sampling clock selection signal; The multi-phase clock generator links to each other with MUX and transmits multi-phase clock signal, and MUX links to each other with sampler and transmits sampled clock signal.
Described loop filter is the proportional integral device.
Described controller comprises: mould 1 register, subtracter and control word calculator; Wherein: the mould 1 register transmission register value that links to each other with subtracter; The control word calculator links to each other with subtracter and transmits control word, and subtracter links to each other with mould 1 register and transmits object information, and mould 1 register links to each other with MUX and transmits sampling clock information; Mould 1 register links to each other with adaptive interpolation filters and transmits residual clocking error information, and the control word calculator links to each other with loop filter and receives timing error information.
Described adaptive interpolation filters is used to eliminate the influence of residual clocking error; Comprise: RLS (least square method) sef-adapting filter and an adder; Wherein: the RLS sef-adapting filter links to each other with adder and transmits filtered and sampled signal; The RLS sef-adapting filter links to each other with sampler and receives sampled signal, and the RLS sef-adapting filter links to each other with controller and receives residual clocking error information, and adder links to each other with Timing Error Detector and transmits interpolation result information.
The method for synchronous of the above-mentioned timing synchronization device based on symbol rate adaptive-interpolation that the present invention relates to may further comprise the steps:
The first step, the continuous signal of input is carried out the optimum sampling of symbol rate, the signal after obtaining sampling through sampler.
The optimum sampling of described symbol rate is:
1) the multi-phase clock generator produces some symbol frequency multi-phase clock signals;
2) controller provides the optimum sampling clock signal to MUX, and MUX is selected from the plurality of polyphase clock signal and the minimum clock signal S of desirable sampled point phase difference value;
3) the clock signal S of sampler utilization selection carries out the symbol rate sampling to input signal.
Second step, the signal after the sampling is carried out symbol rate adaptive-interpolation handle, obtain approaching the signal of desirable sampled value.
Described symbol rate adaptive-interpolation is handled, and is:
Wherein: x (k) is a k sampled value constantly, w
nBe tap coefficient, Δ t is the residual clocking error between actual samples point and desirable sampled point, z
kIt is the k signal that approaches desirable sampled value constantly.
Described w
nUpgrade through existing RLS adaptive approach.
The 3rd step, the signal that approaches desirable sampled value is carried out timing error successively detect and Filtering Processing, obtain filtered signal of timing error.
It is to adopt Mueller & Muller detection method to realize that the k that obtains is timing error consequential signal e constantly that described timing error detects
kFor:
e
k＝Re[c
k *z
k-1-c
k-1 *z
k]，
Wherein: z
kBe the k signal that approaches desirable sampled value constantly, z
K-1Be the k-1 signal that approaches desirable sampled value constantly, c
kBe corresponding z
kDecision value, c
K-1Be corresponding z
K-1Decision value, Re representes to get real part,
*Conjugation is got in expression.
The 4th step, filtered signal of timing error is carried out control and treatment, the optimum sampling clock signal that obtains is outputed to MUX, and the residual clocking error signal that will obtain outputs to adaptive interpolation filters.
Described control and treatment may further comprise the steps:
1) according to k moment signal of timing error e
kWith k moment control word w
kRelation: w
k=e
k+ 1, obtain k control word w constantly
k
2) according to r
k=mod (r
K-1-w
K-1) 1, the value r of die sinking 1 register when obtaining k
k, wherein: r
K-1The value of die sinking 1 register when being k-1, w
K-1It is k-1 control word constantly;
The value r of die sinking 1 register when 3) obtaining k
kWith k moment control word w
kDifference, and obtain this difference and k control word w constantly
kRatio t;
4) according to [t*n], obtain the optimum sampling clock signal in the optimum sampling of symbol rate, according to t*n-[t*n], obtain the residual clocking error information of symbol rate adaptive-interpolation in handling, wherein: n is the multi-phase clock number, [] expression rounds.
Compared with prior art, the invention has the beneficial effects as follows:
(1) only needs a sampled value for each symbol, reduced power consumption thereby greatly reduce sample frequency.Several equiphase interval timers through the generation of multi-phase clock generator; Utilize controller to select clock near desirable sampled point; Thereby make sampled value as far as possible near desirable sampled value, simultaneously, because Timing Error Detector has been selected Mueller & Muller method for use; Make each data only need a sampled value just can calculate timing error, thereby can accomplish regularly synchronously.
(2) utilize the method for RLS self-adaptive interpolation filter to handle residual clocking error; Make the result approach desirable sampled value as far as possible; The RLS adaptive approach has the characteristics of fast convergence rate, can be soon the influence of residual clocking error is reduced to minimum, utilizes the RLS self-adaptive interpolation filter to handle the influence that reduces residual clocking error simultaneously; Reduce the multi-phase clock number, thereby reduced complexity.
Description of drawings
Fig. 1 is an apparatus structure sketch map of the present invention;
Fig. 2 is the structural representation of the adaptive interpolation filters of embodiment;
Fig. 3 is the residual clocking error sketch map of embodiment;
Fig. 4 is the timing synchronization simulation sketch map of embodiment;
Wherein: figure (a) only carries out the optimum sampling of symbol rate when being 4 clock samplings, and does not carry out the sampling analogous diagram that obtains when symbol rate adaptive-interpolation is handled; The emulation sketch map that the embodiment method obtains when (b) being 4 clock samplings; Only carry out the optimum sampling of symbol rate when (c) being 8 clock samplings, and do not carry out the sampling analogous diagram that obtains when symbol rate adaptive-interpolation is handled; The emulation sketch map that the embodiment method obtains when (d) being 8 clock samplings; Abscissa is represented homophase, and ordinate is represented quadrature.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are further described: present embodiment provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment being to implement under the prerequisite with technical scheme of the present invention.
Embodiment
As shown in Figure 1; The timing synchronization device that present embodiment relates to based on symbol rate adaptive-interpolation; Comprise: sampler, adaptive interpolation filters, Timing Error Detector, loop filter, controller, multi-phase clock generator and MUX; Wherein: link to each other with the adaptive interpolation filters sampled signal of transmission symbol of sampler; The adaptive interpolation filters signal after the transmission symbol rate interpolation processing that links to each other with Timing Error Detector, the Timing Error Detector transmit timing error signal that links to each other with loop filter, the loop filter signal of timing error after the transmission process that links to each other with controller; Controller links to each other with adaptive interpolation filters and transmits residual clocking error signal; Controller links to each other with MUX and transmits sampling clock selection signal, and the multi-phase clock generator links to each other with MUX and transmits multi-phase clock signal, and MUX links to each other with sampler and transmits sampled clock signal.
Described sampler is used for the symbol rate sampling, according to the optimum sampling clock of MUX output the time-continuous signal of input is sampled, and symbol frequency is 100MHz in the present embodiment.
Described multi-phase clock generator produces one group and has equiphase clock at interval, and clock frequency is a symbol rate, and the multi-phase clock generator produces 4 equiphase interval timers in the present embodiment, and promptly 4 clocks respectively differ for four/one-period.
Described loop filter adopts classical proportional integral device, and the parameter of proportional path and path of integration is respectively 0.2 and 0.002 in the present embodiment.
Described controller comprises: mould 1 register; Subtracter and control word calculator, wherein: the mould 1 register transmission register value that links to each other with subtracter, the control word calculator transmission control word that links to each other with subtracter; Subtracter links to each other with mould 1 register and transmits object information; The mould 1 register transmission sampling clock information that links to each other with MUX, mould 1 register links to each other with adaptive interpolation filters and transmits residual clocking error information, the control word calculator transmit timing control information that links to each other with loop filter.
Described adaptive interpolation filters is used to eliminate the influence of residual clocking error; Comprise: a RLS sef-adapting filter and an adder; Wherein: the RLS sef-adapting filter links to each other with adder and transmits filtered and sampled signal; The RLS sef-adapting filter links to each other with sampler and receives sampled signal, and the RLS sef-adapting filter links to each other with controller and receives residual clocking error information, and adder links to each other with Timing Error Detector and transmits interpolation result information.
As shown in Figure 2, the structure of RLS sef-adapting filter is FIR (Finite Impulse Response, a finite impulse response (FIR)) filter in the present embodiment, wherein: z
-1The expression register, w
MBe M tap coefficient, in the present embodiment, filter order is 15 rank.
The method for synchronous of present embodiment relates to above-mentioned timing synchronization device based on symbol rate adaptive-interpolation may further comprise the steps:
The first step, the continuous signal of input is carried out the optimum sampling of symbol rate through sampler, obtains k sampled value x (k) constantly.
The optimum sampling of described symbol rate is:
1) the multi-phase clock generator produces 4 equiphase interval timer signals;
2) controller provides the optimum sampling clock signal to MUX, and MUX is selected from 4 equiphase interval timer signals and the minimum clock signal S of desirable sampled point phase difference value;
3) the clock signal S of sampler utilization selection carries out the symbol rate sampling to input signal.
There is residual clocking error in reasons such as the limited or clock jitter of the multi-phase clock number that produces owing to the multi-phase clock generator between clock that sampler is used to sample and the desirable sampled point, as shown in Figure 3, wherein: t
2The corresponding ideal sampling instant, what from the uniformly-spaced phase clock that the multi-phase clock generator produces, selected by controller is t near the clock of desirable sampling instant
1, selected sampling clock t
1With desirable sampling clock t
2Between certain error delta t is arranged, Δ t is residual clocking error, because the influence of residual clocking error, makes sampled value and be not equal to desirable sampled value, this will be handled by the RLS sef-adapting filter by the influence that residual clocking error brings.
Second step, the signal after the sampling is carried out symbol rate adaptive-interpolation handle, obtain approaching the signal of desirable sampled value.
Described symbol rate adaptive-interpolation is handled and is accomplished by adaptive interpolation filters; As shown in Figure 2; Its importation comprises: the k of sampler symbol rate sampling is sampled value x (k) constantly; Residual clocking error Δ t, the desired value d of adaptive interpolation filters (k), continuous time signal is a at k value of symbol constantly
k, total impulse response is sampled to h
k, then sampler in k sampled value constantly is:
Wherein: T is the cycle of symbol, and is inclined to one side when t is signal.
h
kBe expressed as:
h
k＝h(kT-t
1) (2)
t
1Can see the sampling instant of the sampling clock that elects, corresponding to the t among Fig. 3
1Because desirable sampling instant is t
2, the impulse response sampling g of desirable sampling
kFor:
g
k＝h(kT-t
2) (3)
Then desirable sampled value is expressed as:
Can obtain the relation of desirable sampled value z (k) and actual sample value x (k) by formula (1) and formula (4):
For h
kAnd g
k, utilize first order Taylor can obtain its relation to be:
g
k＝h
k+Δt·h
k′ (6)
With (6) formula substitution (5) formula, and make w
k=h
-1H
k' the relation that can obtain desirable sampled value and actual sample value is:
Wherein: w
nBe the tap coefficient of adaptive interpolation filters, w
nUpgrade according to the RLS adaptive approach.
The tap of adaptive interpolation filters is input as the product of sampled value x (k) and current residual clocking error Δ t; The desired value d of adaptive-filtering (k) is the difference of value z (k) Yu the actual sample value x (k) of desirable sampling instant; Wherein: z (k) can be obtained by training sequence; Treat that filter can substitute with the decision value of sampling after stable, error e (k) is the difference that d (k) and filter are exported y (k).(7) formula of utilization through the RLS adaptive-filtering, is exported y (k) with filter and is added that corresponding sampled value x (k) promptly obtains approaching the interpolation of desirable sampled value, and deliver to Timing Error Detector.
The 3rd step, the signal that approaches desirable sampled value is carried out timing error successively detect and Filtering Processing, obtain filtered signal of timing error.
It is to adopt Mueller & Muller detection method to realize that the k that obtains is timing error consequential signal e constantly that described timing error detects
kFor:
e
k＝Re[c
k *z
k-1-c
k-1 *z
k]，
Wherein: z
kBe the k signal that approaches desirable sampled value constantly, z
K-1Be the k-1 signal that approaches desirable sampled value constantly, c
kBe corresponding z
kDecision value, c
K-1Be corresponding z
K-1Decision value, Re representes to get real part,
*Conjugation is got in expression.
The 4th step, filtered signal of timing error is carried out control and treatment, the optimum sampling clock signal that obtains is outputed to MUX, and the residual clocking error signal that will obtain outputs to adaptive interpolation filters.
Described control and treatment may further comprise the steps:
1) according to k moment signal of timing error e
kWith k moment control word w
kRelation: w
k=e
k+ 1, obtain k control word w constantly
k
2) according to r
k=mod (r
K-1-w
K-1) 1, the value r of die sinking 1 register when obtaining k
k, wherein: r
K-1The value of die sinking 1 register when being k-1, w
K-1It is k-1 control word constantly;
The value r of die sinking 1 register when 3) obtaining k
kWith k moment control word w
kDifference, and obtain this difference and k control word w constantly
kRatio t;
4) according to [t*n], obtain the optimum sampling clock signal in the optimum sampling of symbol rate, according to t*n-[t*n], obtain the residual clocking error information of symbol rate adaptive-interpolation in handling, wherein: n is the multi-phase clock number, [] expression rounds.
When adopting the QPSK modulation system, and desirable sampled point is when being positioned in the middle of adjacent two clocks of multi-phase clock just, and the simulation result that present embodiment obtains is as shown in Figure 4; Wherein: Fig. 4 (a) is the optimum sampling that only carries out symbol rate; And do not carry out the sampling analogous diagram that obtains when symbol rate adaptive-interpolation is handled, can know the synchronous requirement of sampled value basic symbol by this figure; But because the influence of residual clocking error, sampled value is not on desirable sampled point; Fig. 4 (b) is the simulation result figure that the present embodiment technology obtains, and can be known by this figure, and the result approaches to desirable sampled value, and effect obviously is superior to Fig. 4 (a).
Constant in other condition; When the clock number that only the multi-phase clock generator is produced is brought up to 8, only carry out the optimum sampling of symbol rate, and the sampling analogous diagram of not carrying out obtaining when symbol rate adaptive-interpolation is handled is shown in Fig. 4 (c); Can know by this figure; Because the clock number increases, and makes sampling precision that raising arranged, but still there is tangible residual clocking error influence; The simulation result figure that the present embodiment technology obtains can be known by this figure that shown in Fig. 4 (d) on the basis of 8 clock samplings, the result after the processing approaches desirable sampled value very much.
In real system, can be according to the requirement of precision and complexity, choose reasonable multi-phase clock number.Present embodiment only needs a sampled value to each symbol, greatly reduces sample frequency, thereby has reduced power consumption; And, carry out interpolation processing with adaptive approach, to approach desirable sampled value to sampling clock that causes owing to the clock deficiency and the residual clock jitter between the desirable sampled point; Thereby reduced required clock number; Reduced the system design complexity, self-adaptive processing adopts convergence rate RLS method faster, can improve the precision of sampling soon.
Claims (8)
1. timing synchronization device based on symbol rate adaptive-interpolation; Comprise: sampler, loop filter, controller, multi-phase clock generator and MUX; It is characterized in that; Also comprise: adaptive interpolation filters and Timing Error Detector, wherein: link to each other with the adaptive interpolation filters sampled signal of transmission symbol of sampler, the adaptive interpolation filters signal after the transmission symbol rate interpolation processing that links to each other with Timing Error Detector; The Timing Error Detector transmit timing error signal that links to each other with loop filter; The loop filter signal of timing error after the transmission process that links to each other with controller, the controller residual clocking error signal of transmission that links to each other with adaptive interpolation filters, controller links to each other with MUX and transmits sampling clock selection signal; The multi-phase clock generator links to each other with MUX and transmits multi-phase clock signal, and MUX links to each other with sampler and transmits sampled clock signal;
Described adaptive interpolation filters comprises: a RLS sef-adapting filter and an adder; Wherein: the RLS sef-adapting filter links to each other with adder and transmits filtered and sampled signal; The RLS sef-adapting filter links to each other with sampler and receives sampled signal; The RLS sef-adapting filter links to each other with controller and receives residual clocking error information, and adder links to each other with Timing Error Detector and transmits interpolation result information.
2. the timing synchronization device based on symbol rate adaptive-interpolation according to claim 1 is characterized in that, described loop filter is the proportional integral device.
3. the timing synchronization device based on symbol rate adaptive-interpolation according to claim 1; It is characterized in that; Described controller comprises: mould 1 register, subtracter and control word calculator, wherein: the mould 1 register transmission register value that links to each other with subtracter, the control word calculator transmission control word that links to each other with subtracter; Subtracter links to each other with mould 1 register and transmits object information; The mould 1 register transmission sampling clock information that links to each other with MUX, mould 1 register links to each other with adaptive interpolation filters and transmits residual clocking error information, the control word calculator transmit timing control information that links to each other with loop filter.
4. the method for synchronous of the timing synchronization device based on symbol rate adaptive-interpolation according to claim 1 is characterized in that, may further comprise the steps:
The first step, the continuous signal of input is carried out the optimum sampling of symbol rate, the signal after obtaining sampling through sampler;
Second step, the signal after the sampling is carried out symbol rate adaptive-interpolation handle, obtain approaching the signal of desirable sampled value;
The 3rd step, the signal that approaches desirable sampled value is carried out timing error successively detect and Filtering Processing, obtain filtered signal of timing error;
The 4th step, filtered signal of timing error is carried out control and treatment, the optimum sampling clock signal that obtains is outputed to MUX, and the residual clocking error signal that will obtain outputs to adaptive interpolation filters.
5. method for synchronous according to claim 4 is characterized in that, the optimum sampling of the symbol rate described in the first step is:
1) the multi-phase clock generator produces some symbol frequency multi-phase clock signals;
2) controller provides the optimum sampling clock signal to MUX, and MUX is selected from the plurality of polyphase clock signal and the minimum clock signal S of desirable sampled point phase difference value;
3) the clock signal S of sampler utilization selection carries out the symbol rate sampling to input signal.
6. method for synchronous according to claim 4 is characterized in that, the symbol rate adaptive-interpolation described in second step is handled, and is:
Wherein: x (k) is a k sampled value constantly, w
nBe the tap coefficient that upgrades through existing RLS adaptive approach, Δ t is the residual clocking error between actual samples point and desirable sampled point, z
kIt is the k signal that approaches desirable sampled value constantly.
7. method for synchronous according to claim 4 is characterized in that, it is to adopt Mueller & Muller detection method to realize that the k that obtains is timing error consequential signal e constantly that the timing error described in the 3rd step detects
kFor:
e
k＝Re[c
k *z
k-1-c
k-1 *z
k]，
Wherein: z
kBe the k signal that approaches desirable sampled value constantly, z
K-1Be the k-1 signal that approaches desirable sampled value constantly, c
kBe corresponding z
kDecision value, c
K-1Be corresponding z
K-1Decision value, Re representes to get real part,
*Conjugation is got in expression.
8. method for synchronous according to claim 4 is characterized in that, the control and treatment described in the 4th step may further comprise the steps:
1) according to k moment timing error consequential signal e
kWith k moment control word w
kRelation: w
k=e
k+ 1, obtain k control word w constantly
k
2) according to r
k=mod (r
K-1-w
K-1) 1, the value r of die sinking 1 register when obtaining k
k, wherein: r
K-1The value of die sinking 1 register when being k-1, w
K-1It is k-1 control word constantly;
The value r of die sinking 1 register when 3) obtaining k
kWith k moment control word w
kDifference, and obtain this difference and k control word w constantly
kRatio t;
4) according to [t*n], obtain the optimum sampling clock signal in the optimum sampling of symbol rate, according to t*n-[t*n], obtain the residual clocking error signal of symbol rate adaptive-interpolation in handling, wherein: n is the multi-phase clock number, [] expression rounds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102302807A CN101895334B (en) | 2010-07-20 | 2010-07-20 | Timing synchronization device based on symbol rate adaptive-interpolation and synchronization method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102302807A CN101895334B (en) | 2010-07-20 | 2010-07-20 | Timing synchronization device based on symbol rate adaptive-interpolation and synchronization method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101895334A CN101895334A (en) | 2010-11-24 |
| CN101895334B true CN101895334B (en) | 2012-09-19 |
Family
ID=43104419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102302807A Expired - Fee Related CN101895334B (en) | 2010-07-20 | 2010-07-20 | Timing synchronization device based on symbol rate adaptive-interpolation and synchronization method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101895334B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102752006A (en) * | 2011-04-22 | 2012-10-24 | 无锡士康通讯技术有限公司 | Baseband demodulation circuit for radio frequency receiver |
| CN102255864B (en) * | 2011-08-30 | 2013-05-29 | 豪威科技(上海)有限公司 | Low-complexity general sampling recovery method and device |
| CN103582107B (en) * | 2012-07-19 | 2018-06-26 | 中兴通讯股份有限公司 | A kind of output control method and device of Symbol Timing ring |
| CN103607365A (en) * | 2013-11-14 | 2014-02-26 | 成都林海电子有限责任公司 | Data demodulation method for satellite remote sensing signal |
| CN104062494B (en) * | 2014-05-30 | 2018-08-14 | 深圳市中电软件有限公司 | It is a kind of inhibit spectrum leakage sampling interval compensation method and system |
| CN106842248A (en) * | 2016-11-23 | 2017-06-13 | 西安电子科技大学昆山创新研究院 | A kind of new method for improving Beidou receiver timing locating speed |
| CN107884745B (en) * | 2017-10-24 | 2021-08-10 | 深圳大学 | Atmospheric error processing method for UWB positioning |
| EP3569986B1 (en) * | 2018-05-14 | 2020-04-08 | Melexis Technologies NV | Position sensing device |
| CN109756206A (en) * | 2018-12-24 | 2019-05-14 | 科大讯飞股份有限公司 | Interpolation filter construction method and system |
| CN111130595B (en) * | 2019-12-23 | 2021-10-15 | 东方红卫星移动通信有限公司 | Low-earth-orbit satellite feed link timing synchronization method |
| CN111245544A (en) * | 2020-01-08 | 2020-06-05 | 西安电子科技大学 | Timing synchronization improvement method for symbol rate deviation in non-cooperative communication system |
| CN113542166B (en) * | 2021-06-10 | 2022-07-22 | 西安电子科技大学 | Timing recovery method and device with low jitter and rapid convergence |
| CN115996111B (en) * | 2023-03-24 | 2023-06-27 | 湖南迈克森伟电子科技有限公司 | Sampling clock signal generation method, symbol synchronization method and related device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049763A (en) * | 1998-07-28 | 2000-02-18 | Matsushita Electric Ind Co Ltd | Receiver, automatic frequency correction device and communication equipment |
| CN1323494A (en) * | 1998-08-14 | 2001-11-21 | 夸尔柯姆股份有限公司 | Synchronisation of a low power clock in a wireless communication device |
| CN1510933A (en) * | 2002-12-21 | 2004-07-07 | 深圳市中兴通讯股份有限公司 | Method for clock synchronization by wireless interface |
| CN1897495A (en) * | 2005-07-13 | 2007-01-17 | 三洋电机株式会社 | Wireless receiving device having low power consumption and excellent reception performance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7263090B2 (en) * | 2002-02-01 | 2007-08-28 | Viasat, Inc. | System and method of timing and frequency control in TDM/TDMA networks |
-
2010
- 2010-07-20 CN CN2010102302807A patent/CN101895334B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049763A (en) * | 1998-07-28 | 2000-02-18 | Matsushita Electric Ind Co Ltd | Receiver, automatic frequency correction device and communication equipment |
| CN1323494A (en) * | 1998-08-14 | 2001-11-21 | 夸尔柯姆股份有限公司 | Synchronisation of a low power clock in a wireless communication device |
| CN1510933A (en) * | 2002-12-21 | 2004-07-07 | 深圳市中兴通讯股份有限公司 | Method for clock synchronization by wireless interface |
| CN1897495A (en) * | 2005-07-13 | 2007-01-17 | 三洋电机株式会社 | Wireless receiving device having low power consumption and excellent reception performance |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101895334A (en) | 2010-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101895334B (en) | Timing synchronization device based on symbol rate adaptive-interpolation and synchronization method thereof | |
| JP6568247B2 (en) | N-phase signal transition alignment | |
| CN1719818B (en) | Apparatus and method for processing sampling frequency deviation tracking signal in orthogonal frequency division multiplex system | |
| US10389555B2 (en) | Phase delay difference-based channel compensation | |
| CN106998236A (en) | A kind of feedback-type symbol timing synchronizing apparatus and method based on filtering interpolation | |
| CN104184451A (en) | Reconfigurable circuit block and exemplary method for configuring the circuit block | |
| JP5476506B2 (en) | On-the-fly compensation of sampling frequency and phase offset on the receiver side for ultra-high-speed wireless communication | |
| US20140169442A1 (en) | Clock data recovery method and clock data recovery circuit | |
| CN108989260A (en) | The digital time synchronization method of modified and device based on Gardner | |
| CN111600823B (en) | Parallel OQPSK offset quadriphase shift keying demodulator | |
| CN110752870B (en) | Timing recovery method and device for roll-off coefficient variable broadband satellite transmission system | |
| CN104125052A (en) | Parallel timing synchronization system and method | |
| CN104516397A (en) | Method for portable device processing data based on clock extracted from data form host | |
| CN111245544A (en) | Timing synchronization improvement method for symbol rate deviation in non-cooperative communication system | |
| US11570024B2 (en) | Equalizer with perturbation effect based adaptation | |
| CN103957003A (en) | Time to digital converter and frequency tracking device and method | |
| CN1842070B (en) | Timing recovery circuit with multiple stages | |
| CN107623654B (en) | FPGA-based bit timing synchronization method for high-speed 16apsk signal | |
| WO2012088840A1 (en) | Clock synchronization method and device | |
| CN104717051B (en) | A kind of Interpolate estimation method in parallel demodulation bit synchronization | |
| CN111130595B (en) | Low-earth-orbit satellite feed link timing synchronization method | |
| CN101854320B (en) | Estimating and correcting device of sampling clock in VSB (Vestigial Sideband) modulation system | |
| CN101320982B (en) | Time sequence reply parameter generation circuit and signal receiving circuit | |
| EP0353891A2 (en) | Synchronising fractional tap equalisation with received signals | |
| EP3160077B1 (en) | Clock recovery apparatus and clock recovery method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120919 Termination date: 20150720 |
|
| EXPY | Termination of patent right or utility model |