CN102752006A - Baseband demodulation circuit for radio frequency receiver - Google Patents
Baseband demodulation circuit for radio frequency receiver Download PDFInfo
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- CN102752006A CN102752006A CN2011101059460A CN201110105946A CN102752006A CN 102752006 A CN102752006 A CN 102752006A CN 2011101059460 A CN2011101059460 A CN 2011101059460A CN 201110105946 A CN201110105946 A CN 201110105946A CN 102752006 A CN102752006 A CN 102752006A
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Abstract
The invention discloses a baseband demodulation circuit for a radio frequency receiver. The baseband demodulation circuit comprises an analog/digital conversion module, a matching filter, a withdrawal device and a synchronous tracking circuit, wherein the synchronous tracking circuit is connected with the matching filter and the withdrawal device respectively, detects an error of a signal received from the matching filter, adjusts the error of the received signal according to the error detection result, obtains the displacement d and transmits the adjusted signal and the displacement d to the withdrawal device; and the withdrawal device withdraws a sign signal for the signal received from the synchronous tracking circuit according to the displacement d received from the synchronous tracking circuit. According to the baseband demodulation circuit for the radio frequency receiver, the displacement d of the withdrawal device is adjusted at any time through the synchronous tracking circuit, so that the clock of a transmitter is tracked, and the phenomenon of failed reception caused by clock errors is avoided.
Description
Technical field
The present invention relates to the signal processing technology of radio-frequency transmitter in the wireless communication field, particularly a kind of base band demodulating circuit of radio-frequency transmitter.
Background technology
At present, radio communication has developed into the digital communication stage, and an important step in the digital communication is a clock stability.Specifically, the clock of radio frequency sending set and radio-frequency transmitter need highly be consistent.If the clock of radio-frequency transmitter and radio frequency sending set have deviation, along with the postponement of time, the situation that receiver can occur having sampled many or lack, this is just the reliability of influence communication.
With European digital handset standard DPMR is example (etsi standard TS 102 490 and TS 102 658).The character rate of DPMR is 2400 symbols of per second.The longest call duration time of standard-required is 180 seconds, promptly in 180 second time, transmits under the situation of 432k symbol, and the deviation of a symbol can not be arranged.So DPMR is 2ppm to the error requirements of base band clock.
Yet clock crystal error more common on the market is all greater than 5ppm, and more in the majority and cheap with the crystal of error 20ppm.Error is that the crystal of 2ppm is generally customized, and cost is much higher.This has influenced the popularization of digital handset.
The reason that needs the 2ppm crystal; Be because the DPMR standard when formulating; Adopted the simplest base band demodulating circuit in the radio-frequency transmitter, this circuit structure is as shown in Figure 1, comprising: analog-to-digital conversion module 101, matched filter 102, withdrawal device 103 and simple synchronization module 104.
Wherein, analog-to-digital conversion module 101 converts analog baseband signal into digital signal and sends to matched filter 102.Its conversion regime is following:
y(n)＝yt(nT/N)
Wherein yt (t) is the analog signal that receives, y (n) be on the time point of t=nT/N, sample the digital signal of falling, the T is-symbol is at interval.N is an over-sampling rate.To the DPMR system, T=1/2400 second, N＞=4.
The filter that the ideal signal that matched filter 102 adopts and receives has same waveform as carries out filtering to the received signal, and filtered signal is sent to withdrawal device 103 and simple synchronization module 104, to reduce the error rate.Its operation principle is:
Suppose that the signal that receives is y (n)=x (n)+n (n),
Wherein x (n) is that ideal transmits, and n (n) comprises noise and interference signal, and y (n) is the signal that receiver is received.
Matched filter 102 has and ideal same waveform: h (the n)=x (n) that transmitted
It is output as z (n)=conv (y (n), h (n)), wherein conv () expression filtering operation.
Withdrawal device 103 extracts mark signal: S (k)=z (N*k+d) from the output signal of the matched filter 102 of over-sampling, thus signal after the acquisition demodulation.
Wherein n=N*k+d representes k sample point, and d=0 is to N-1.An output signal is extracted in this expression formula explanation from every N input signal, which specifically extracts determined by displacement d.Displacement d is calculated by simple synchronization module 104.In case displacement d calculates, in the whole conversation cycle, no longer change.
The output signal z (n) of 104 pairs of matched filters 102 of simple synchronization module calculates, and obtains displacement d and sends to withdrawal device 103.
In case, in the whole conversation cycle, no longer change because prior art displacement d calculates, that is to say synchronously and only when receiving beginning, carry out, make this receiver not have the clock tracing performance.Therefore, any point clock skew through certain hour, all possibly cause to take defeat, thereby cause communication disruption.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of base band demodulating circuit of radio-frequency transmitter, make receiver have the clock tracing performance, reduce the phenomenon that takes defeat that causes because of clocking error.
For achieving the above object, the invention provides a kind of base band demodulating circuit of radio-frequency transmitter, comprising: analog-to-digital conversion module, matched filter and withdrawal device also comprise synchronous follow-up circuit.
Said synchronous follow-up circuit links to each other respectively with withdrawal device with matched filter; It carries out error-detecting to the signal that receives from matched filter, and according to the error-detecting result, the signal that receives is carried out the error adjustment; And obtain displacement d, adjusted signal and displacement d are sent to withdrawal device;
Withdrawal device is according to the displacement d that receives from synchronous follow-up circuit, to the signal extraction mark signal that receives from synchronous follow-up circuit.
Preferably, saidly comprise according to circuit synchronously: interpolation is recovered module, error-detecting module and loop filtering module.
Said interpolation is recovered module and is linked to each other respectively with withdrawal device with matched filter, error-detecting module, loop filtering module; It is according to the signal of timing error that receives from the loop filtering module; The signal that receives from matched filter is passed through the signal after linear interpolation produces an interpolation, export to error-detecting module and withdrawal device respectively.
The error-detecting module also links to each other with the loop filtering module, the signal that recovers the module reception from interpolation is carried out timing error detect, and the timing error testing result is sent to the loop filtering module.
The loop filtering module also links to each other with withdrawal device; Timing error testing result to receiving from the error-detecting module is carried out filtering; Obtain the stable timing error that comprises integer part and fractional part; Wherein fractional part is sent to interpolation as signal of timing error recover module, wherein integer part is sent to withdrawal device as displacement d.
Withdrawal device is according to the displacement d that receives from the loop filtering module, to recovering the signal extraction mark signal that module receives from interpolation.
Preferably, described analog-to-digital conversion module is the analog-to-digital conversion module by following formula manipulation:
y(n)＝yt(nT/N)
Wherein: yt (t) is the analog signal that receives, and y (n) is the digital signal that sampling obtains on the time point of t=nT/N, T is-symbol interval, and N is an over-sampling rate.
Preferably, said matched filter adopts the receiving filter identical with emission filter, and it will send to interpolation from the signal that analog-to-digital conversion module receives and recover module.
Preferably, said interpolation is recovered the linear interpolation device realization of module by the following interpolation algorithm of employing:
r(n)＝z(n)*u+z(n-1)*(1-u)
0＜=u＜1st wherein, the signal of timing error that receives from the loop filtering module.
Preferably, said error-detecting module is for adopting the Gardner's algorithm or the error detector of door algorithm sooner or later.
Preferably, said error-detecting module is realized by the error detector that adopts following algorithm:
e(k)＝(r((k-1)*N+b)-r(k*N+b))*r(k*N-N/2+b)
Wherein r representes that interpolation recovers the output signal of module, and k representes sampled point, and N representes over-sampling rate, and T representes symbol period, and b representes the deviation of sampling.
Preferably, said loop filtering module is realized by 1 rank IIR filter of the Gain Adjustable that adopts following formula manipulation:
E(k)＝E(k-1)+a·e(k)
Wherein, E is the timing error testing result of error-detecting module output for accumulation timing error, e, and 0＜a＜1 is a time constant.
Visible by above-mentioned technical scheme; The base band demodulating circuit of this radio-frequency transmitter of the present invention adjusts at any time the displacement d of withdrawal device through synchronous follow-up circuit; Thereby realized tracking, and then reduced the phenomenon that takes defeat that causes because of clocking error transmitter clock.
Description of drawings
Fig. 1 is the base band demodulating electrical block diagram of prior art radio-frequency transmitter;
Fig. 2 is the base band demodulating electrical block diagram of radio-frequency transmitter first preferred embodiment of the present invention;
Fig. 3 is the base band demodulating electrical block diagram of radio-frequency transmitter second preferred embodiment of the present invention;
Fig. 4 is for adopting the tracking results curve chart of base band demodulating circuit shown in Figure 3 to transmit clock.
Embodiment
The base band demodulating circuit of this radio-frequency transmitter of the present invention adjusts at any time the displacement d of withdrawal device through synchronous follow-up circuit, thereby has realized the tracking to transmitter clock, and then has reduced the phenomenon that takes defeat that causes because of clocking error.
Below lift two preferred embodiments, and contrast accompanying drawing specific embodiments of the invention is elaborated.
First preferred embodiment:
As shown in Figure 2, the base band demodulating circuit of radio-frequency transmitter first preferred embodiment of the present invention comprises: analog-to-digital conversion module 201, matched filter 202, synchronous follow-up circuit 203 and withdrawal device 204.
Wherein, analog-to-digital conversion module 201 converts analog baseband signal into digital signal and sends to matched filter 202.Its conversion regime is identical with prior art, and is specific as follows:
y(n)＝yt(nT/N)
Wherein yt (t) is the analog signal that receives, and y (n) is the digital signal that sampling obtains on the time point of t=nT/N, and the T is-symbol at interval.N is an over-sampling rate.To the DPMR system, T=1/2400 second, N＞=4.
The filter that the ideal signal that matched filter 202 adopts and receives has same waveform as carries out filtering to the received signal, and filtered signal is sent to synchronous follow-up circuit 203, to reduce the error rate.Its operation principle is identical with prior art, is specially:
Suppose that the signal that receives is y (n)=x (n)+n (n),
Wherein x (n) is that ideal transmits, and n (n) comprises noise and interference signal, and y (n) is the signal that receiver is received.
In the present embodiment, matched filter 202 has and the ideal same waveform that transmitted:
h(n)＝x(n)
It is output as z (n)=conv (y (n), h (n)), wherein conv () expression filtering operation.
Synchronous follow-up circuit 203 links to each other respectively with withdrawal device 204 with matched filter 202 among Fig. 2; It carries out error-detecting to the signal that receives from matched filter 202; And according to the error-detecting result; The signal that receives is carried out the error adjustment, and obtain displacement d, adjusted signal and displacement d are sent to withdrawal device 204.
Can adopt in the present embodiment Gardner's algorithm or sooner or later a door algorithm carry out error-detecting, come the signal that receives is carried out the error adjustment through methods such as linear interpolations.
Synchronous follow-up circuit 203 in the present embodiment can adopt programmable logic device, realizes through software, also can adopt discrete component to cooperate and realize.
Wherein n=N*k+d representes k sample point, and d=0 is to N-1.
Second preferred embodiment:
As shown in Figure 3, the base band demodulating circuit of radio-frequency transmitter second preferred embodiment of the present invention comprises: analog-to-digital conversion module 301, matched filter 302, interpolation are recovered module 303, error-detecting module 304, loop filtering module 305 and withdrawal device 306.
Wherein, analog-to-digital conversion module 301 is identical with analog-to-digital conversion module 201, matched filter 202 in embodiment illustrated in fig. 2 with matched filter 302, no longer repeats here.
Interpolation is recovered module 303 and is linked to each other respectively with matched filter 302, error-detecting module 304, loop filtering module 305 and withdrawal device 306; It is according to the signal of timing error that receives from loop filtering module 305; The signal that receives from matched filter 302 is passed through the signal after linear interpolation produces an interpolation; Promptly recover N doubly to the over-sampling data of chip rate, export to error-detecting module 304 and withdrawal device 306 respectively.
Interpolation in the present embodiment is recovered module 303 and can be realized by a linear interpolation device.Through the signal after the linear interpolation than interpolation front signal more can with the coupling that transmits.Linear interpolation algorithm is confirmed by following formula:
r(n)＝z(n)*u+z(n-1)*(1-u)
0＜=u＜1st wherein, the signal of timing error that receives from loop filtering module 305.
Error-detecting module 304 also links to each other with loop filtering module 305 among Fig. 3, the signal that recovers module 303 receptions from interpolation is carried out timing error detect, and the timing error testing result is sent to loop filtering module 304.
In the present embodiment, error-detecting module 304 is for adopting the error detector of Gardner's algorithm.Certainly, also can adopt other similar algorithms, for example: sooner or later the door scheduling algorithm error detector.Gardner's algorithm the convergence speed is slower, but convergence precision is higher, and the random data that is suitable for usefulness carries out clock tracing to timing error.
Gardner's basic idea is: when not having timing error, the difference of adjacent two optimum sampling points and the product of mid-transition point are 0; When having timing error, this value is not equal to 0, is similar to door algorithm sooner or later, and the size of this value has reflected " distance " of current sample strip point and optimum sampling point, the positive and negative direction that departs from that reflected.The expression formula of Gardner algorithm computation timing error is:
e(k)＝(r((k-1)*N+b)-r(k*N+b))*r(k*N-N/2+b)
Wherein r representes that interpolation recovers the output signal of module 303, and k representes sampled point, and N representes that over-sampling rate T representes symbol period, and b representes the deviation of sampling.
Fig. 3 intermediate ring road filtration module 305 also links to each other with withdrawal device 306; Timing error testing result to receiving from error-detecting module 304 is carried out filtering; Obtain the stable timing error that comprises integer part and fractional part; Wherein fractional part is sent to interpolation as signal of timing error recover module 303, wherein integer part is sent to withdrawal device 306 as displacement d.
In the present embodiment, loop filtering module 305 loop filters are 1 rank finite impulse response filter of 1 Gain Adjustable, and expression formula can be written as
E(k)＝E(k-1)+a·e(k)
Wherein, E is the timing error testing result of error-detecting module output for accumulation timing error, e.0＜a＜1 is a time constant.A is big more, and E (k) is stable more, but convergence time is slow more.
Owing to adopted over-sampling, so timing error comprises integer part and fractional part.The value of integer part can increase along with the accumulation of timing error gradually, and the span of fractional part is between 0 to 1.The timing error of integer part converts the variation of withdrawal device extraction point position or the variation of interpolation device reference point location into, and fractional part has reflected treats the position of restore data between adjacent two sampled points.
Have the base band demodulating circuit of clock tracing function more than the employing, be used for the reception of DPMR signal, the error of tolerable 100ppm.And communication time does not receive 180 seconds restriction.
Utilize the result of base band demodulating circuit tracing transmitter base band of the present invention clock drift as shown in Figure 4.Wherein, abscissa is clock cycle T, and ordinate is the timing error testing result.In this example, transmitter and receiver clock relative error is 100ppm.The signal to noise ratio of baseband signal is 10dB.Testing time is 2 seconds, and during this period of time, the clock between the Receiver And Transmitter has differed two cycles.From Fig. 4, can find out, utilize the drift of the reception function track transmitter clock of clock tracing circuit.And then when sampling, compensate, thereby guarantee long reliable communicating.
In addition, several lines perpendicular to abscissa have also shown the place that the symbol error code takes place among Fig. 4.In this test, the final error rate is 0.17%, with the situation basically identical of no clock drift.
Visible by the above embodiments; The base band demodulating circuit of this radio-frequency transmitter of the present invention recovers the displacement d that module, loop filtering module and error-detecting module come to adjust at any time withdrawal device through interpolation; Thereby realized tracking, and then reduced the phenomenon that takes defeat that causes because of clocking error transmitter clock.
Claims (8)
1. the base band demodulating circuit of a radio-frequency transmitter comprises analog-to-digital conversion module, matched filter and withdrawal device, it is characterized in that: also comprise synchronous follow-up circuit;
Said synchronous follow-up circuit links to each other respectively with withdrawal device with matched filter; It carries out error-detecting to the signal that receives from matched filter, and according to the error-detecting result, the signal that receives is carried out the error adjustment; And obtain displacement d, adjusted signal and displacement d are sent to withdrawal device;
Withdrawal device is according to the displacement d that receives from synchronous follow-up circuit, to the signal extraction mark signal that receives from synchronous follow-up circuit.
2. base band demodulating circuit as claimed in claim 1 is characterized in that: saidly comprise according to circuit synchronously: interpolation is recovered module, error-detecting module and loop filtering module;
Said interpolation is recovered module and is linked to each other respectively with withdrawal device with matched filter, error-detecting module, loop filtering module; It is according to the signal of timing error that receives from the loop filtering module; The signal that receives from matched filter is passed through the signal after linear interpolation produces an interpolation, export to error-detecting module and withdrawal device respectively;
The error-detecting module also links to each other with the loop filtering module, the signal that recovers the module reception from interpolation is carried out timing error detect, and the timing error testing result is sent to the loop filtering module;
The loop filtering module also links to each other with withdrawal device; Timing error testing result to receiving from the error-detecting module is carried out filtering; Obtain the stable timing error that comprises integer part and fractional part; Wherein fractional part is sent to interpolation as signal of timing error recover module, wherein integer part is sent to withdrawal device as displacement d;
Withdrawal device is according to the displacement d that receives from the loop filtering module, to recovering the signal extraction mark signal that module receives from interpolation.
3. according to claim 1 or claim 2 base band demodulating circuit, it is characterized in that: described analog-to-digital conversion module is the analog-to-digital conversion module by following formula manipulation:
y(n)＝yt(nT/N)
Wherein: yt (t) is the analog signal that receives, and y (n) is the digital signal that sampling obtains on the time point of t=nT/N, T is-symbol interval, and N is an over-sampling rate.
4. according to claim 1 or claim 2 base band demodulating circuit, it is characterized in that: said matched filter adopts the receiving filter identical with emission filter, and it will send to interpolation recovery module from the signal that analog-to-digital conversion module receives.
5. base band demodulating circuit as claimed in claim 2 is characterized in that: said interpolation is recovered module and is realized by the linear interpolation device that adopts following interpolation algorithm:
r(n)＝z(n)*u+z(n-1)*(1-u)
0＜=u＜1st wherein, the signal of timing error that receives from the loop filtering module.
6. base band demodulating circuit as claimed in claim 2 is characterized in that: said error-detecting module is for adopting the Gardner's algorithm or the error detector of door algorithm sooner or later.
7. base band demodulating circuit as claimed in claim 6 is characterized in that: said error-detecting module is realized by the error detector that adopts following algorithm:
e(k)＝(r((k-1)*N+b)-r(k*N+b))*r(k*N-N/2+b)
Wherein r representes that interpolation recovers the output signal of module, and k representes sampled point, and N representes over-sampling rate, and T representes symbol period, and b representes the deviation of sampling.
8. base band demodulating circuit as claimed in claim 2 is characterized in that: said loop filtering module is realized by 1 rank IIR filter of the Gain Adjustable that adopts following formula manipulation:
E(k)＝E(k-1)+a·e(k)
Wherein, E is the timing error testing result of error-detecting module output for accumulation timing error, e, and 0＜a＜1 is a time constant.
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| CN111194077A (en) * | 2019-12-17 | 2020-05-22 | 北京航空航天大学杭州创新研究院 | Timing synchronization method under low sampling rate |
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Application publication date: 20121024 |