JPH01251971A - Digital waveform equalizing device - Google Patents

Abstract

PURPOSE:To correct a sampling phase in real time by sampling character multiplexing signals with frequencies (m) times as frequent as the transmission frequencies of the character multiplexing signals, separately adding respective sampled character multiplexing signals having the same sampling phase out of all the sampled character multiplexing signals with each other, and setting the sampling phase according to the added values. CONSTITUTION:The title device is composed of an input terminal 21, an A/D converting circuit 22, a delaying circuit 23, a sub-sampling circuit 24, a waveform equalizer 25, a decoder 26, an output terminal 27, a clock generating circuit 28, two successive multiplying circuits 29, a band-pass filter(BPF) 30, a synchronization adder circuit 31, and a comparing circuit 32. Further, the character multiplexing signals are converted into digital signals with sampling frequencies (m) ((m) is a positive integer equal to 2 or above) times as frequent as the transmission frequencies of the signals, respective plural converted outputs out of all the converted outputs, which are sampled with the same phase, are separately added with each other, and either of sampling outputs is selected according to the values of the two added outputs. Thus, a phase can be corrected in real time.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for digitally equalizing the waveform of a teletext signal superimposed on a television signal in a teletext receiver. This invention relates to a digital waveform equalization device.

(Prior Art) A teletext broadcasting receiver that receives a text multiplex signal superimposed on a television signal is generally provided with a waveform equalization device for waveform equalizing the text multiplex signal.

FIG. 5 shows the conventional configuration of this waveform equalization device.

The illustrated waveform equalization device is a digital waveform equalization device that converts a received character multiplex signal into a digital signal and equalizes the waveform.

In FIG. 5, an analog character multiplex signal supplied to an input terminal 11 is converted into a digital signal by an analog/digital conversion circuit (hereinafter referred to as an A/D conversion circuit) 12. This digital signal is waveform-equalized by a waveform equalizer 1j constituted by a transversal filter, for example, and then decoded by a decoder 14.

This decoded output is supplied to output terminal 15.

The sampling clock used in the A/D conversion circuit 12 is generated as follows. That is, the character multiplex signal supplied to the input terminal 11 is roughly supplied to the phase comparator circuit 16, where the phase is compared with the digital character multiplex signal output from the A/D conversion circuit 12. This comparison result is supplied to a clock generation circuit 17 that generates a sampling clock. According to the above comparison result, the clock generating circuit 17 generates a signal from the clock generating circuit 17 so that the phase of the character multiplexed signal supplied to the input terminal 11 and the character multiplexed signal output from the A/D conversion circuit 12 match. Controls the phase of the output sampling clock. As a result, a sampling clock having a phase that punches out the peak of the character multiplex signal is obtained.

Note that the phase comparison operation in the phase comparison circuit 16 is performed only during the superimposition period of a clock run-in signal (hereinafter referred to as a CRI signal). This is done by detecting the CRI signal from the character multiplex signal supplied to the input terminal 11 by the clock run-in detection circuit 18. 6th
The figure shows the CRI signal.

A conventional digital waveform equalization device has the above-mentioned configuration, but this configuration has the following problems.

(1) When the phase of a character multiplex signal changes, an appropriate sampling phase cannot be obtained for a certain period from the time of the change.

In the case of the configuration shown in FIG. 5, the phase of the sampling clock is controlled by an automatic phase control loop (hereinafter referred to as APC loop) consisting of a phase comparison circuit 16, a clock generation circuit 17, and an A/D conversion circuit 12. This is because an appropriate sampling phase can be obtained by this.

That is, in such a configuration, when the phase of the character multiplex signal changes, the sampling phase cannot be corrected immediately because the APC loop has a time constant.

As a result, for example, if the phase of a character multiplex signal changes for each superimposition line, the sampling phase of the character multiplex signal will deviate from the appropriate phase for a certain period after the superimposition line changes, and the quality of the digital signal will deteriorate. do.

(2) If the signal-to-noise ratio of the character multiplexed signal is poor or if waveform distortion occurs in the CRI section due to superimposition of a ghost signal, it may not be possible to obtain an appropriate sampling phase. As a result, the amount of distortion correction in the waveform equalizer 25 increases, and its equalization performance deteriorates.

This is because conventional digital waveform equalizers acquire new sampling phase correction information at predetermined intervals, separate from previous phase correction information, and are therefore directly affected by waveform distortion. be.

(Problems to be Solved by the Invention) As described above, in the conventional digital waveform equalization device, when the phase of the character multiplex signal changes, the sampling phase cannot be corrected in real time. There is a problem that the quality of the waveform equalized output deteriorates for a certain period after the phase of the character changes, and a problem that it is impossible to set an appropriate sampling phase when waveform distortion or the like occurs in the character multiplex signal.

Therefore, the present invention is capable of correcting the sampling phase in real time even if the phase of the text multiplex signal changes, and can reliably correct the sampling phase even if the signal to noise ratio of the text multiplex signal decreases or there is waveform distortion. An object of the present invention is to provide a digital waveform equalization device that can set an appropriate sampling phase.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention converts a received analog character multiplexed signal into a signal transmission frequency m (m is 2
a means for converting into a digital signal at a sampling frequency that is a positive integer on Li), extracting a signal component having the frequency of the clock run-in signal from the conversion output of this means, and extracting a signal component having the same sampling phase from the extracted output; Means for obtaining m summation outputs by adding the m summation outputs separately; and means for rate conversion.

(Function) As in the above configuration, the character multiplex signal is transmitted at m of its transmission frequency.
According to a configuration in which sampling is performed at twice the frequency, the sampling phases with the same sampling phase are added individually, and the sampling phase is set according to the magnitude, a time constant circuit like a conventional APC loop is not required. Therefore, even if the phase of the 0 character multiplex signal changes, the sampling phase can be corrected in real time.

In addition, among the digital conversion outputs, multiple ones with the same sampling phase are independently added together, and the sampling phase is corrected according to this addition output, so that the effects of phase distortion etc. are avoided on the m addition outputs. Since it occurs randomly and does not have to be limited to the CR1 portion, it is possible to perform phase correction without being affected by noise, waveform distortion, etc.

(Example) Hereinafter, an example of this method will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention, and FIG. 2 is a signal waveform diagram showing signal waveforms at various parts in FIG.

In FIG. 1, 21 is an input terminal to which a received analog character multiplex signal is supplied. The character multiplexed signal supplied to this input terminal 21 is supplied to an A/D conversion circuit 22 and converted into a digital signal S1 in accordance with a sampling clock having a frequency twice the signal transmission frequency. This digital signal S1 is shown in FIG. 2(a).

This digital signal S1 is delayed by a predetermined time in a delay circuit 23 and then supplied to a sub-sampling circuit 24. Then, it is subsampled by this subsampling circuit 24,
It is converted to a signal with the same transmission rate as the text multiplex signal. The output of this sub-sampling circuit 25 is waveform-equalized by a waveform equalizer 26 and then decoded by a decoder 26. This decoded output is supplied to the output terminal 27.

The sampling clock of the A/D conversion circuit 22 consists of a clock generation circuit 28 that generates a clock having the same frequency as the transmission frequency of the character multiplexed signal, and a clock generation circuit 28 that generates a clock having the same frequency as the transmission frequency of the character multiplex signal.
The output clock is generated by a 2× multiplier circuit 29 that doubles the output clock.

The output of the A/D conversion circuit 22 is further supplied to a band pass filter (hereinafter referred to as BPF) 30. This 13PF31 extracts a signal component having the same frequency as the CRI signal from the input signal. This extracted output S2 is
Shown in Figure (b).

This extracted output S2 is subjected to synchronous addition after its absolute value is taken by a synchronous addition circuit 31. As a result, the synchronous addition circuit 31 obtains two addition outputs in which the sampling phases having the same sampling phase are separately added. Figure 2 (C)
shows the absolute value output S3 of the extracted output S2.

Two addition outputs outputted from the synchronous addition circuit 31 are compared in magnitude by a comparison circuit 32. This comparison result is supplied to the sub-sample circuit 24.

This sub-sample circuit 24, according to this comparison result,
Select the digital signal sampled at the larger phase of the summation output. As a result, the sub-sample circuit 24
, a digital signal sampled at the appropriate sampling phase is selected.

In the example of FIG. 2, two digital signals "O" are sampled at different sampling phases.

Among the "x"s, the added value of the digital signal rOJ is larger, so this digital signal rOJ is selected.

The delay circuit 23 is a circuit for time-aligning the digital character multiplexed signal supplied to the sub-sampling circuit 24 and the output of the comparison circuit 32.

FIG. 3 is a circuit diagram showing an example of the specific configuration of FIG. 1.

In FIG. 3, the sub-sample circuit 24 consists of three latch circuits 241, 242, 243 and a selection circuit 244. The latch circuit 241 latches all two digital signals rOJ and rXJ, if explained with reference to FIG. Of these, the latch circuit 242 latches the digital signal "0", and the latch circuit 243 latches the digital signal rXJ. The selection circuit 244 performs rate conversion of the digital signal by selecting one of the two latch outputs according to the comparison result of the comparison circuit 32.

The BPF 30 consists of two latch circuits 301 and 302 and a subtraction circuit 303, and extracts a signal component having the frequency of the CRI signal according to the passband characteristic x 1 expressed by the following equation (1).

X, = 1-Z'″2 ・・・・・・(1
) The synchronous addition circuit 31 includes an absolute value circuit 311 and an addition circuit 3.
12. It consists of two latch circuits 313 and 314, and performs synchronous addition according to the addition characteristic x 2 expressed by the following equation (2).

This embodiment described in detail above has the following effects.

(1) The phase of the character multiplex signal changes and the sampling phase can be corrected in real time.

This converts a character multiplexed signal into a digital signal at a sampling frequency twice the transmission frequency, adds multiple samples of the converted outputs sampled at the same phase, and then calculates the magnitude of the two added outputs. This is because one of the sampling outputs is selected depending on the situation. In other words, in such a configuration, the conventional APC
Since there is no need for a time constant circuit such as a loop that causes a delay in sampling phase correction, real-time phase correction becomes possible.

(2) An appropriate sampling phase can be obtained even if the signal-to-noise ratio of the character multiplexed signal deteriorates or the waveform is distorted by a ghost signal. Thereby, it is possible to reduce the amount of distortion correction in the waveform equalization amount 25, and it is possible to perform a stable waveform equalization operation.

This is because when comparing the magnitude of digital signals with different sampling phases, the sum of multiple signals with the same sampling phase is compared, so effects such as waveform distortion occur randomly on the two comparison targets. This is because, as a result, comparisons can be made without being affected by noise, waveform distortion, etc.

(3) Appropriate sampling phase can be obtained even during black and white television broadcasting without color burst signals.

This is because there is no need to consider the phase of the sampling clock, so there is no need to lock it to the color burst signal.

One embodiment of the present invention has been described above, but in the same configuration as this, if the frequency of the sampling clock is made an integral multiple of three or more times the transmission frequency of the character multiplexed signal, the accuracy of the obtained sampling phase can be further improved. Can be done.

FIG. 3 is a circuit diagram showing the configuration of another embodiment of the invention.

In this embodiment, instead of increasing the frequency of the sampling clock, linear interpolation is performed using two digital signals sampled at different sampling phases to obtain a digital signal with an appropriate sampling phase. be.

That is, in FIG. 4, 41 is a linear interpolation circuit. The linear interpolation circuit 41 performs linear interpolation using the two sampling outputs output from the delay circuit 23 to obtain a sampling output with an appropriate sampling phase. The interpolation coefficient in this case is output from the interpolation coefficient calculation circuit 42 according to the magnitude of the two addition outputs output from the synchronous addition circuit 31.

In this case, the addition process of the synchronous addition circuit 31 is performed only during the superimposition period of the CRI signal according to the detection output of the clock run-in detection circuit 42 which detects the CRI signal from the character multiplexed signal supplied to the input terminal 21.

With such a configuration, it is possible to always obtain the optimum sampling phase that punches out the peak of the character multiplex signal. However, the magnitude of the obtained digital signal is different from the peak value of the character multiplex signal, but this can be corrected by passing this digital signal through the waveform equalizer 25.

Furthermore, in this embodiment, since the period in which the synchronous addition is performed is limited to the period in which the CRI signal is superimposed, it is possible to obtain a sampling phase with higher precision than in the case where the period is not limited.

Note that this invention is not limited to the previous embodiments.

For example, as a data interpolation method, methods other than linear interpolation may be used.

Further, methods other than sub-sampling and data interpolation may be used as a method for converting the rate of a digital signal so as to obtain an appropriate sampling phase.

[Effects of the Invention] As described above, according to the present invention, even if the phase of the character multiplex signal changes, the sampling phase can be corrected in real time, and the SN ratio of the character multiplex signal decreases. Even if there is distortion due to ghost signals, etc., an appropriate sampling phase can be reliably set.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
1 is a signal waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a circuit diagram showing an example of the specific configuration of FIG. 1, and FIG. 4 is a circuit diagram showing the configuration of another embodiment of the present invention. 5 is a circuit diagram showing the configuration of a conventional digital waveform equalization device, and FIG. 6 is a signal waveform diagram showing the data structure of a character multiplex signal. 21--input terminal, 22--A/D conversion circuit, 23
...Delay circuit, 24...Subsample circuit, 25.
... Waveform equalizer, 26 ... Decoder, 27 ... Output terminal, 28 ... Clock generation circuit, 29 ... Double multiplier circuit, 30 ... BPF, 31 ... Synchronous addition circuit, 3
2... Comparison circuit, 41... Linear interpolation circuit, 42...
- Interpolation coefficient calculation circuit, 43...CRI detection circuit.

Claims (1)

[Claims] Analog/digital conversion means for converting a received analog character multiplexed signal into a digital signal at a sampling frequency m (m is a positive integer of 2 or more) times the transmission frequency of the received analog character multiplexed signal; A signal extraction means for extracting a signal component having the frequency of the clock run-in signal from the conversion output of the digital conversion means; and m an addition means for obtaining m addition outputs, and a conversion output of the analog/digital conversion means, which has a transmission frequency of the character multiplex signal and has an appropriate phase, according to the magnitude of the m addition outputs obtained from the addition means. A digital waveform equalization device comprising: rate conversion means for converting the rate into a signal sampled by the rate conversion means; and waveform equalization means for waveform equalizing the converted output of the rate conversion means.