JP2518520B2 - Demodulation method and demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation method and demodulator applied to a digital radio transmission system.

[0002]

2. Description of the Related Art Conventionally, a demodulator of this type has a structure as shown in the block diagram of FIG. In this demodulator, the modulated wave of the analog input signal input from the signal input terminal IN is multiplied by the first reproduced carrier wave input from the local oscillator input terminal 100 in the multiplier 1, while the local oscillator input terminal 200 And is also multiplied by the second reproduction carrier having a phase difference of 90 degrees with respect to the first reproduction carrier in the multiplier 2. The modulated outputs from the multipliers 1 and 2 are low pass filters 3 and 4, respectively.
After passing through, it becomes demodulated baseband signals a and b.

Here, the multipliers 1, 2 and the low-pass filter 3,
Reference numeral 4 indicates a demodulation baseband signal a, b by filtering and demodulating an analog input signal with a reproduced carrier wave, and therefore may be collectively referred to as a demodulation circuit. The demodulated baseband signals a and b are respectively amplified by amplifiers 5 and 6 to have appropriate amplitudes, and analog / digital converters (A / D) 9 and
It is converted into a digital signal by 10. These digital signals are equalized by a decision feedback equalizer (DFE) 13 for waveform distortion due to fading or the like, and the equalized outputs are output from the output terminals OUT1 and OUT2, respectively.

By the way, the demodulated baseband signals a and b amplified and output by the amplifiers 5 and 6, respectively, have their clock components extracted by the clock component extraction circuit 11 through the nonlinear circuits 7 and 8, respectively. The clock component extraction circuit 11 is composed only of a bandpass filtering function. This clock component is a clock synchronization circuit (PLL)
The demodulated clock input to 12 and synchronized with this clock component is sent from the clock synchronization circuit (PLL) 12 to the analog / digital converters (A / D) 9 and 10.

Incidentally, a technique related to such a demodulator has two pilot channels for detecting a phase shift and a frequency shift in addition to the data channel, and an automatic equalizer connected to the data channel is provided. A timing synchronization method for averaging a product of a difference between two tap coefficients adjacent to a center tap and a center tap coefficient is used as timing phase shift information, and timing synchronization is performed by using this timing phase shift information. 60-5214
No. 7, the received signal is demodulated, the output phase of the roll-off filter operation in which the tap coefficient is set is changed, the waveform is shaped, and the timing of the received signal is determined based on the determination result of the extracted timing component. Japanese Patent Laid-Open No. 61-82545 discloses a timing pulling method for synchronizing the phase of a signal and a baud rate clock.

[0006]

In the case of the demodulator described above, interference is generated due to fading, and for example, FIG.
As shown in, the fading notch frequency f _N in the modulation spectrum is from the center frequency f _C to f of the carrier frequency f.
_When it is at f _C + f _o / 2 [Hz], which is _O / 2 (f _o is the modulation speed frequency in the modulation spectrum), the level of the clock component extracted from the baseband signal is as shown in FIG. descend. As a result, the clock synchronization is deviated although the equalization capacity has a margin.

The present invention has been made to solve such a problem, and its technical problem is to provide a demodulation method capable of maintaining good synchronization without causing clock deviation even if interference occurs due to fading. And to provide a demodulator.

[0008]

According to the present invention, a clock extracted by demodulating an analog input signal by a reproduced carrier, band-pass-limited to obtain a demodulated baseband signal, and nonlinearly processing the demodulated baseband signal. In a demodulation method of converting the demodulation baseband signal into a digital signal based on a demodulation clock synchronized with the component, equalizing the digital signal and outputting the digital signal, the demodulation baseband signal is delayed and combined to generate a clock. When a frequency component is extracted and a demodulation component clock synchronized with the clock frequency component is used as a sampling clock signal and the demodulation baseband signal is converted into a digital signal , among tap coefficients used for equalization processing of the digital signal Maximum coefficient
A demodulation method including a control step for controlling the variable delay amount of the combined output based on the tap coefficient taking

Further, according to the present invention, a demodulation circuit for filtering and demodulating an analog input signal by a reproduced carrier wave and outputting a demodulation baseband signal, a nonlinear circuit for nonlinearly processing the demodulation baseband signal, and a nonlinearly processed signal Clock component extraction circuit for extracting a clock component from the clock, a clock synchronization circuit for outputting a demodulation clock synchronized with the clock component, an analog / digital converter for converting the demodulation baseband signal into a digital signal based on the demodulation clock, and a digital In a demodulator including an equalizer for equalizing a signal, a clock component extraction circuit has a fixed delay circuit for fixedly delaying a non-linearly processed signal and a variable delay for variably delaying a demodulated baseband signal. Circuit, an amplitude controller for controlling the amplitude of the delay output of the variable delay circuit, and a fixed delay circuit and an amplitude controller A combiner that obtains a combined output formed by combining the outputs, an extraction device that extracts a clock component from the combined output, an amplitude controller and a variable delay circuit based on the tap coefficient included in the equalized output of the equalizer. A demodulator having a controlling clock equalization controller is obtained.

Further, according to the present invention, in the demodulator, the extraction device includes a bandpass filter for extracting a clock frequency component from the combined output, and the clock synchronization circuit has a demodulation component clock synchronized with the clock frequency component. The analog-to-digital converter converts the demodulated baseband signal into a digital signal using the demodulated component clock as a sampling clock signal, and the clock equalization controller controls the output amplitude ratio of the amplitude controller and the fixed delay circuit. A demodulator is obtained which controls the amplitude controller to be equal to the ratio of the maximum tap coefficient and the center tap coefficient of the equalizer.

[0011]

The demodulator of the present invention is provided with a clock equalization controller for selecting the tap having the maximum tap coefficient from the taps of the decision feedback equalizer. This clock equalization controller is composed of an amplitude controller that controls the output amplitude of a variable delay circuit that variably delays a demodulation baseband signal, and a ratio of the output amplitude of a fixed delay circuit that delays the demodulation baseband signal fixedly. The amplitude controller is controlled so that is equal to the ratio of the maximum tap coefficient and the center tap coefficient of the equalizer. As a result, the delay of the variable delay circuit is controlled to be equal to the delay at the maximum coefficient tap, and the clock component included in the demodulated baseband signal is sufficiently equalized, so clock synchronization is maintained even under fading. Be done.

[0012]

The demodulation method and demodulator of the present invention will be described in detail below with reference to the accompanying drawings. First, the outline of the demodulation method of the present invention will be briefly described.

According to this demodulation method, a demodulation method of a conventional demodulator, that is, a demodulated baseband signal obtained by demodulating an analog input signal by a reproduction carrier and then band-pass-limited is synchronized with a clock component extracted by nonlinear processing. In the method of equalizing and outputting the digital signal obtained by digitally converting the demodulation baseband signal based on the demodulation clock, the synthesized output is obtained by delaying the demodulation baseband signal fixedly or variably. When a clock frequency component is extracted from the demodulation component clock that is synchronized with this clock frequency component and is used as a sampling clock signal and the demodulation baseband signal is converted into a digital signal,
Of the tap coefficients used for digital signal equalization,
Yes combined output based on the tap coefficient to take the maximum of the coefficient of
A control step for controlling the variable delay amount is included.

Therefore, a specific description will be given with reference to a block diagram of a demodulator according to an embodiment of the present invention shown in FIG. 1 in which this demodulation method is introduced. However, in the basic configuration of this demodulator, the same parts as those of the demodulator described with reference to FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted. Only the different parts will be described.

That is, this demodulator also has the components shown in FIG. 5, namely, the signal input terminal IN, the local oscillator input terminal 100,
200, a demodulation circuit including multipliers 1 and 2 and low-pass filters 3 and 4, amplifiers 5 and 6, and non-linear circuits 7 and 8
A clock component extraction circuit 11 ', analog / digital converters (A / D) 9 and 10, and a clock synchronization circuit (P
LL) 12 and a decision feedback equalizer (D FE ) 13 are provided. Here, the clock component extraction circuit 11 'will be described below.

The clock component extraction circuit 11 'is a fixed delay circuit (τ which delays the demodulated baseband signal in a fixed manner).
₀ ) 14, a variable delay circuit (τ) 15 that variably delays the demodulated baseband signal, and the variable delay circuit (τ) 1
Amplitude controller (voltage-controlled attenuator) that controls the output amplitude of 5
16, a fixed delay circuit (τ ₀ ) 14 and an amplitude controller 16
17 for obtaining a combined output from the bandpass filter 1 as an extracting device for extracting a clock component from the combined output
8 and a clock equalization controller 19 that controls the amplitude controller 16 and the variable delay circuit (τ) 15 based on the tap coefficient included in the equalization output of the decision feedback equalizer (D FE ) 13. I have it.

In the case of this demodulator, the outputs of the non-linear circuits 7 and 8 are the fixed delay circuit (τ ₀ ) 14 and the clock equalization controller 1.
And a variable delay circuit (τ) 15 controlled by 9 respectively. The output of the variable delay circuit (τ) 15 is given an appropriate amplitude by the amplitude controller 16, and then the combiner 17
Is added to the output of the fixed delay circuit (τ ₀ ) 14 to obtain a combined output.

Further, in the case of this demodulator, when the demodulated signal is distorted due to fading, the decision feedback equalizer (DE
F) Each tap coefficient of 13 corrects the distortion of the signal,
It changes corresponding to the amount of the signal delayed by the delay of each tap included in the signal component. Usually, in order to converge the signal points are needed all the tap information, demodulated base to extract the clock component in the band f _C + f _O / 2 where f _O / 2 away from the center frequency f _C is It is only necessary to be able to equalize the deep notch in the part apart by [Hz]. Therefore, in the present embodiment, the equalization process is performed only on the tap having the largest contribution among the taps.

For example, the delay at the center tap of the decision feedback equalizer (DFE) 13 is T _O , and the tap coefficient is C _O.
If the tap having the maximum tap coefficient is the M-th tap and the tap coefficient of the tap M is C _M , the fixed delay circuit (τ ₀ ) 14 outputs T _{O to} the outputs of the nonlinear circuits 7 and 8. Give a delay.

The clock equalization controller 19 monitors the tap coefficient in the decision feedback equalizer (DFE) 13, detects the tap M having the maximum tap coefficient, and as a result, based on the information on the delay amount at the tap M. Variable delay circuit (τ)
As the delay amount output by the 15 becomes T _O + MT, variable delay circuit (tau) controls one 5. That is, here, the clock equalizer controller 19 determines that the ratio of the output amplitudes of the amplitude controller 16 and the fixed delay circuit (τ ₀ ) 14 is the decision feedback equalizer (DF).
E) The amplitude controller 16 is controlled so as to be equal to the ratio of the maximum tap coefficient of 13 and the center tap coefficient.

FIG. 2 shows an example of the variable delay circuit (τ) 15. Here, the demodulated baseband signals a and b that have passed through the nonlinear circuits 7 and 8 are input to the input terminal IN. The demodulated baseband signals a and b input from the input terminal IN pass through a plurality of delay circuits each having a delay of one clock as illustrated, and the outputs of the delay circuits are input to the multiplexer. However, the output of each delay circuit corresponds to the delay amount of each tap. The multiplexer outputs the control signal from the clock equalization controller 19 to the CO
By inputting from the NT terminal, an input having a delay amount of T _O + TM is selected and then output to the amplitude controller 16.

FIG. 3 is shown for explaining the relationship between the tap coefficient and the clock equalizer constant. FIG. 3A shows a configuration example of the decision feedback equalizer (DFE) 13, and FIG. b) is an example of comparison processing of each tap coefficient, and FIG. 7C is an example of setting the clock equalizer constant.

Here, the decision feedback equalizer (DFE) 13 is used.
Of the respective tap coefficients C _-N , C _{-N + 1} , ..., C _O , C _M , C _{+ N} including corresponding elements of the delay amounts T _O , T _M , and T _N are compared by the clock equalization controller 19. , And the delay amount T _O + TM, the clock equalization controller 19 sets the ratio of the output of the amplitude controller 16 to the output of the fixed delay circuit (τ ₀ ) 14 to C _M / C _O. It has shown that it controls. As a result, the output of the amplitude controller 16 and the fixed delay circuit (τ ₀ ) 1
The output of No. 4 and the output of No. 4 are combined by the combiner 17, and the clock component in the demodulated baseband signal can be equalized.

FIG. 4 (a) shows the compression output (signature) characteristic of this demodulator at the time of fading interference in comparison with the conventional one shown in FIG. 4 (b).
However, the MP region in the figure shows a region where the relation "amplitude of delayed wave <amplitude of main wave" is established, and the NMP region shows a region where the relation "amplitude of delayed wave> amplitude of main wave" is established. . 4A and 4B, in the case of the demodulator of this embodiment, the output characteristic line appears in the NMP region at the notch depth D _N regardless of the notch frequency f _N. , In the conventional demodulator, the output characteristic line has a notch depth D _N.
It can be seen that it is expressed in both the NMP region and the MP region. As a result, the demodulator of this embodiment can maintain good clock synchronization even if the clock component in the demodulated baseband signal is distorted due to fading.

[0025]

As described above, according to the present invention, according to the present invention, a clock component in the demodulated baseband signal when the notch frequency of the fading away f _0/2 [Hz] from the center frequency of the carrier frequency interference A demodulation method and a demodulator that do not cause synchronization deviation even when receiving a signal are obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a demodulator according to an embodiment of the present invention.

2 shows an example of a variable delay circuit provided in the demodulator shown in FIG.

3A and 3B are diagrams for explaining a relationship between a tap coefficient and a clock equalizer constant in the demodulator shown in FIG. 1, and FIG. 3A is a configuration of a decision feedback equalizer included in the demodulator. FIG. 6B is an example of comparison processing of each tap coefficient, and FIG. 7C is an example of setting a clock equalizer constant.

4A is a compression output characteristic at the time of fading interference in the demodulator shown in FIG. 1, and FIG. 4B is a compression output characteristic at the time of fading interference in the conventional demodulator.

FIG. 5 is a block diagram showing a conventional demodulator.

6A shows a modulation spectrum in a state in which a notch frequency deviates from a center frequency of a carrier frequency at the time of interference due to fading of the demodulator shown in FIG. 5, and FIG.
Shows the level fluctuation of the extracted clock component at that time.

[Explanation of symbols]

1, 2 Multiplier 3, 4 Low-pass filter 5, 6 Amplifier 7, 8 Non-linear circuit 9, 10 Analog / digital converter (A / D) 11, 11 'Clock component extraction circuit 12 Clock synchronization circuit (PLL) 13 Decision Feedback Equalizer (DFE) 14 Fixed Delay Circuit (τ ₀ ) 15 Variable Delay Circuit (τ) 16 Amplitude Controller (Voltage Control Attenuator) 17 Combiner 18 Bandpass Filter 19 Clock Equalization Controller 100, 200 stations input terminal

Claims (3)

(57) [Claims] 1. A demodulation baseband signal is obtained by demodulating an analog input signal by a reproduced carrier wave after band-pass filtering, and the demodulation baseband signal is subjected to a non-linear processing to obtain a demodulation baseband signal. In a demodulation method of converting a demodulated baseband signal into a digital signal, equalizing the digital signal and outputting the digital signal, a clock frequency component is extracted from a combined output obtained by delaying and combining the demodulated baseband signal, and the clock frequency When the demodulated baseband signal is converted into the digital signal by using the demodulation component clock synchronized with the component as the sampling clock signal, the tap coefficient that takes the maximum coefficient among the tap coefficients used in the equalization processing of the digital signal is used. characterized <br/> include control step of controlling the variable delay amount of the synthetic output based Way tone. 2. A demodulation circuit for filtering and demodulating an analog input signal with a reproduced carrier wave to output a demodulation baseband signal, a nonlinear circuit for nonlinearly processing the demodulation baseband signal, and a clock component from the nonlinearly processed signal. A clock component extracting circuit for extracting, a clock synchronizing circuit for outputting a demodulated clock synchronized with the clock component,
In a demodulator including an analog / digital converter that converts the demodulated baseband signal into a digital signal based on the demodulated clock, and an equalizer that equalizes the digital signal, the clock component extraction circuit includes: A fixed delay circuit for fixedly delaying the non-linearly processed signal,
A variable delay circuit that variably delays the demodulated baseband signal, an amplitude controller that controls the amplitude of the delay output of the variable delay circuit, and a combination of both outputs of the fixed delay circuit and the amplitude controller. A combiner that obtains a combined output, an extraction device that extracts the clock component from the combined output, and controls the amplitude controller and the variable delay circuit based on tap coefficients included in the equalized output of the equalizer. And a clock equalization controller for controlling the demodulator. 3. The demodulator according to claim 2, wherein the extraction device includes a bandpass filter that extracts a clock frequency component from the combined output, and the clock synchronization circuit includes:
A demodulation component clock that is synchronized with the clock frequency component is generated, and the analog / digital converter converts the demodulation baseband signal into a digital signal using the demodulation component clock as a sampling clock signal, and the clock equalization controller A demodulator which controls the amplitude controller so that the ratio of the output amplitudes of the amplitude controller and the fixed delay circuit becomes equal to the ratio of the maximum tap coefficient and the center tap coefficient of the equalizer.