GB2165110A

GB2165110A - Multiplex data receiver with improved timing phase control apparatus

Info

Publication number: GB2165110A
Application number: GB08522219A
Authority: GB
Inventors: Hidehito Aoyagi
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1984-09-06
Filing date: 1985-09-06
Publication date: 1986-04-03
Also published as: GB2165110B; GB8522219D0

Abstract

A multiplexed signal received at a terminal (10) is digitized by a sampler (1) and applied to a demodulator. The individual baseband signals are equalized in power by AGC amplifiers (4A-4N) controlled by power level detectors (5A-5N) producing power level signals PA-PN). The signals are then applied to adaptive transversal equalizers (DA-DN) which produce deviation signals (DA-DN) indicating on a channel-by-channel basis the phase error in the sampling signal applied to the sampler (1) by a VCO(2) which is controlled by a frequency control circuit (8). In order to ensure that this circuit acts only on the basis of information from good channels, a selection circuit selects from the deviation signals (DA-DN) only those whose power level signals (PA-PN) are above a given threshold. The control circuit (8) averages the selected deviation signals to provide the control signal for the VCO(2). Various alternatives for deriving and selecting the deviation signals are disclosed. <IMAGE>

Description

SPECIFICATION Multiplex data receiver with improved timing phase control apparatus The present invention relates to a data receiver for a transmission system employing a plurality of parallel channels, and more specifically to improvements in a timing phase control apparatus used in the receiver.

Multiplexed parallel transmission systems have been widely employed. In such transmission systems, various distortions and deviations, such as phase and amplitude distortions and a sampling, timing phase deviation, are absorbed or compensated by an equalizer such as transversal filter, so that the data can be correctly demodulated. As a compensating system for the timing phase deviation, there has heretofore been employed a timing synchronization system which controls the oscillation frequency of a voltage-controlled oscillator (VCO) to optimized the sampling timing phase on the basis of a timing phase deviation data obtained by the equalizer according to the following principle. That is, the distribution of tap coefficient (weight ocefficient) values of the transversal filter expresses the impulse response of the transversal filter.

The timing phase deviation makes a tap position giving a maximum coefficient value deviate from the central tap position. Therefore, in the above system, the timing phase deviation data is detected from the change in tap coefficient value, and the voltage-controlled oscillator is so controlled that the maximum coefficient value is located at the central tap position at all times. According to GOTTFRIED UNGERBOEK, for example, the deviation of the tap position giving the maximum tap coefficient is detected by comparing the sum of squared powers of coefficients of the input side and that of the output side with the central tap as a boundary, and the tap coefficients are finely adjusted so that there is no imbalance between the two sums of the squared powers.The details are disclosed in a paper "Fractional Tap-Spacing Equalizer and consequences for Clock Recovery in Data Modems", IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.

COM-24, NO. 8, AUGUST, 1976, pp. 856-864.

In a conventional timing synchronizing system, the timing phase deviation data obtained only from predetermined channels are exclusively used for timing control. The predetermined channels are usually such a channel that the least deterioration is expected and channels around it. Thus, the tap coefficients of all channels are controlled always based upon thus obtained timing phase deviation data. In the shortwave transmission system, however, unexpected selective fading or radio interference may seriously deteriorate the above-mentioned predetermined channels. Therefore, if the timing synchronization is performed based upon the timing phase deviation data of low accuracy (small S/N ratio) obtained from the thus deteriorated channels, a proper equalization operation is not expected. This causes error in the demodulated data and non-synchronism.

SUMMARY OF THE INVENTION The object of the present invention is, therefore, to provide a timing phase conrol apparatus capable of establishing and maintaining timing synchronism stably even when the transmission channels are deteriorated by the selective fading.

The present invention is featured by monitoring the quality of each of all the channels or a plurality of the predetermined channels to select the best channel, that is, the channel having the best quality, or one or a plurality of the channels whose quality is allowable, and controlling the sampling frequency by the timing phase deviation value of the selected channel or by a mean value of the timing phase deviation values of the selected channels. One example of indexes representing the quality of the channel is the power of the demodulated baseband signal of that channel, and another example is the decision error power produced by the adaptive equalizer of that channel. These quality indexes represent, in other words, the amount of degradation which the signal of each channel has been subjected to on the transmission line.Therefore, the selected channel or channels has the least amount of degradation or the allowable (small) amount of degradation. By employing the timing phase deviation value or values of the channel or channels which has been subjected to no degradation or a small degradation, the sampling frequency can be properly controlled.

Other objects and features of the invention will be clarified from the following description with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a multiplexed parallel transmission system on the receiving side according to an embodiment of the present invention; Figure 2 is a block diagram showing in detail a timing phase control signal selecting circuit 7 and a frequency control circuit 8 shown in Figure 1; Figures 3 and 4 are diagrams illustrating concrete circuits of an equalizer shown in Figure 1; Figures Sand 6 are diagrams explaining the extracting of timing phase deviation data by the equalizer shown in Figure 4; and Figure 7 is a block diagram showing a multiplexed parallel transmission system on the receiving side according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figure 1, transmitted signals are received and applied to an input terminal 10 and the received signals are sampled, quantized, and converted into digital signals by a sampling circuit 1. timing clock signal for sampling is generated by an oscillator (such as voltage-controlled oscillator: VCO) 2 and applied to the sampling circuit 1. The frequency of the timing clock signal, that is the sampling frequency at the sampling circuit 1, is controlled by a signal from a frequency conrol circuit 8.A demodulator 3 receives the digital signals from the sampling circuit 1, demodulates baseband signals of the respective channels, and sends the demodulated signals to the corresponding automatic gain control amplifiers (AGC's) 4A, 4B, 4C, -----, , 4N and to power detectors 5A, 5B, 5C, -----, 5N that detect the power of each channel baseband signal, and generate power signals PA to PN. The power signals PA to PN are applied to the amplifiers 4A to 4N, respectively, and to a timing phase control signal selecting circuit 7. The gain of each of the amplifiers 4A to 4N is controlled by each of the power signals such that its output may be constant. The thus produced constant outputs of the amplifiers 4A to 4N are then supplied to corresponding automatic equalizers (AEO's) 6A, 6B, 6C, -----, 6N.As is well known, the automatic equalizers SAto 6N are of the transversal type. They equalize amplitude distortion, phase distortion and interchannel interference which the respective channel bands have been, subjected to in transmission and produce the equalized outputs of the respective channels from the output terminals CHA, CHB, CHC, -----, CHN.

Some or all of these transversal-type automatic equalizers 6A to 6N further have extracting circuits to extract the timing phase deviation data from the tap coefficients. The data DA, DB, Dc, , DN of timing phase deviations produced from the extracting circuits are sent to the timing phase control signal selecting circuit 7.

The timing phase control signal selecting circuit 7 is provided with baseband power signals PA to PN of all the channels in this embodiment (or a plurality of channels determined beforehand) detected by the power detectors 5A to 5N, and selects a suitable channel or channels based upon the power signals as mentioned below. Figure 2 is a diagram showing in detail the circuit 7. The power signals PAto PN are compared with a predetermined allowable voltage in comparator circuits 71A, 71 B, 71 C, -----, 71 N. When the baseband signal power is greater than the allowable voltage, the comparator judges that the channel is deteriorated in transmission, and outputs a switching signal to the corresponding switch out of the switches 72A, 72B, 72C, -----, 72N.First ends of the switches 72A to 72N are input ends of the circuit 7 for receiving the data DA to DN from the equalizers 6A to 6N and the other ends are coupled to an adder 81. When the baseband power signal is greater than the allowable value, the corresponding switch is closed in response to the switching signal, while the corresponding switch is opened when the baseband signal power is smaller than the allowable voltage. Thus, the signal selecting circuit 7 selects or extracts the timing phase deviation data from channels that are deteriorated relatively little. The extracted timing phase deviation signals are supplied to the adder 81 of a frequency control circuit 8, where the thus extracted signals are added up together and amplified by an amplifier 82.The gain of the amplifier 82 varies responsive to the number of the switching signals produced by the comparator circuits 71A to 71 N. Namely, the adder 81 and the amplifier 82 constitute an averaging circuit which generates an average value of timing phase deviation of the selected channels as a frequency control signal for the oscillator 2. By this frequency control signal, the sampling frequency in the sampling circuit 1 is controlled.

According to the present invention as described above, the amounts of deterioration of the respective channels are monitored by detecting the baseband signal powers of predetermined channels (all the channels in the embodiment shown in Figure 1) to select the channel or channels that are deteriorated little, and the timing is controlled on the basis of the timing phase deviation data of the selected channel or channels only. Therefore, the timing phase deviation data from a channel where the selective fading is taking place is neglected, and the appropriate timing is stably maintained at all times.

In the above-mentioned embodiment, the appropriate channels generating the timing phase deviation data are selected based upon the baseband signal powers of the channels. The appropriate channels, however, can be selected based upon other signal parameters such as a demodulated signal level. Namely, when a demodulated signal level is within a predetermined range around a standard level, i.e., the demodulated signal level is close to the standard level, the channel generating the demodulated signal can be selected, where the standard level is defined by a demodulated signal level underthe condition that no problem occurs on the transmission line.

In the embodiment, the signal powers of all the channels are monitored. However, the monitored channels may not be all of the channels but a part thereof which is relatively hardly subjected to deterioration on the transmission line. In usual, the channel in the central portion of the transmission band and the channels therearound are predetermined to be monitored. Moreover, the selected channel may be only one which has the best signal power or the signal power nearest the standard level.

Figure 3 shows a circuit for extracting the timing phase deviation data provided in the transversal-type automatic equalizers 6A to 6N of Figure 1. This circuit extracts as the timing phase deviation data the difference between the sum of squared powers of tap coefficients of the input side and that of the output side with the central tap as a boundary. Specifically, a demodulated signal is sent to a first-stage register 601 and to a multplier 610. The demodulated signal is multiplied in the multiplier 610 by a coefficient CM N determined by a known tap coefficient setter (not shown), and is then sent to an adder 620.The demodulated ;signal is further delayed by a predetermined time period (one-half the sampling period Tin this embodiment) through the register 601, multiplied in a multiplier (not shown) by a coefficient CM.N1, and is sent to the adder 620. The registers 602,603 and 604 have the same function as the register 601. Further, the registers 601 to 604 are constituted by shift registers of (2N+1) stages with taps. The multipliers 611,612, 613, 614 have the same function as the multiplier 610, and operate to multiply the signals by tap coefficients CMi, CM, CM+1, Chn +1, CMN. Outputs of the multipliers 611 to 614 are supplied to the adder 620. The adder 620 generates the equalizer output. Here, the multiplier 612 is used for multiplying a central tap coefficient CM.

The tap coefficients CMN, , CM-i, CM, CM1, , CMN supplied to the multipliers 610, ,611,612, 613,-----,614 are raised to the second power respectively by the multipliers 603, -----,631,632,633, ,634.

With the position of central tap as a boundary, the sum of squared powers of tap coefficients of the input side and the sum of squared powers of tap coefficients of the output sides are obtained through adders 641 and 642. Outputs of the adders 641 and 642 are sent to a subtractor 650 to calculate a difference between these tow outputs. The calculated difference D is given by the following equation.

The outputs DA to DN of the subtractors 650 in the respective channels are supplied to the signal selecting circuit 7, and in response thereto the frequency control circuit 8 adjusts the oscillation frequency of the oscillator 2 to obtain an optimum sampling timing. In other words, an optimum sampling timing is obtained by adjusting a tap position giving a maximum tap coefficient value to the central tap position.

Figure 4 shows another example of the circuit for extracting timing phase deviation data. According to this circuit, the tap position deviation is developed based upon the balance of the tap coefficient distribution between the input side and the output side with the central tap position as a boundary. Compared with the circuit of Figure 3, the circuit of Figure 4 is simplified since there is no need of performing square power calculation.

In Figure 4, registers 601 to 604, multipliers 610 to 614 and an adder 620 constituting a transversal filter are constructed in the same manner as in Figure 3. The balanced condition of tap coefficients on the input and output sides with the central tap position as a boundary is checked by comparing the tap coefficients CM+1 and CM-1 at symmetrical positions with each other. That is, a subtractor 660 finds a difference (CMS - CM-1 ) between the tap coefficients at the symmetrical positions, and the difference is multiplied by the tap coefficient CM by a multiplier 670 to find the timing phase deviation data D as given by D = CM(CM1 - CM1).

In Figures 5 and 6, the abscissa represents the tap position (time corresponding to the tap positions), and the ordinate represents the tap coefficient value. Under the condition where there is no timing phase deviation, the central tap coefficient CM exists at a peak position of impulse response curve R. As the timing phase deviation (e.g., time t) takes place, on the other hand, the central tap coefficient CM is deviated from the peak position. According to this embodiment, the deviation is extracted by comparing tap coefficients CM+1 and CM-1 at symmetrical positions with each other.In FigureS, the absolute value of difference I CM+1- CM~1 represents the amount of timing phase deviation, and the polarity thereof represents the direction of timing phase deviation, over a phase deviation range of +90 . Over a phase deviation of 90 to 270 , furthermore, the polarity of tap coefficients is inverted as shown in Figure 6. By multiplying the difference (CMS1- CM-i) by CM, the amount of timing phase deviation can be extracted in the same manner as in Figure 5.

Figure 7 illustrates another embodiment of the present invention. The embodiment shown in Figure 1 removes uncertainty in the timing phase deviation data that caused by the decrease in received signal power due to selective fading. This embodiment is capable of removing uncertainty in the timing phase deviation data that caused by radio interference as well as by selective fading.

The embodiment shown in Figure 7 is different from that in Figure 1 only with regard to the equalizers 6A to 6N which have a known AGC function and a function to generate a well-known decision error power, and to the timing phase conrol signal selecting circuit 7 which selects the timing phase deviation data DA, Da, Dc, -----, , DN on the basis of the decision errors powers EA, EB, Ec, , EN.

The timing phase control signal selecting circuit 7 monitors the decision error powers of all the channels or a plurality of predetermined channels to select the channel or channels whose decision error power is smaller than an allowable value, and the timing phase deviation data of the selected channel or channels is sent to the frequency control circuit 8. When the radio interference is not taking place on the transmission line, the decision error powers of all the monitored channels are smaller than the value for discrimination.

The timing phase deviation data of all the monitored channels are selected and averaged, making it possible to produce a highly accurate timing phase deviation control signal. In contrast, when radio interference occurs on the transmission n I i ne, the decision error power of a channel where the radio interference occurs becomes greater than the allowable value, and therefore, the timing phase deviation data of that channel may fail to exhibit an accurate value. In this case, according to this embodiment, the deteriorated channel is not selected and its the timing phase deviation data is not employed. Therefore, a highly accurate timing phase deviation control signal is obtainable on the basis of the timing phase deviation data from the remaining, non- or less-deteriorated channels. Therefore, the timing phase control signal selected by the timing phase control signal selecting circuit 7 exhibits highly accurate value at all times irrespective of the radio interference on the transmission line.

There can be contrived various other methods to select an optimum channel out of a plurality of monitored channels. For instance, the least-deteriorated channel which has the smallest decision error power may be selected and the timing phase control signal of that channel only may be used for the timing control.

Claims

1. A multiplex data receiver comprising a sampler, demodulating means for producing a plurality of demodulated signals, a plurality of equalizers for equalizing the demodulated signals, and control means responsive to a timing phase deviation signal produced by one or more of the equalizers to control the sampling phase of the sampler, and a selecting circuit which selects the said one or more of the equalizers as that equalizer or those equalizers whose demodulated signals satisfy a predetermined criterion of goodness.

2. A data receiver according to claim 1, wherein the selecting circuit selects from the set consisting of all equalizers.

3. A data receiver according to claim 1, wherein the selecting circuit selects from a set consisting of predetermined ones only and not all of the equalizers.

4. A data receiver according to claim 2 or 3, wherein the said criterion is absolute.

5. A data receiver according to claim 2 or 3, wherein the said criterion is relative as between the equalizers in the said set.

6. A data receiver according to claim 5, wherein the selecting circuit selects only the equalizer whose demodulated signal is the best of the demodulated signals.

7. A data receiver according to any of claims 2 to 6, wherein the criterion of goodness is inversely related to the amount of deterioration experienced by the data transmitted in the corresponding channel.

8. A data receiver according to any of claims 2 to 7, wherein each equalizer in the said set has an associated power measuring circuit for measuring the power in the corresponding demodulated signal and in that the selecting circuit determines which demodulated signals are good in dependent upon their power signals.

9. A data receiver according to claim 8, wherein each power measuring circuit controls an AGC circuit preceding the corresponding equalizer.

10. A data receiver according to claim 8 or 9, wherein the selecting circuit includes a comparator circuit for comparing the power signals with a predetermined threshold and a switching circuit for passing to the control means only these deviation signals corresponding to power signals exceeding the threshold.

11. A data receiver according to any of claims 2 to 7, wherein each equalizer in the said set provides a decision error power signl and in that the selecting circuit determines which demodulated signals are good in dependence upon their corresponding decision error power signals.

12. A data receiver according to claim 11, wherein the selecting circuit includes a comparator circuit for comparing the decision error power signals with a predetermined threshold and a switching circuit for passing to the control means only these deviation signals corresponding to decision error power signals below the threshold.

13. A data receiver according to any of claims 1 to 12, wherein the control means control the sampling phase in dependence upon an average of the timing phase deviation signals selected by the selecting circuit.

14. A data receiver according to any of claims 1 to 13, wherein the control means comprises a controlled oscillator for adjusting the instantaneous sampling frequency in dependence upon the timing phase deviation signals selected by the selecting circuit.

15. A data receiver according to any of claims 1 to 14, wherein each equalize is a transversal filter and produces its timing phase deviation signal on the basis of tap coefficients positioned on the input side and on the output side of the central tap position.

16. A data receiver according to claim 15, wherein the timing phase deviation signal is produced on the basis of the comparison result between tap coefficients at symmetrical positions on the input side and the output side of the central tap position.

17. A data receiver according to claim 16, wherein the timing phase deviation signal is produced on the basis of the difference between the tap coefficients at symmetrical positions on the input side and the output side of the central tap position multiplied by the tap coefficient at the central tap position.

18. A data receiver according to claim 15, wherein the timing phase deviation signal is produced on the basis of the comparison result between the sums of squared powers of tap coefficients on the input side and the output side of the central tap position.