CN109861690B - Output feedback clock duty ratio adjusting device, method and system - Google Patents
Output feedback clock duty ratio adjusting device, method and system Download PDFInfo
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- CN109861690B CN109861690B CN201910088934.8A CN201910088934A CN109861690B CN 109861690 B CN109861690 B CN 109861690B CN 201910088934 A CN201910088934 A CN 201910088934A CN 109861690 B CN109861690 B CN 109861690B
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Abstract
The invention provides a duty ratio adjusting device, a method and a system of an output feedback clock, wherein the device comprises: the clock receiver is used for receiving and amplifying the differential clock signals and is also used for adjusting the duty ratio of the differential clock signals; the clock buffer circuit is used for increasing the driving capability of the clock receiver for amplifying the differential clock signal; the analog synchronization circuit is used for synchronizing data in the digital-to-analog converter according to the differential clock signal to generate differential data; the analog DAC core circuit is used for converting the digital signals into corresponding analog signals; the duty ratio detection circuit is used for extracting duty ratio information of an analog signal, wherein the waveform of the analog signal is positively correlated with the clock duty ratio; and a duty ratio adjusting circuit for generating a duty ratio adjustment control signal with respect to the differential clock signal within the clock receiver according to the extracted duty ratio information. The invention reduces the influence of non-ideal factors on the duty ratio in the digital-to-analog conversion of the clock, and improves the speed and the accuracy of the duty ratio adjustment.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a duty ratio adjusting device, method and system of an output feedback clock, which are applied to clock processing of high-speed two-path time-interleaved DACs.
Background
With the increase of the conversion rate of the DAC, the high-speed DAC starts to adopt a time interleaving structure to increase the speed, and the clock has two phases of high and low levels, so that the two-path time interleaving structure is most convenient to realize and use. As shown in fig. 1, the two-way time interleaving structure outputs 1 group of signals at the high level of the clock, and outputs another group of signals at the low level of the clock, so as to realize the alternate output of the two signals.
The ideal DAC output signal has a zero-order hold characteristic, requiring that the hold times of the output signals be equal. The holding time of odd output signals of a DAC adopting a two-way time interleaving structure is related to the high/low level of a clock, and the holding time of even output signals is related to the low/high level of the clock, so that when the duty ratio of the clock does not meet the requirement, the output signals of the DAC have 2 different holding times which are alternately changed, and clutter related to signal frequency is generated in an NYQUIST area of the DAC. The first nyquist zone of the DAC is 0-fDAC/2, and when a sine wave of frequency fout is output, a spur is generated at fDAC/2-fout, thereby degrading the wide-band spectral characteristics of the DAC.
However, a conventional clock duty cycle feedback control circuit is shown in fig. 2. The duty ratio is detected after the clock is received, the duty ratio of the clock is adjusted according to the detection result, the corrected clock is sent to the high-speed synchronization unit through buffering, although the performance of the corrected clock is good, the duty ratio of an output signal after buffering, data synchronization and current switching changes, and the expected improvement effect is difficult to obtain after the clock is corrected.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides an output feedback clock duty cycle adjusting device, method and system for solving the problem of the influence of the non-ideal factor of the corrected clock on the channel path, the non-ideal factor of the data processed by the clock, and the non-ideal factor of the data converted by the current switch on the output signal of the DAC.
To achieve the above and other related objects, the present invention provides an output feedback clock duty ratio adjusting device, adapted to adjust a duty ratio of a clock signal in a digital-to-analog converter, including:
the clock receiver is used for receiving an externally input differential clock signal, amplifying the differential clock signal into a CMOS signal and receiving a duty ratio adjusting control signal to adjust the duty ratio of the differential clock signal;
a clock buffer circuit for increasing a driving capability of the clock receiver to amplify the differential clock signal;
the analog synchronization circuit is used for synchronizing data in the digital-to-analog converter according to the differential clock signal to generate differential data so as to simulate the non-ideal phenomenon of the synchronization circuit on a data path in the digital-to-analog converter;
the analog DAC core circuit is used for converting the digital signals into corresponding analog signals so as to simulate the non-ideal phenomenon of a DAC core in the digital-to-analog converter;
the duty ratio detection circuit is used for extracting duty ratio information of an analog signal output by the analog DAC core, wherein the waveform of the analog signal is positively correlated with the clock duty ratio;
a duty cycle adjustment circuit for generating a duty cycle adjustment control signal with respect to a differential clock signal within the clock receiver based on the extracted duty cycle information.
Another objective of the present invention is to provide a method for adjusting duty ratio of an output feedback clock, which is suitable for adjusting the duty ratio of a clock signal in a digital-to-analog converter; the method comprises the following steps:
receiving an input differential clock signal by using a clock receiver, and amplifying the differential clock signal into a CMOS signal;
utilizing a clock buffer circuit to increase the driving capability of the clock receiver for amplifying the differential clock signal so as to connect at least two analog synchronous circuits;
synchronizing data in the digital-to-analog converter by using an analog synchronization circuit according to the differential clock signal to generate differential data so as to simulate the non-ideal phenomenon of the synchronization circuit on a data path in the digital-to-analog converter;
converting the digital signals in the differential data into corresponding analog signals by using an analog DAC core circuit so as to simulate the non-ideal phenomenon of a DAC core in the digital-to-analog converter;
extracting duty ratio information of an analog signal output by the analog DAC core by using a duty ratio detection circuit;
generating, with a duty cycle adjustment circuit, a duty cycle adjustment control signal with respect to a differential clock signal within the clock receiver according to the duty cycle information;
and adjusting the differential clock signal in the clock receiver according to the duty ratio adjusting control signal.
The invention also aims to provide an output feedback clock duty ratio adjusting system which comprises the output feedback clock duty ratio adjusting device.
As described above, the output feedback clock duty ratio adjusting apparatus, method and system of the present invention have the following advantages:
the invention adopts the clock buffer circuit, reduces the influence of non-ideal factors on the time duty ratio on the clock path, simultaneously utilizes the analog synchronization unit and the analog DAC core to simulate the conversion of the DAC digital signal to the analog signal, reduces the influence of the non-ideal factors on the duty ratio in the digital-to-analog conversion of the clock, and improves the speed and the accuracy of the duty ratio adjustment.
Drawings
FIG. 1 is a schematic diagram of a two-way time-interleaved DAC;
FIG. 2 is a schematic diagram of a conventional clock duty cycle feedback control;
FIG. 3 is a block diagram of an output feedback clock duty cycle adjusting apparatus according to the present invention;
FIG. 4 shows an implementation circuit diagram of a Dummy DAC core circuit provided by the present invention;
FIG. 5 is a schematic diagram showing an output signal of a Dummy DAC core circuit according to the present invention;
fig. 6 is a flowchart illustrating a method for adjusting duty ratio of an output feedback clock according to the present invention.
Element number description:
1. time receiver
2. Clock buffer circuit
3. Analog synchronous circuit
4. Analog DAC nuclear circuit
5. Duty ratio detection circuit
6. Duty cycle regulating circuit
31. First analog synchronous circuit
32. Second analog synchronous circuit
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, amount and proportion of each component in actual implementation can be changed freely, and the layout of the components can be more complicated.
Referring to fig. 3, a block diagram of a structure of a duty ratio adjusting device for an output feedback clock according to the present invention includes:
the clock receiver 1 is configured to receive a differential clock signal input from the outside, amplify the differential clock signal into a CMOS signal, and receive a duty ratio adjustment control signal to adjust a duty ratio of the differential clock signal;
the differential clock signal is a sine wave clock signal, the clock receiver amplifies the sine wave clock signal into a COMS signal, and the clock receiver can amplify the sine wave clock signal by adopting a high-speed signal amplifying circuit.
A clock buffer circuit 2 for increasing a driving capability of the clock receiver to amplify the differential clock signal;
the clock buffer circuit can increase the driving capability of the clock receiver in a step-by-step increasing manner.
An analog synchronization circuit 3 (Dummy synchronization circuit) for synchronizing data in the digital-to-analog converter according to the differential clock signal to generate differential data so as to simulate a non-ideal phenomenon of a synchronization circuit on a data path in the digital-to-analog converter;
the analog synchronization circuit and the synchronization circuit in the digital-to-analog converter are realized by the same circuit structure.
An analog DAC core circuit 4 (Dummy DAC core) for converting the digital signal into a corresponding analog signal to simulate the non-ideal phenomenon of the DAC core in the digital-to-analog converter;
the analog DAC core circuit and the DAC core circuit in the digital-to-analog converter are realized by the same circuit structure.
The duty ratio detection circuit 5 is used for extracting duty ratio information of an analog signal output by the analog DAC core, wherein the waveform of the analog signal is positively correlated with the clock duty ratio;
wherein, the waveform of the output signal of the Dummy DAC core is related to the clock duty ratio.
A duty ratio adjusting circuit 6 for generating a duty ratio adjusting control signal regarding a differential clock signal within the clock receiver according to the extracted duty ratio information.
The clock receiver signal path can be pulled up or pulled down through a transistor.
In this embodiment, since fig. 3 is evolved according to the implementation principle of two paths of time-interleaved digital-to-analog converters, if a multi-channel time-interleaved digital-to-analog converter is selected, a plurality of analog synchronization circuits need to be correspondingly connected behind a clock buffer circuit, that is, this embodiment can be applied to a time-interleaved DAC of any channel. The invention overcomes the non-ideal factors of the clock on the channel path, the data processed by the clock and the data converted by the current switch after the correction of the traditional clock duty ratio adjusting device (feedback control device), and improves the speed and the accuracy of the duty ratio adjustment, thereby improving the overall performance of the time-interleaved DAC.
Wherein, the output feedback clock duty ratio adjusting device can be manufactured by adopting a standard CMOS process or a Bipolar process.
On the basis of the above embodiment, the analog synchronization circuit 3 includes at least a first analog synchronization circuit 31 (first Dummy synchronization circuit) and a second analog synchronization circuit 32 (first Dummy synchronization circuit), wherein one input terminal of the first analog synchronization circuit is connected to a low level "0" as input data; the other input end of the first analog synchronous circuit receives an output end of the clock buffer, and two output ends of the first analog synchronous circuit output first differential data after synchronization; one input end of the second analog synchronous circuit is connected with a high level '1' and used as input data; the other input end of the second analog synchronization circuit receives the other output end of the clock buffer, and the two output ends of the second analog synchronization circuit output the synchronized second differential data.
Specifically, as fig. 3 is a clock duty ratio adjusting device of two-way time-interleaved digital-to-analog converter, the corresponding analog synchronization circuit includes a first analog synchronization circuit 31 and a second analog synchronization circuit 32, wherein the analog synchronization circuit has the same structure as the synchronization circuit corresponding to the main data (main data 0 and main data 1) in the digital-to-analog converter, and is used for simulating the non-ideal phenomenon of the synchronization circuit on the main data channel, so as to reduce the influence of the non-ideal factor on the duty ratio of the clock in the digital-to-analog conversion.
On the basis of the foregoing embodiment, please refer to fig. 4, which is a circuit diagram for implementing a Dummy DAC core circuit according to the present invention, where the analog DAC core circuit includes a first DAC1 and a second DAC2, an input terminal of the first DAC is connected to a high level "1", one end of a first output terminal and one end of a second output terminal of the first DAC are respectively connected to a control switch, and the control switch receives a differential clock signal CLKp for control; the input end of the second digital-to-analog conversion unit is connected with a low level '0', one end of a first output end and one end of a second output end of the second digital-to-analog conversion unit are respectively connected with a control switch, the control switches are controlled by a differential clock signal CLKn, the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second output end of the second digital-to-analog conversion unit are interconnected and output a first pulse signal OUTP, the other ends of the control switches corresponding to the second output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are interconnected and output a second pulse signal OUTN, and the first pulse signal OUTP and the second pulse signal OUTN are complementary signals.
Wherein the analog DAC core circuit further comprises: the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are connected with one end of a first protection resistor, and the other end of the first protection resistor is connected with a power supply voltage VSS; the other end of the control switch corresponding to the second output end of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit is connected with one end of a second protection resistor, the other end of the second protection resistor is connected with a power supply voltage VSS, and the same resistance values of the first protection resistor and the second protection resistor are R.
Specifically, as shown in fig. 5, DAC1_ outp outputs high and DAC1_ outn outputs low at a high "1" input, DAC2_ outp outputs low and DAC2_ outn outputs high at a low "0" input.
When the differential clock signal CLKp is at a high level and the differential clock signal CLKn is at a low level, the control switch corresponding to the first output terminal of the DAC1 is turned off and cannot be turned on, and the control switch corresponding to the first output terminal of the DAC2 is turned on and outputs a low level, then the first pulse signal OUTp is at a low level; the control switch corresponding to the second output terminal of the DAC1 is turned off and cannot be turned on, and the control switch corresponding to the second output terminal of the DAC2 is turned on to output a high level, so that the second pulse signal OUTn is at a high level.
When the differential clock signal CLKp is at a low level and the differential clock signal CLKn is at a high level, the control switch corresponding to the first output terminal of the DAC1 is turned on to output a high level, and the control switch corresponding to the first output terminal of the DAC2 is turned off and cannot be turned on, so that the first pulse signal OUTp is at a high level; and enabling the control switch corresponding to the second output end of the DAC1 to be turned on and output a low level, and enabling the control switch corresponding to the second output end of the DAC2 to be turned off and unable to be turned on, so that the second pulse signal OUTn is at a low level.
In the embodiment, the Dummy DAC circuit reduces the influence of non-ideal factors on the duty ratio of a clock in digital-to-analog conversion by matching the conversion from the analog DAC digital signal to the analog signal of the Dummy synchronous circuit, and improves the speed and the accuracy of duty ratio adjustment, thereby improving the overall performance of the time-interleaved DAC.
On the basis of the above embodiment, the duty ratio detection circuit includes a low-pass filtering unit and a comparing unit, wherein an input end of the low-pass filtering unit is connected to two output signals of the analog DAC core circuit, and converts a pulse width into a level signal; the comparator is connected with the output end of the low-pass filtering unit and converts the level signal into clock duty ratio information, namely, the magnitude relation between the clock high level holding time and the clock low level holding time, because the two paths of time-interleaved DACs are preferred in the embodiment, the duty ratio of the high level and the low level output by the duty ratio detection circuit tends to be 50%, and the duty ratio adjusting control signal generated by the duty ratio adjusting circuit aims to enable the duty ratio of the high level and the low level output by the clock receiver to be up to 50%.
On the basis of the above embodiments, there is an output feedback clock duty ratio adjusting system, which includes the above output feedback clock duty ratio adjusting device, which is not described herein again.
Referring to fig. 6, a flowchart of a duty cycle adjusting method of an output feedback clock according to the present invention is shown,
s1, receiving an input differential clock signal by using a clock receiver, and amplifying the differential clock signal into a CMOS signal;
step S2, a clock buffer circuit is used for increasing the driving capability of the clock receiver for amplifying the differential clock signal so as to connect at least two analog synchronous circuits;
s3, synchronizing data in the digital-to-analog converter by using an analog synchronization circuit according to the differential clock signal to generate differential data so as to simulate the non-ideal phenomenon of the synchronization circuit on a data path in the digital-to-analog converter;
s4, converting the digital signals in the differential data into corresponding analog signals by using an analog DAC core circuit so as to simulate the non-ideal phenomenon of a DAC core in the digital-to-analog converter;
s5, extracting duty ratio information of an analog signal output by the analog DAC core by using a duty ratio detection circuit;
step S6, utilizing a duty ratio adjusting circuit to generate a duty ratio adjusting control signal related to a differential clock signal in the clock receiver according to the duty ratio information;
and S7, adjusting the differential clock signal in the clock receiver according to the duty ratio adjusting control signal.
Wherein the analog synchronization circuit comprises at least a first analog synchronization circuit and a second analog synchronization circuit,
one input end of the first analog synchronous circuit is connected with a low level '0', the other input end of the first analog synchronous circuit receives one output end of the clock buffer, and two output ends of the first analog synchronous circuit output first differential data after synchronization;
one input end of the second analog synchronous circuit is connected with a high level 1, the other input end of the second analog synchronous circuit receives the other output end of the clock buffer, and two output ends of the second analog synchronous circuit output the second differential data after synchronization.
The analog DAC core circuit comprises a first digital-to-analog conversion unit DAC1 and a second digital-to-analog conversion unit DAC2, wherein the input end of the first digital-to-analog conversion unit is connected with a high level '1', one end of a first output end and one end of a second output end of the first digital-to-analog conversion unit DAC are respectively connected with a control switch, and the control switches are controlled by a differential clock signal CLKp; the input end of the second digital-to-analog conversion unit is connected with a low level '0', one end of a first output end and one end of a second output end of the second digital-to-analog conversion unit are respectively connected with a control switch, the control switches are controlled by a differential clock signal CLKn, the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second output end of the second digital-to-analog conversion unit are interconnected and output a first pulse signal OUTP, the other ends of the control switches corresponding to the second output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are interconnected and output a second pulse signal OUTN, and the first pulse signal OUTP and the second pulse signal OUTN are complementary signals.
The analog DAC core circuit further comprises: the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are connected with one end of a first protection resistor, and the other end of the first protection resistor is connected with a power supply voltage; the other end of the control switch corresponding to the second output end of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit is connected with one end of a second protection resistor, and the other end of the second protection resistor is connected with the power supply voltage.
The duty ratio detection circuit comprises a low-pass filtering unit and a comparison unit, wherein the input end of the low-pass filtering unit is connected with two output signals of the analog DAC core circuit, and the pulse width is converted into a level signal; the comparator is connected with the output end of the low-pass filtering unit and converts the level signal into a clock duty ratio signal.
Since the output feedback clock duty ratio adjusting method and the output feedback clock duty ratio adjusting device are in a one-to-one correspondence relationship, the corresponding technical details and technical effects are not repeated herein, and the details are described in the output feedback clock duty ratio adjusting device.
In summary, the invention employs the clock buffer path, so as to reduce the influence of non-ideal factors on the time duty ratio on the clock path, and meanwhile, the analog synchronization unit and the analog DAC core are used for converting the digital DAC digital signal into the analog signal, so as to reduce the influence of the non-ideal factors on the duty ratio in the digital-to-analog conversion of the clock, and improve the speed and accuracy of duty ratio adjustment. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. An output feedback clock duty cycle adjusting device, adapted to adjust the duty cycle of a clock signal in a digital-to-analog converter, comprising:
the clock receiver is used for receiving an externally input differential clock signal, amplifying the differential clock signal into a CMOS signal and receiving a duty ratio adjusting control signal to adjust the duty ratio of the differential clock signal;
a clock buffer circuit for increasing a driving capability of the clock receiver to amplify the differential clock signal;
the analog synchronization circuit is used for synchronizing data in the digital-to-analog converter according to the differential clock signal to generate differential data so as to simulate the non-ideal phenomenon of the synchronization circuit on a data path in the digital-to-analog converter;
the analog DAC core circuit is used for converting the digital signals into corresponding analog signals so as to simulate the non-ideal phenomenon of a DAC core in the digital-to-analog converter;
the duty ratio detection circuit is used for extracting duty ratio information of an analog signal output by the analog DAC core, wherein the waveform of the analog signal is positively correlated with the clock duty ratio;
a duty cycle adjustment circuit for generating a duty cycle adjustment control signal with respect to a differential clock signal within the clock receiver based on the extracted duty cycle information.
2. The output feedback clock duty cycle adjustment device of claim 1, wherein the analog synchronization circuit comprises at least a first analog synchronization circuit and a second analog synchronization circuit, wherein,
one input end of the first analog synchronous circuit is connected with a low level '0', the other input end of the first analog synchronous circuit receives one output end of the clock buffer, and two output ends of the first analog synchronous circuit output first differential data after synchronization;
one input end of the second analog synchronous circuit is connected with a high level 1, the other input end of the second analog synchronous circuit receives the other output end of the clock buffer, and two output ends of the second analog synchronous circuit output the second differential data after synchronization.
3. The output feedback clock duty cycle adjusting device according to claim 1, wherein the analog DAC core circuit comprises a first digital-to-analog converting unit and a second digital-to-analog converting unit, an input terminal of the first digital-to-analog converting unit is connected to a high level "1", and one end of a first output terminal and one end of a second output terminal of the first digital-to-analog converting unit are respectively connected to a control switch, and the control switches are controlled by a differential clock signal CLKp; the input end of the second digital-to-analog conversion unit is connected with a low level '0', one end of a first output end and one end of a second output end of the second digital-to-analog conversion unit are respectively connected with a control switch, the control switches are controlled by a differential clock signal CLKn, the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second output end of the second digital-to-analog conversion unit are interconnected and output a first pulse signal OUTP, the other ends of the control switches corresponding to the second output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are interconnected and output a second pulse signal OUTN, and the first pulse signal OUTP and the second pulse signal OUTN are complementary signals.
4. The output feedback clock duty cycle adjustment device of claim 3, wherein the analog DAC core circuit further comprises: the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are connected with one end of a first protection resistor, and the other end of the first protection resistor is connected with a power supply voltage; the other end of the control switch corresponding to the second output end of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit is connected with one end of a second protection resistor, and the other end of the second protection resistor is connected with the power supply voltage.
5. The output feedback clock duty cycle adjusting device according to claim 1, wherein the duty cycle detecting circuit comprises a low pass filtering unit and a comparing unit, wherein the input end of the low pass filtering unit is connected with two output signals of the analog DAC core circuit to convert the pulse width into a level signal; the comparison unit is connected with the output end of the low-pass filtering unit and converts the level signal into clock duty ratio information.
6. A duty ratio adjusting method of an output feedback clock is suitable for adjusting the duty ratio of a clock signal in a digital-to-analog converter, and comprises the following steps:
receiving an input differential clock signal by using a clock receiver, and amplifying the differential clock signal into a CMOS signal;
utilizing a clock buffer circuit to increase the driving capability of the clock receiver for amplifying the differential clock signal so as to connect at least two analog synchronous circuits;
synchronizing data in the digital-to-analog converter by using an analog synchronization circuit according to the differential clock signal to generate differential data so as to simulate the non-ideal phenomenon of the synchronization circuit on a data path in the digital-to-analog converter;
converting the digital signals in the differential data into corresponding analog signals by using an analog DAC core circuit so as to simulate the non-ideal phenomenon of a DAC core in the digital-to-analog converter;
duty ratio information of an analog signal output by the analog DAC core is extracted by using a duty ratio detection circuit;
generating, with a duty cycle adjustment circuit, a duty cycle adjustment control signal with respect to a differential clock signal within the clock receiver according to the duty cycle information;
and adjusting the differential clock signal in the clock receiver according to the duty ratio adjusting control signal.
7. The output feedback clock duty cycle adjustment method of claim 6, wherein the analog synchronization circuit comprises at least a first analog synchronization circuit and a second analog synchronization circuit, wherein,
one input end of the first analog synchronous circuit is connected with a low level 0, the other input end of the first analog synchronous circuit receives one output end of the clock buffer, and two output ends of the first analog synchronous circuit output first differential data after synchronization;
one input end of the second analog synchronous circuit is connected with a high level 1, the other input end of the second analog synchronous circuit receives the other output end of the clock buffer, and two output ends of the second analog synchronous circuit output the second differential data after synchronization.
8. The method according to claim 6, wherein the DAC core circuit comprises a first DAC unit and a second DAC unit, the input terminal of the first DAC unit is connected to a high level "1", and one end of the first output terminal and one end of the second output terminal are connected to a control switch respectively, and the control switch receives the differential clock signal CLKp for control; the input end of the second digital-to-analog conversion unit is connected with a low level '0', one end of a first output end and one end of a second output end of the second digital-to-analog conversion unit are respectively connected with a control switch, the control switches are controlled by a differential clock signal CLKn, the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second output end of the second digital-to-analog conversion unit are interconnected and output a first pulse signal OUTP, the other ends of the control switches corresponding to the second output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are interconnected and output a second pulse signal OUTN, and the first pulse signal OUTP and the second pulse signal OUTN are complementary signals.
9. The output feedback clock duty cycle adjustment method of claim 8, wherein the analog DAC core circuit further comprises: the other ends of the control switches corresponding to the first output ends of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are connected with one end of a first protection resistor, and the other end of the first protection resistor is connected with a power supply voltage; the other end of the control switch corresponding to the second output end of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit is connected with one end of a second protection resistor, and the other end of the second protection resistor is connected with the power supply voltage.
10. The output feedback clock duty cycle adjusting method according to claim 6, wherein the duty cycle detecting circuit comprises a low pass filtering unit and a comparing unit, wherein the input end of the low pass filtering unit is connected with two output signals of the analog DAC core circuit to convert the pulse width into a level signal; the comparison unit is connected with the output end of the low-pass filtering unit and converts the level signal into clock duty ratio information.
11. An output feedback clock duty cycle regulation system comprising the output feedback clock duty cycle regulation device of any one of claims 1 to 5.
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| CN111934655B (en) * | 2020-07-28 | 2023-03-28 | 新华三半导体技术有限公司 | Pulse clock generation circuit, integrated circuit and related method |
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