KR101287097B1 - Four-channel pipelined sar adc to minimize mismatches between channels - Google Patents

Abstract

PURPOSE: A four channel pipe line SAR ADC minimized mismatching between channels is provided to remove amplifier offset mismatching between channels and to minimize electricity consumption and an area. CONSTITUTION: Four channel pipe line SAR ADC comprises a first SAR ADC (100), a remaining voltage amplifier (110), a second SAR ADC (120) and a digital correction circuit (130). For pieces of 6 bit SAR ADC in the first step is composed of SAR ADC with four channels connected in parallel. The remaining voltage amplifier is connected to an output unit of the first SAR ADC and is shared in four channels with a couple of input units. The second SAR ADC is composed of SAR ADC in four channels connected in parallel which tests remaining voltage which is amplified in the remaining voltage amplifier. The digital correction circuit corrects errors of digital output which comes out of the first SAR ADC and the second SAR ADC.

Description

A four-channel pipelined SAR ADC minimizes cross-channel mismatch problems.

The present invention relates to a 4-channel time-interleaved (TI) pipelined successive approximation register (SAR) analog-to-digital converter (ADC), and more particularly, Channel pipelined SAR ADC that minimizes cross-channel mismatch problems, gain mismatch problems, and sampling timing mismatch problems, resolves reference voltage instability problems due to interchannel interference, and minimizes power consumption.

In high definition video systems such as HDTV, which require high definition and fast operation speed, an ADC for converting an analog signal including RGB signals into a digital signal is indispensable. In particular, HD1080i, which is the most widely used among HDTV broadcasts, requires an ADC having a resolution of 10 bits or more and an operation speed of 150MS / s or more. On the other hand, as the demand for ADCs with high resolution of 10 bits or more surges rapidly even at a high operation speed of several hundred MS / s or more, recently, pipelined ADCs are connected in parallel so that power consumption is minimized, Many TI pipeline ADCs have been proposed that can simultaneously obtain the TI pipeline ADC.

A typical T-I architecture-based ADC connects low-speed sub-ADCs in parallel to improve overall ADC operation speed while optimizing power consumption without process constraints. However, there are problems that the performance of the entire ADC is deteriorated due to offset mismatch between channels, gain mismatch, and sampling timing mismatch. In the case of a TI ADC with a resolution of 10 bits or more, the signal-to-noise-and-distortion ratio (SNDR) performance is limited to 55.9 dB at the maximum of two channels due to mismatch between channels, The more the mismatching performance is reduced. Therefore, in order to obtain high resolution of 10 bits or more, a correction technique to solve interchannel mismatch is essential, but since additional circuit is required and complicated, various T-I pipeline ADCs based on various analog circuit design techniques have been recently announced.

First, the closed-loop sampling technique can solve the offset mismatch problem by eliminating the amplifier offset effect of each channel. However, the stability problem may occur due to the difference between the loop gain and the phase margin in the amplifying and sampling operation. In particular, the sampling operation is limited by the performance of the amplifier.

In the dual sampling scheme, only one amplifier is used in both channels to reduce the area and power consumption while eliminating the offset mismatch problem between the channels. However, since the amplifier is continuously used for one cycle, the amplifier input terminal is reset There is no time, and a memory effect occurs. This requires an additional digital domain correction scheme to eliminate memory effects.

Another method for eliminating offset mismatches is random chopping. However, since the noise is increased and the SNDR is maintained, it is necessary to completely remove the tone due to the offset mismatch in order to obtain a high SNDR. On the other hand, when two or more channels use a technique of sharing one sample-and-hold amplifier (SHA), the interchannel offset and sampling timing mismatch are reduced, but the requirement of SHA to operate over the entire period is high, There is a restriction on the number of channels. In order to solve this problem, a SHI-free T-I ADC has been proposed. However, this structure reduces the input signal bandwidth and there is still a channel mismatch problem due to the amplifier of the first stage multiplying digital-to-analog converter (MDAC).

Therefore, a problem to be solved by the present invention is to minimize the problem of channel-to-channel offset mismatch, gain mismatch problem and sampling timing mismatch in the TI structure, solve the problem of reference voltage instability due to interchannel interference, and minimize power consumption Channel 4-channel pipelined SAR ADC.

In order to achieve the above object, the present invention provides a SAR ADC comprising: a first SAR ADC consisting of four channels of SAR ADCs connected in parallel; One residual voltage amplifier coupled to the output of the first SAR ADC and shared by four channels having two separate pairs of inputs; A second SAR ADC consisting of four-channel SAR ADCs connected in parallel for sampling the residual voltage amplified in the residual voltage amplifier; And a digital calibration circuit for correcting an error of a digital output output from the first SAR ADC and the second SAR ADC.

According to an embodiment of the present invention, the SAR operation timing of the SAR ADC corresponding to the first channel and the SAR ADC included in the first SAR ADC and the SAR ADC included in the second SAR ADC does not overlap, The SAR ADCs corresponding to the first channel and the third channel share one reference voltage and the SAR ADCs corresponding to the second and fourth channels share another reference It is desirable to share the voltage.

In addition, since the residual voltage amplification operation sections in the four channels do not overlap each other, the residual voltage amplifier uses one reference voltage that shares one reference voltage and has a specification different from the reference voltage used by the SAR ADCs desirable.

According to another embodiment of the present invention, there is further provided an on-chip clock generation circuit for generating a high frequency clock, wherein the on-chip clock generation circuit is capable of adjusting a duty cycle of a clock used for SAR operations .

Also, half of the input signal range input to the first SAR ADC can be used as the input signal to the second SAR ADC.

According to another embodiment of the present invention, the first SAR ADC and the second SAR ADC perform a sampling operation at a quarter of the operation speed of the 4-channel pipeline SAR ADC, and the falling edge of the sampling clock edge can be synchronized with an externally applied clock.

According to the present invention, the pipelined SAR structure is selected instead of removing the SHA, and the four channels share one residual voltage amplifier, thereby eliminating the channel-to-channel amplifier offset mismatch problem and minimizing power consumption and area .

In addition, according to the present invention, by separating the reference voltage used in the amplification operation and the SAR operation and implementing all the channels to use the same reference voltage in the residual voltage amplification operation, the problem of the reference voltage instability between channels and the gain inconsistency problem It can be solved at the same time.

Furthermore, according to the present invention, the effect of sampling timing mismatch between channels can be minimized by synchronizing the polling edge of the sampling clock with an externally applied clock.

1 is a block diagram of a 4-channel pipelined SAR ADC according to a preferred embodiment of the present invention.
2 shows an overall timing diagram of a 4-channel pipelined SAR ADC according to a preferred embodiment of the present invention.
FIG. 3 illustrates a first stage of a conventional 4-channel 11-bit pipelined ADC and a first stage of a 4-channel 11-bit pipelined SAR ADC according to an embodiment of the present invention.
FIG. 4 illustrates the problem of sharing one reference voltage in four channels and the case of using separate reference voltages for each channel.
Figure 5 illustrates an ADC in accordance with an embodiment of the present invention using two separate reference voltages with separate specifications.
6 illustrates the structure and operation of an on-chip clock generation circuit included in an ADC according to an embodiment of the present invention.
Figure 7 shows the first stage using two different specifications of reference voltages.
Figure 8 shows a SAR ADC2 based on a range-scaling technique.
Figure 9 shows two separate pairs of input stage based residual voltage amplifiers.
FIG. 10 shows SNDR and SFDR according to the sampling frequency of the ADC and SNDR and SFDR according to the input frequency according to the embodiment of the present invention.

Prior to the description of the concrete contents of the present invention, for the sake of understanding, the outline of the solution of the problem to be solved by the present invention or the core of the technical idea is first given.

The present invention proposes a 4-channel pipelined SAR 11-bit 150 MS / s ADC that minimizes interchannel mismatch problems by applying various analog circuit based design techniques without special correction techniques.

In order to solve the input offset mismatch between channels, the input SHA is removed. However, in the conventional SHA-free pipelined ADC, the input signal is sampled by the flash ADC and the MDAC, respectively, thereby causing a mismatch in the input signal that is sampled during high frequency input signal processing. To solve this problem, the ADC of the present invention employs a pipeline SAR structure using a SAR-based ADC instead of a flash ADC, and solves the problem that the input signal bandwidth is limited in a structure without SHA.

At the same time, the input signal is sampled through one sampling capacitor to enable both SAR operation and MDAC operation.

Also, in order to solve various nonlinear problems caused by the amplifier of the first stage MDAC, which is still present even though the input stage SHA is removed, four channels are sequentially shared by one residual voltage amplifier.

Meanwhile, the ADC according to the present invention separately separates the reference voltage used in the amplification operation and the SAR operation, thereby reducing the problem of the reference voltage instability caused by the SAR operation of the other channel during the amplification operation.

In addition, the implementation of all channels to use the same reference voltage during amplification operation minimizes the channel-to-channel gain mismatch problem.

In the case of sampling timing, a single clock-edge sampling technique is applied to the clocks used in four channels to minimize mismatch.

In addition, an on-chip clock generation circuit that generates a high frequency clock in the chip is used. In particular, to maximize the reference voltage sampling and preamp amplification operation period, a circuit is implemented so that the duty cycle can be controlled externally .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art, however, that these examples are provided to further illustrate the present invention, and the scope of the present invention is not limited thereto.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: It is to be noted that components are denoted by the same reference numerals even though they are shown in different drawings, and components of different drawings can be cited when necessary in describing the drawings. In the following detailed description of the principles of operation of the preferred embodiments of the present invention, it is to be understood that the present invention is not limited to the details of the known functions and configurations, and other matters may be unnecessarily obscured, A detailed description thereof will be omitted.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprises " or "comprising" when used herein should be interpreted as excluding the presence or addition of one or more other elements, steps, operations, or elements in addition to the stated element, step, I never do that.

1 is a block diagram of a 4-channel pipelined SAR ADC according to a preferred embodiment of the present invention.

FIG. 1 shows an 11-bit 150 MS / s pipelined SAR ADC based on a 4-channel T-I structure as an embodiment of the present invention.

Referring to FIG. 1, a 4-channel pipelined SAR ADC according to the present embodiment includes four 6-bit SAR ADCs 100 in the first stage, a residual voltage amplifier 110, four 6-bit SAR ADCs in the second stage 120, a digital calibration circuit 130, a reference current and reference voltage generator 140, a clock and timing circuit 150, and an on-chip clock generation circuit 160.

The four 6-bit SAR ADCs (100, hereinafter referred to as SAR ADC1) in the first stage sequentially sample the input signals into four channels and convert them into digital codes of the upper 6 bits through the SAR operation.

The residual voltage amplifier 110 amplifies the residual voltage, which is the difference between the input signal and the reference voltage determined by the upper 6-bit digital code, and sequentially transfers the amplified residual voltage to the four 6-bit SAR ADCs 120 of the second stage.

At this time, the residual voltage amplifier 110 has two pairs of separated input terminals, and four channels share one residual voltage amplifier 110.

The four 6-bit SAR ADCs 120 in the second stage (hereinafter referred to as SAR ADC2) sample the amplified residual voltage and then output the lower 6-bit digital code through the SAR operation.

The digital calibration circuit 130 corrects the error of the digital output from the SAR ADC1 100 and the SAR ADC2 120 and outputs it. That is, a high-order 6-bit digital code is input from the SAR ADC1 100, a low 6-bit digital code is input from the SAR ADC2 120, and then 11 bits are output.

The reference current and reference voltage generator 140 are integrated in the ADC chip and generate two different types of reference voltages for use in the SAR ADCs 100 and 120 and the residual voltage amplifier 110, respectively.

The clock and timing circuit 150 divides the externally applied 150 MHz clock to produce two remaining clocks of 75 MHz and 37.5 MHz.

The on-chip clock generation circuit 160 generates a clock of its own high frequency within the ADC chip for operation of the SAR ADCs 100 and 120 requiring a fast frequency of 450 MHz.

On the other hand, the proposed ADC uses the range-scaling technique to reduce the amplifier's closed-loop gain and optimize the power consumption of the amplifier.

2 shows an overall timing diagram of a 4-channel pipelined SAR ADC according to a preferred embodiment of the present invention.

Referring to FIG. 2, each of the four channels independently operates at 37.5 MS / s, and the entire ADC can obtain an operating speed of 150 MS / s (= 37.5 MS / s × 4 channels).

The input signal sequentially sampled in each of the four channels of the first stage SAR ADC1 (100) is converted into a digital code of the upper 6 bits through the SAR operation, and the difference between the input signal and the reference voltage determined by the upper 6-bit code The residual voltage is amplified and delivered sequentially to the second stage SAR ADC2 120.

The SAR ADC2 120 samples the amplified residual voltage from the residual voltage amplifier 110 and then outputs the lower 6-bit digital code through the SAR operation. In the second stage, the SAR operation time can be increased by the absence of the residual voltage amplification period. However, in order to use one on-chip clock generation circuit 160, .

As shown in the timing chart of the first stage at the top of FIG. 2, since the residual voltage amplification operation sections of the respective channels do not overlap each other, each of the four channels shares one reference voltage having an 11- can do.

In addition, channel 1 and channel 3, and channel 2 and channel 4 have different SAR operation periods. Therefore, the two groups of channels share a separate reference voltage having a 6-bit resolution, Respectively.

The present invention is characterized in that it includes a structure described below to solve a channel mismatch problem in a T-I structure.

First, to reduce the offset mismatch problem, it has a 4-channel T-I structure sharing one residual voltage amplifier.

FIG. 3 illustrates a first stage of a conventional 4-channel 11-bit pipelined ADC and a first stage of a 4-channel 11-bit pipelined SAR ADC according to an embodiment of the present invention.

3, there is shown a four-channel T-I structure sharing one residual voltage amplifier.

Table 1 compares the effect of offset mismatching based on the first stage of each ADC shown in FIG.

In the conventional 4-channel 11-bit pipelined ADC shown in FIG. 3, the input stage SHA of each channel and the offset of the first stage MDAC amplifier are the biggest factors that determine the offset of the entire ADC, and the amplifier offset matching Should be designed to be at least 11-bit level. However, existing pipelined ADCs will require at least 8 residual amplifiers per channel, at least for each channel, depending on the number of bits determined at each stage for 4-channel implementation. Without additional correction circuit, 11-bit level matching It is difficult to obtain. On the other hand, the first stage of a 4-channel 11-bit pipelined SAR ADC according to an embodiment of the present invention uses a pipelined SAR structure to replace the SHA function with a SAR structure, Of the residual voltage amplifiers, it is possible to fundamentally eliminate the offset mismatch problem between the four channels, while simultaneously minimizing power consumption and area.

Second, two separate specifications are used to minimize the gain mismatch problem.

4 shows a case where one reference voltage is shared by four channels and a case where reference voltages separated for each channel are used.

In general, the simplest way to solve the gain mismatch by the reference voltage in a conventional T-I ADC is to share the same reference voltage on all channels. However, due to the structural characteristics of the pipelined SAR in the ADC according to the present invention, as shown in FIG. 4 (a), when one reference voltage is shared in four channels, a problem of reference voltage instability due to inter- . That is, since a reference voltage becomes unstable due to interference with another channel which performs fast SAR operation of 450 MHz in one channel in the residual voltage amplification operation, stable amplification operation is difficult, and in particular, the residual voltage amplifier requires a high resolution of 11 bits Reference voltage instability problems have a major impact on overall ADC performance degradation.

4 (b) shows a case where different reference voltages are used for each channel in order to solve the problem of reference voltage instability which occurs when four channels share one reference voltage. However, when each channel uses a different reference voltage, another type of gain mismatch problem arises due to a reference voltage mismatch between channels.

In order to simultaneously solve the problem of the reference voltage instability and the gain mismatch caused by the structural characteristics of the conventional TI pipeline SAR, the ADC according to the embodiment of the present invention uses the reference voltage used for the amplification operation and the SAR operation with different specifications And the other two structures were separated.

Figure 5 illustrates an ADC according to an embodiment of the present invention using two separate reference voltages with separate specifications.

The reference voltage mismatch factor, which has the greatest influence on the overall ADC performance, is due to the reference voltage which requires high accuracy of 11 bits used in the residual voltage amplification. In the ADC according to the present invention, one residual voltage amplifier is shared, The same single reference voltage is used to perform the amplification operation, thereby minimizing the problem of the mismatch between the reference voltages. On the other hand, the reference voltage mismatch used in the SAR ADC blocks has a similar effect to that of the comparator offset mismatch of the low resolution flash ADC in the existing pipeline structure in terms of the overall ADC performance.

Thus, the ADC according to the present invention requires only a low reference voltage accuracy of 6 bits, unlike FIG. 4 (b), where each channel always has an 11-bit accuracy, which can be implemented without additional correction techniques.

Referring to FIG. 5, channel 1 and channel 3 of the first and second stages have different SAR operation timings, so that they can share one reference voltage. Channel 2 and channel 4 share the same reference voltage Sharing is possible. Therefore, the proposed ADC greatly reduced power consumption and area by using three reference voltages, one reference voltage with 11 bit resolution for residual voltage amplification and two reference voltages with 6 bit resolution for SAR operation .

Third, a single clock-edge sampling technique is used to solve the sampling timing mismatch problem.

In case of timing mismatch due to clock jitter in the polling edge of the sampling clock used for each channel in the conventional multi-channel T-I ADC, the sampling time of the entire ADC is not constant.

Meanwhile, since each channel of the 4-channel TI ADC according to the present invention performs a sampling operation at 1/4 of the entire operation speed, four sampling clocks having different phases are required for each channel, and a 150- And the sampling operation for each channel can be performed using the clock of 75 MHz generated by the clock generator. However, in the case of 75MHz clock, clock jitter occurs largely in the division process through digital logic circuit, which causes sampling timing mismatch in T-I structure. Therefore, the proposed ADC minimizes the effect of sampling timing mismatch between channels by synchronizing the polling edge of each channel sampling clock to the externally applied accurate clock of 150MHz. In addition, the layout of the sampling clock generation circuit is symmetrically arranged in the center of the SAR ADC of each channel, and the length of the clock metal line is minimized to minimize sampling timing mismatch due to parasitic capacitance and resistance components on the layout.

Hereinafter, a detailed circuit of the on-chip clock generation circuit according to an embodiment of the present invention will be described.

The ADC according to the present invention includes an on-chip clock generation circuit for fast frequency SAR ADC operation.

The ADC according to the present invention requires a 450 MHz high frequency clock signal for SAR operation. However, when a 150MHz clock for sampling and amplifying operation and a 450MHz clock for SAR operation are simultaneously applied from the outside, synchronization problems of two clock signals occur.

In recent years, asynchronous SAR ADCs have been proposed and solved in order to solve the problem of high frequency clocks externally applied, which can improve the operation speed of the entire SAR ADC by minimizing the latch operation time in the comparator have. However, when the input signal of the comparator is very small, the operation time of the comparator for determining one bit becomes long, and the asynchronous technique may cause an error in the ADC output digital code.

Therefore, in order to solve this problem, the ADC according to the present invention uses an on-chip clock generation circuit that generates a clock of a high frequency in itself in the ADC.

6 illustrates the structure and operation of an on-chip clock generation circuit included in an ADC according to an embodiment of the present invention.

Referring to FIG. 6, the on-chip clock generation circuit generates a clock signal having a frequency of about 450 MHz for a predetermined time. In particular, the on-chip clock generation circuit is configured to adjust the duty cycle in order to maximize the reference voltage sampling and pre- The designed clock has a duty cycle of about 70%, which alleviates design specifications for digital-to-analog converters (DACs), reference voltage generators, and preamplifiers, minimizing power consumption and area. In addition, unlike the asynchronous circuit technique, which requires a time delay circuit for each of the eight SAR ADCs, by using one on-chip clock generator circuit to simultaneously drive two SAR ADCs, .

A circuit design technique applied to each stage according to an embodiment of the present invention is as follows.

Figure 7 shows the first stage using two different specifications of reference voltages.

The first stage of the ADC according to the present invention adds two control logic circuits for the amplification operation and the SAR operation and a switch for selecting the reference voltage as shown in FIG. 7 in order to use two separate reference voltages. The reference voltage VRFP_AMP or VRFN_AMP for the amplifying operation or the reference voltage VRFP_SAR or VRFN_SAR for the SAR operation is selected according to the digital code outputted from the control logic circuit corresponding to each operation, a bootstrapping circuit was used to process the gate input signals of a wide range of _{-p p} without distortion.

Figure 8 shows a SAR ADC2 based on a range-scaling technique.

The ADC according to the present invention uses a range-scaling technique that receives an input signal of 1.6V _{p- p} in order to reduce the power consumption of the amplifier and lowers it to 0.8V _{p- p} from the second stage, Half of the range. Therefore, referring to FIG. 8, the second stage SAR ADC2 applies a method of sampling only the reference voltage to half of the capacitors in order to process the input signal.

This architecture has the disadvantage of requiring twice as much capacitance as a conventional SAR ADC, but it does allow for range-scaled signal processing without adding a reference voltage generator. In addition, as shown in FIG. 8, the capacitor having the smallest size uses two unit capacitors (CU) connected in series to use CU / 2 as a single unit capacitor, thereby reducing the total number of capacitors to one half and applying the range- Thereby preventing additional area increase.

Meanwhile, an ADC according to an embodiment of the present invention includes a high voltage gain amplifier using two pairs of input stages separated for memory effect removal.

Figure 9 shows two separate pairs of input stage based residual voltage amplifiers.

Referring to FIG. 9, the ADC according to the present invention employs a structure in which four channels share one residual voltage amplifier in order to solve the problem of an offset mismatch in the T-I structure. At the same time, using two separated pairs of input terminals, the reset time of the unused channel is secured, and the memory effect generated in the conventional amplifier sharing technique is eliminated. In addition, for the implementation of a residual voltage amplifier requiring a high voltage gain of 11 bit resolution, a gain-boosting technique is adopted in the first amplifier of the two-stage amplifier.

FIG. 10 shows SNDR and SFDR according to the sampling frequency of the ADC and SNDR and SFDR according to the input frequency according to the embodiment of the present invention.

Referring to FIG. 10 (a), when the sampling rate is increased to 160 MS / s at the 1 MHz differential input frequency, SNDR and SFDR according to the channel number are shown. While the sampling rate was increased to 160 MS / s, the ADC according to the present invention exhibited similar dynamic performance even when the number of channels increased. When operating at 150 MS / s or less, SNDR and SFDR were 54.5 dB and 65.5 dB. In particular, the ADC according to the present invention maintains SNDR of about 60 dB regardless of the number of channels at an operating speed of 100 MS / s or less, thereby exhibiting significantly improved interchannel matching characteristics as compared with the previously announced T-I ADC.

Referring to FIG. 10B, SNDR and SFDR are measured when the input frequency is increased to the Nyquist frequency at an operating speed of 100 MS / s and 150 MS / s when four channels are used. First, when the input frequency increases to 50 MHz at an operating speed of 100 MS / s, the SNDR and the SFDR of the ADC according to the present invention are maintained at 54.4 dB and 60.7 dB or more, respectively. On the other hand, at the operating speed of 150MS / s, when the input frequency increases to 40MHz, SNDR and SFDR are maintained at 50.5dB and 61.3dB, respectively.

The present invention relates to a 4-channel T-I pipelined SAR 11-bit 150 MS / s ADC using various analog circuit design techniques without additional correction techniques to solve offset, gain, and sampling timing mismatch problems occurring in existing T-I ADCs.

The ADC according to the present invention eliminates the input stage SHA circuit and employs a pipelined SAR structure using a SAR ADC as a sub-ADC instead of a conventional flash ADC, thereby achieving an inter-channel offset mismatch problem and an input commonly observed in the SHA- Solves the problem of limiting the signal frequency bandwidth.

In addition, by implementing the four signal channels to share one amplifier, it is possible to fundamentally eliminate various mismatch problems between channels by the residual voltage amplifier of MDAC, and by using two separated pairs of input stages, .

In order to solve the problem of reference voltage instability due to inter-channel signal interference, reference voltages having different specifications for SAR operation and amplification operation are separately used. In particular, all the channels use the same reference voltage Use minimizes gain mismatch problems. Channel-to-channel signal sampling timing mismatches are solved by synchronizing the externally applied 150 MHz accurate clock and polling edges by applying a single clock-edge sampling technique to the clocks used by the four channels.

The 450MHz clock for SAR operation generated inside the chip modulates the duty cycle to mitigate the design specifications of the DAC, reference voltage generator, and preamplifier, while at the same time minimizing power consumption.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and specific embodiments and drawings. However, it should be understood that the present invention is not limited to the above- And various modifications and changes may be made thereto by those skilled in the art to which the present invention pertains. Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

An 11-bit 150 MS / s pipelined SAR ADC based on a 4-channel time-interleaved architecture with minimal nonlinear errors

Claims (6)

A first SAR ADC consisting of four channels of SAR ADCs connected in parallel;
One residual voltage amplifier coupled to the output of the first SAR ADC and shared by four channels having two separate pairs of inputs;
A second SAR ADC consisting of four-channel SAR ADCs connected in parallel for sampling the residual voltage amplified in the residual voltage amplifier; And
And a digital calibration circuit for correcting an error of a digital output output from the first SAR ADC and the second SAR ADC,
The SAR operation timing of the SAR ADC corresponding to the first channel and the SAR ADC included in the first SAR ADC and the SAR ADC included in the second SAR ADC does not overlap and the SAR operation timing of the SAR ADC corresponding to the second channel and the fourth channel However,
The SAR ADCs corresponding to the first channel and the third channel share one reference voltage,
Wherein the SAR ADCs corresponding to the second channel and the fourth channel share another reference voltage. delete The method according to claim 1,
Wherein the residual voltage amplifier uses one reference voltage having a different specification than the reference voltage used by the SAR ADCs. The method according to claim 1,
Further comprising an on-chip clock generation circuit,
Wherein the on-chip clock generation circuit adjusts the duty cycle of the clock used in the SAR operation. The method according to claim 1,
Wherein the half of the input signal range input to the first SAR ADC is used as the input signal to the second SAR ADC. The method according to claim 1,
The first SAR ADC and the second SAR ADC perform a sampling operation at a quarter of the operating speed of the 4-channel pipeline SAR ADC and synchronize the falling edge of the sampling clock with an externally applied clock Channel pipelined SAR ADCs.

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