KR101686217B1 - Two-Channel Asynchronous SAR ADC - Google Patents

Two-Channel Asynchronous SAR ADC Download PDF

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KR101686217B1
KR101686217B1 KR1020160021353A KR20160021353A KR101686217B1 KR 101686217 B1 KR101686217 B1 KR 101686217B1 KR 1020160021353 A KR1020160021353 A KR 1020160021353A KR 20160021353 A KR20160021353 A KR 20160021353A KR 101686217 B1 KR101686217 B1 KR 101686217B1
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South Korea
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comparator
sar adc
resistor
sar
signal
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KR1020160021353A
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Korean (ko)
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이승훈
조영세
이기욱
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서강대학교산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

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  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The present invention relates to a two-channel asynchronous pipeline SAR ADC. According to the present invention, the SAR ADC device may comprise a semi-stable status detector circuit unit which, when a READY signal, which notifies that a comparators operation is completed, is not outputted in between a clock signal and a clock delay signal, generates a META signal, which determines the output of the comparator at a high logic level and reduces an output error due to the semi-stable status of the comparator. In addition, the present invention can let the SAR ADC of the first step and the second step share one comparator to minimize an offset mismatch between two channels without an additional correction technique. In addition, the present invention can minimize the chip area and switching power consumed within the DAC by using a technique to determine the lowest two bits through an R-2R resistance-based DAC for the SAR ADC of the second step and reducing the number of used capacitors.

Description

A dual-channel asynchronous pipeline SAR ADC {

The present invention relates to a SAR ADC, and more particularly to a dual channel asynchronous pipeline SAR ADC.

Recently, CMOS technology by process scaling continues to evolve into ultra-fine nano process technology such as 45nm and 28nm processes, and there is increasing interest in low power and small area design. On the other hand, research on the development of system-on-a-chip (SoC) in which various analog circuits and digital circuits are integrated on a single chip has been actively conducted. In such SoC applications, An analog-to-digital converter (ADC) capable of processing digital signals is indispensable.

Recently, various high performance devices such as smart TV, next generation TV system such as IPTV, and IEEE 802.16 based wireless interoperability for microwave access (WiMAX) satisfy 10 bit resolution and operating speed of over 160MS / s, Gt; ADC < / RTI > is essentially required. In a variety of systems, such as existing high-definition video display systems and wireless communication networks, pipelined ADCs were mainly used to minimize power consumption and area while meeting these high resolution qualities and increased bandwidth specifications.

On the other hand, in the case of a digital circuit-based successive-approximation register (SAR) ADC, not only the operation speed of the SAR logic is greatly improved due to the development of the process, but also the consumption of the digital circuit The power of SAR has been rapidly decreased, and the competitiveness of the process has been improved.

As such, SAR ADCs are becoming more and more competitive with nano processes, but their performance is limited by increasing resolution and circuit noise size, and their internal operating speed tends to increase exponentially with increasing operating speed . In order to overcome this shortcoming, it is possible to implement a high-speed ADC by applying a time-interleaved (TI) structure in which several low-speed same sub-ADCs are connected in parallel based on a pipeline structure. The performance of the entire ADC is degraded due to various nonlinear mismatches between the channels, such as offset, gain, and sampling timing, which are generated by the application. Therefore, in order to obtain a high resolution of 10 bits or more, it is necessary to minimize not only the noise of the constituent circuit but also the mismatch between various channels. In order to solve these channel mismatch problems, various correction techniques are necessary. However, since additional circuits are required and complicated, a variety of T-I pipeline ADCs based on various analog circuit design techniques have been recently announced.

In particular, in the case of T-I pipelined ADC, channel-to-channel offset mismatch is the main cause of performance degradation, whereas T-I structure SAR ADC is the main cause of degradation of channel-to-channel offset mismatch by comparator. A method of correcting the offset of the comparator by adding a variable capacitor to the output of the comparator to solve the interchannel offset mismatch by the comparator has been proposed, but this requires additional timing and digital circuitry for offset correction. In addition, offset correction techniques based on digital circuits require additional power consumption and area because large scale and complex circuits must be integrated in the chip.

Korean Patent Publication No. 10-2003-0056903 Korean Patent Publication No. 10-2010-0031831

Accordingly, an object of the present invention is to provide a dual channel asynchronous pipeline SAR ADC that minimizes nonlinear errors such as offset mismatch between channels and noise of a circuit without using a separate correction technique.

A dual-channel asynchronous pipelined SAR ADC according to an exemplary embodiment of the present invention includes a first SAR ADC and a second SAR ADC implemented as a dual channel, and the asynchronous SAR logic and the D / A converter (DAC) and is configured to share a first comparator, and the second stage is formed by a third SAR ADC and a fourth SAR ADC implemented as dual channels, respectively, asynchronous SAR logic and DAC And to share a second comparator.

And a residual voltage amplifier located between the first stage and the second stage for performing residual voltage amplification of the SAR ADC selected from the first SAR ADC and the second SAR ADC.

The apparatus may further include a clock timing circuit section for generating a clock signal.

Wherein the first comparator receives the clock signal, a clock delay signal delayed by a predetermined time of the clock signal, and a ready signal corresponding to the completion of the operation of the first comparator to sense the metastable state of the first comparator, And a first sensing circuit for outputting a sensing signal for allowing the first comparator to output a predetermined output when the first comparator detects the metastable state of the first comparator and to perform a next operation.

Wherein the second comparator receives the clock signal, a clock delay signal delayed by a predetermined time of the clock signal, and a ready signal corresponding to the completion of the operation of the second comparator to sense the metastable state of the second comparator, And a second sensing circuit for outputting a sensing signal for allowing the second comparator to output a predetermined output and to perform a next operation when the second comparator detects the metastable state of the second comparator.

The third SAR ADC and the fourth SAR ADC each include a capacitor-resistor hybrid DAC including a capacitor row for determining upper bits of a sampled input signal and a resistor row for determining lower bits of the sampled input signal, .

The resistor string is connected at one end to the common mode voltage input terminal by a switching element at each end thereof, a first resistor whose one end is connected by a switching element, the common mode voltage input terminal, the first reference voltage input terminal and the second reference voltage input terminal A second resistor and a third resistor, and a fourth resistor connecting the second resistor and the third resistor.

The first resistor, the second resistor, and the third resistor may have a resistance value twice that of the fourth resistor.

The capacitor-resistor hybrid DAC may compare the sampled input signal with the common mode voltage to determine the most significant bit.

A SAR ADC according to another embodiment of the present invention, a SAR ADC including an asynchronous SAR logic and a DAC, a comparator outputting a comparison result to the SAR logic comparing a voltage output from the DAC with a predetermined reference voltage, Lt; RTI ID = 0.0 > circuitry < / RTI >

Wherein the comparator receives the clock signal, a clock delay signal obtained by delaying the clock signal by a predetermined time, and a ready signal corresponding to the completion of the operation of the comparator, detects the metastable state of the comparator, And a sensing circuit for outputting a sensing signal for allowing the comparator to output a predetermined output and to perform a next operation when sensed.

The DAC may include a column of capacitors for determining the upper bits of the sampled input signal and a column of resistors for determining the lower bits of the sampled input signal.

According to the present invention, it is possible to reduce the output error due to the metastable state of the comparator, minimize the offset mismatch between two channels without a separate correction technique, reduce the number of capacitors used in the DAC, It is possible to minimize the switching power consumed.

1 is a diagram illustrating a configuration of a dual channel asynchronous pipeline SAR ADC according to an embodiment of the present invention.
2 is a diagram illustrating operation timing of each SAR ADC of a dual channel asynchronous pipeline SAR ADC according to an embodiment of the present invention.
3 is a diagram illustrating the structure of a shared comparator used in the first stage of a dual channel asynchronous pipeline SAR ADC according to the present invention.
4 is a diagram illustrating the structure of a shared comparator used in the second stage of a dual channel asynchronous pipeline SAR ADC according to the present invention.
5 is a detailed diagram illustrating the structure of a residual voltage amplifier used in a dual channel asynchronous pipeline SAR ADC according to the present invention.
6 is a diagram illustrating a DAC structure of a SAR ADC formed in a second stage of a dual channel asynchronous pipeline SAR ADC according to the present invention.
Fig. 7 is a timing chart comparing the timing of the synchronous SAR algorithm and the timing of the asynchronous SAR algorithm.
8 is a diagram provided to illustrate a metastable state sensing circuit applied to a dual channel asynchronous pipeline SAR ADC according to the present invention.
Figure 9 is a timing diagram provided to illustrate the principle of operation of the metastable state sensing logic.
10 is a diagram showing a result of metastable state detection of a comparator simulated according to the present invention.
11 is a view for explaining a case where one reference voltage is shared and a case where a reference voltage driving circuit is separated in a dual channel asynchronous pipeline SAR ADC according to the present invention.
12 is a diagram illustrating a dual channel asynchronous pipeline SAR ADC according to the present invention implemented on a chip.
Figure 13 is a diagram illustrating measured DNL and INL of the dual channel asynchronous pipeline SAR ADC of Figure 12;
14 is a diagram illustrating a measured FFT spectrum of the dual channel asynchronous pipeline SAR ADC of FIG. 12;
15 is a graph showing SNDR and SFDR measured according to a sampling frequency of a dual channel asynchronous pipeline SAR ADC according to the present invention.
16 is a diagram illustrating dynamic performance according to an input frequency of a dual channel asynchronous pipeline SAR ADC according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

1 is a diagram illustrating a configuration of a dual channel asynchronous pipeline SAR ADC according to an embodiment of the present invention.

The dual channel asynchronous pipelined SAR ADC illustrated in FIG. 1 is a dual channel, 10-bit, 200 MS / s 28 nm CMOS asynchronous pipelined SAR ADC that includes a 4-bit and 7-bit decision based two stage pipelined architecture, a dual channel TI structure, and an asynchronous SAR algorithm Are applied at the same time, and the following description will be made on the basis thereof. Of course, it should be understood that the number of bits determined by two SAR ADCs implemented in a dual channel in the first stage and the second stage may differ from those illustrated in FIG. 1 .

Referring to FIG. 1, a dual channel asynchronous pipeline SAR ADC (hereinafter referred to as a dual channel SAR ADC device) according to the present invention includes a first asynchronous SAR ADC 110a, a second asynchronous SAR ADC 110b, 120, a residual voltage amplifier 300, a third asynchronous SAR ADC 210a, a fourth asynchronous SAR ADC 210b, a second comparator 220, a digital correction logic 400, a clock timing circuit a clock timing circuit 500, a reference current, and a current & voltage generator 600.

The dual-channel SAR ADC device according to the present invention includes a first asynchronous SAR ADC 110a, a second asynchronous SAR ADC 110b and a first comparator 120 in a first stage, a third asynchronous SAR An ADC 210a, a fourth asynchronous SAR ADC 210b, and a second comparator 210. [

In FIG. 1, the first asynchronous SAR ADC 110a and the second asynchronous SAR ADC 110b located at the first stage are implemented as an asynchronous 4-bit SAR ADC, the third asynchronous SAR ADC 210a located at the second stage, 4 asynchronous SAR ADC 210b illustrate an example implemented with an asynchronous 7-bit SAR ADC. However, as described above, the number of bits of the asynchronous SAR ADC located in the first and second stages may vary according to the embodiment.

1, asynchronous SAR logic (Async. SAR logic) and a capacitor (not shown) are respectively connected to the first asynchronous SAR ADC 110a located at the first stage and the third asynchronous SAR ADC 210a located at the second stage, The second asynchronous SAR ADC 110b and the fourth asynchronous SAR ADC 210b, although it is shown as including a capacitor-resistor DAC (C-DAC) and a capacitor-resistor hybrid DAC Asynchronous SAR logic, C-DAC, and C & R-2R DAC.

1, the comparators 120 and 220 are connected to the first asynchronous SAR ADC 110a located at the first stage and the third asynchronous SAR ADC 210a located at the second stage, respectively. However, The first asynchronous SAR ADC 110a and the second asynchronous SAR ADC 110b located in the second stage share a first comparator 120 and the third asynchronous SAR ADC 210a and the fourth asynchronous SAR ADC 210b share the second comparator 220. And a residual voltage amplifier 300 located between the first and second stages is also shared by each SAR ADC implementing the dual channel.

The residual voltage amplifier 300 performs the residual voltage amplification of the SAR ADC selected from the first asynchronous SAR ADC 110a and the second asynchronous SAR ADC 110b to transfer the amplified residual voltage to the second stage.

The digital calibration circuit 400 performs a function of correcting the code error by the comparator offset.

The clock timing circuit 500 performs the function of generating and providing a clock associated with the operation of the dual channel SAR ADC device according to the present invention.

The reference current and reference voltage generator 600 performs the function of generating and providing a reference current and a reference voltage associated with operation of the dual channel SAR ADC device according to the present invention.

As described above, the dual-channel SAR ADC device according to the present invention is a pipelined SAR structure combining an asynchronous SAR ADC with a pipeline structure. In order to minimize various mismatches such as offset between dual channels, The first comparator 120, the second comparator 220, and the residual voltage amplifier 300 may be shared.

First, the V CM based switching scheme is applied to the first stage SAR ADCs 110a and 110b to remove the capacitor (2 3 C U ) occupying the largest area of each stage. In the first stage, 1.2V PP After receiving the input signal (V IN ), the second stage inputs the signal at 0.6V PP The power consumption by the residual voltage amplifier 300 can be reduced by reducing the design requirement of the residual voltage amplifier 300 by applying a range-scaling technique for reducing the residual voltage amplifier 300. [

Meanwhile, the second stage SAR ADCs 210a and 210b can additionally reduce the number of capacitors used through the V CM- based switching scheme and the C & R-2R DAC to determine the most significant bit and the least significant two bits .

The reference current and the reference voltage generator 600 are integrated in the chip to separately separate the reference voltage driving circuits used for the residual voltage amplification and the SAR operation to thereby generate the reference current and the reference voltage interference problem by three different switching operations By minimizing, the reference voltage interference and various mismatch problems between channels can be minimized.

Meanwhile, the SAR ADCs 110a, 110b, 210a, and 210b constituting each stage operate asynchronously, and therefore, a high-speed internal clock generation circuit for SAR operation is originally eliminated, thereby minimizing the area and power consumption. In addition, the addition of a simple-structured digital sense circuit can solve the meta-stable condition of the comparator.

2 is a diagram illustrating operation timing of each SAR ADC of a dual channel SAR ADC device according to an embodiment of the present invention.

FIG. 2 illustrates the SAR operation and the residual voltage amplification timing of a 10-bit 200 MS / s pipelined SAR ADC based on a dual channel TI structure. Since the two channels operate at 100 MS / s each with a time difference, And the detailed operation of each operation circuit block is as follows.

First, the input signals sequentially sampled on each of the two channels of the first stage are converted from the first-stage SAR ADCs 110a and 110b to higher-order 4-bit digital codes through the asynchronous SAR operation for 2.5 ns, which is a half- do. The residual voltage, which is the difference between the input signal and the reference voltage determined by the 4-bit code, is amplified four times by the residual voltage amplifier 300 applied with the range-scaling technique for 5 ns, which is a half period of the 100 MHz clock, Bit SAR ADCs 210a and 210b.

The second stage samples the residual voltage amplified from the first stage and then converts the residual voltage into the lower 7-bit code through the asynchronous SAR operation in the second stage 7-bit SAR ADCs 210a and 210b, It is possible to output a 10-bit digital code at a speed of / s.

Meanwhile, as illustrated in FIG. 2, the SAR operation of the first stage, the residual voltage amplification, and the SAR operation of the second stage proceed at the same timing, so that the problem of the reference voltage interference may occur. However, Channel SAR ADC device can solve the reference voltage interference problem fundamentally by dividing the reference voltage drive circuit into three.

Next, the comparators 120 and 220 shared by the SAR ADCs 110a, 110b, 210a and 210b forming the dual channel in the first and second stages of the dual channel SAR ADC device according to the present invention are described in more detail do.

In a typical T-I structured SAR ADC, each channel-specific comparator has offset of different magnitudes, which degrades linearity and limits the performance of the entire ADC. In order to solve this problem, various offset correction techniques have been proposed, but additional timing and digital circuits have been required.

The dual channel SAR ADC device according to the present invention can be implemented so that one comparator is shared between channels in order to reduce the offset mismatch between channels without a separate correction technique.

3 is a diagram illustrating the structure of a shared comparator used in the first stage of a dual-channel SAR ADC device according to the present invention.

Referring to FIGS. 1 and 3, the comparator 120 shared in the first stage may be configured as a latch of a two-stage structure without a preamplifier in order to minimize power consumption as illustrated in FIG. Although the switch may be used for the input of the comparator for the channel selection, in the first stage, in the process of amplifying the residual voltage generated after the SAR operation, the residual voltage may be distorted by the charge inflow generated when the switch for channel selection is turned off . In order to solve this problem, the input stage switch of the comparator 120 may be removed and configured as two pairs of input stages. Also, the memory effect that may occur by not resetting the input of the comparator 120 may be automatically removed during the sampling operation.

In the dual-channel SAR ADC device according to the present invention, since the first-stage SAR ADCs 110a and 110b of the pipeline are shared by one comparator 120 using two pairs of input stages, the performance degradation due to channel- Lt; / RTI >

However, when the offset size of the comparator 120 is within 1/2 LSB of 4 bits, the code error due to the offset can be designed to be able to be corrected through the digital calibration circuit 400.

The right graph of FIG. 3 shows that the standard deviation of the comparator offset size is 11.56 mV and the overall distribution is also stably distributed within 1/2 LSB (37.5 mV) of 4 bits as a result of Monte Carlo simulation of comparator offsets for 1000 samples Can be confirmed. Therefore, the code error due to the comparator offset can be corrected through the digital calibration circuit 400, so that it can be confirmed that the linearity of the entire ADC is not affected.

On the other hand, the comparator can generate a code error by the circuit internal noise until the comparison operation of the input signal is finally determined as a logic level digital value. The magnitude of the circuit internal noise can be equivalently expressed as the comparator input reference noise, and the code error of the comparator increases in proportion to the input reference noise magnitude.

Therefore, the dual-channel SAR ADC device according to the present invention applies a 4-bit and 7-bit pipeline structure, so that a code error caused by the offset and noise of the first-stage SAR ADC comparator can be corrected through a digital calibration circuit, In the case of the second-stage SAR ADC, the offset of the comparator circuit and the code error caused by the noise are not corrected, which can cause the degradation of the overall ADC performance. The performance constraint of the overall ADC due to the comparator circuit noise of the second stage SAR ADC can be summarized by Equation 1 below.

Figure 112016017837333-pat00001

In Equation (1), P S and P N denote the power of the input signal and the power of the total noise, respectively, and P Q , P C , P A and P COMP denote the quantization noise power, the kT / C noise power, Represents the input-referred noise power of the second stage comparator. From Equation (1), in order to obtain the performance required for a 10-bit TI ADC, P COMP is 1 mV RMS And the expected SNR is about 59.32dB.

4 is a diagram illustrating the structure of a shared comparator used in the second stage of a dual channel SAR ADC device according to the present invention.

Referring to FIG. 4, the size of the transistor used in the comparator 220 can be determined in consideration of the speed of the comparator and the magnitude of the input reference noise.

Table 1 below shows the comparison of the previously announced comparators with the operation speed, kick-back noise and input reference noise of the comparator according to the present invention, and the designed noise level of the comparator is 750 uV RMS .

[Table 1]

Figure 112016017837333-pat00002

As illustrated in Table 1, the comparator 220 used in the second stage in accordance with the present invention is capable of performing a low kick-back at a faster operating speed -back) noise and input-referred noise characteristics.

On the other hand, in the case of a pipelined ADC having a general TI structure, offset and gain mismatches of different sizes exist in the input stage SHA (Sampling-and-Hold Amplifier) and the first stage MDAC (Multiplying D / A Converter) These offset and gain mismatches are the main causes of the degradation of the overall ADC. Therefore, the offset and gain matching must be designed to be at least 10 bits in order to meet the performance requirements of a 10-bit T-I ADC. However, the conventional pipelined ADC requires two or more amplifiers in total, regardless of the number of bits to be determined for each channel for dual channel implementation. Thus, it is difficult to ensure compatibility with 10 bits or more without additional correction circuit, If each amplifier is used, efficiency is also low in terms of power consumption and area.

5 is a detailed view illustrating a structure of a residual voltage amplifier used in a dual channel SAR ADC device according to the present invention.

The dual channel SAR ADC device according to the present invention can solve the offset and gain mismatch problems and minimize the power consumption and area by sharing one residual voltage amplifier between the channels as illustrated in FIG. By using only one amplifier, the power consumption and area can be reduced to 50% compared to using two amplifiers. By applying range-scaling technique to lower the requirement of the amplifier, additional power consumption Can be reduced.

The residual voltage amplifier 300 according to the present invention shares two channels using two separate pairs of input terminals, and can eliminate the memory effect generated in the sharing technique by resetting unused channels. In addition, by using the overlapped clocks Q1MB and Q2MB in some sections, it is possible to solve the problems of the glitch and signal settlement time delay which may occur when the two input stage transistors are turned on and off at the same time. By using a two-stage amplifier structure, the nanometer process has a high voltage gain and a sufficient output signal swing even at shortened channel lengths and lower supply voltages. The first amplifier can use a folded cascode structure with a gain-boosting structure for high voltage gain, and a common-source structure can be applied to the second amplifier for sufficient output signal swing.

Referring again to FIG. 1, as described above, the dual-channel SAR ADC device according to the present invention adopts a two-stage pipeline structure sequentially determining 4 bits and 7 bits, respectively, 110a, and 110b, the V CM- based switching scheme that directly compares the sampled signal with the common mode voltage V CM without additional switching operations can be used to remove the largest capacitor, 2 3 C U , in the C-DAC.

In the case of the second-stage 7-bit SAR ADCs 210a and 210b, due to the number of unit capacitors exponentially increased by the number of bits to be processed compared to the first-stage 4-bit SAR ADCs 110a and 110b, Consumption also increases. In order to obviate such disadvantage, when a two-stage structure capacitor column using a separate weighted capacitor (C A ) is used for the second stage 7-bit SAR ADCs 210a and 210b, the size of C A is not an integral multiple of the unit capacitor, A mismatch occurs between the capacitor row and the lower capacitor row, which may also be a factor of other performance degradation.

In order to solve this problem, the dual-channel SAR ADC device of the present invention can implement the DAC of the SAR ADC formed in the second stage with a DAC composed of R-2R-based resistance series and a DAC composed of a capacitor series.

6 is a diagram illustrating a DAC structure of a SAR ADC formed in a second stage of a dual channel SAR ADC device according to the present invention.

SAR ADC (210a, 210b) formed in the second stage of the dual-channel SAR ADC system according to the present invention, the switching mechanism of the V CM based as one without applying the two-stage structure using a C A, illustrated in Figure 6, and Using the R-2R resistor-based DAC, the C & R-2R DAC structure, which determines the most significant bit and the least significant 2 bits, can be applied to reduce the number of capacitors while minimizing area and power consumption.

1 and reference to Figure 6, the second end 7-bit SAR ADC (210a, 210b) is a DAC through a switching mechanism of the V CM base to determine the most significant bit to directly compare V CM of the sampled signal with no additional switching operation The capacitor (2 6 C U ) occupying the largest area and determining the most significant bit can be removed. Capacitor column V CM because the switching operation based on the dynamic offset of the input common mode voltage of the comparator that the linearity deterioration ADC V CM change does not occur, the change in voltage across the capacitor compared to existing typical switching technique The power consumption of the DAC can be reduced by about 90% compared with the conventional one.

On the other hand, in the case of the technique of applying the six reference voltages generated by using the previously disclosed resistance column, a constant static current flows through the resistance column, and unnecessary power is consumed accordingly.

In contrast, the SAR ADCs 210a and 210b according to the present invention include a capacitor-resistor hybrid DAC including an R-2R DAC 211 formed of a resistive column having an R-2R structure and a capacitor DAC 212 formed of a capacitor column can do.

The R-2R DAC 211 determines the low order bits of the sampled input signal and the capacitor DAC 212 determines the high order bits of the sampled input signal. For example, the most significant bit among the 7 bits determined by the SAR ADCs 210a and 210b is determined by a V CM -based switching scheme, the lower 2 bits are determined in the R-2R DAC 211, and the remaining 4 bits are stored in the capacitor DAC 212).

When the R-2R DAC 211 with the R-2R resistance based structure is used, the same voltage is applied across the R-2R DAC 211 through the switch after the asynchronous SAR operation, (2 5 C U and 2 4 C U ) of the capacitor row by determining the least significant two bits using the reference voltage generated by the R-2R DAC 211 while eliminating unnecessary power consumption by the current, Can be additionally removed. Accordingly, the 7-bit SAR ADCs 210a and 210b of the second stage using the two techniques according to the present invention, compared to a general 7-bit SAR ADC using a total of 128 capacitors, use only 16 capacitors, Can be reduced.

On the other hand, when a reference voltage generator is added to process a range-scaled input signal in the second-stage 7-bit SAR ADCs 210a and 210b, the power consumption and area increase sharply. Therefore, the second stage 2 to 4 C U capacitor rows 212 of the 7-bit SAR ADC (210a, 210b) It is possible to process an input signal that is range-scaled efficiently without additional reference voltage.

More particularly R-2R DAC (211) is a common-mode voltage V CM first resistor 2111 having one end connected by the switching element to an input terminal, the common-mode voltage V CM input terminal, a first reference voltage input terminal (V REF +) and a second reference voltage input terminal (V REF -) the second resistor 2112 and the third resist 2113, and connected to the second resistor 2112 and the third resist 2113 is one end is connected by a respective switching element to A fourth resistor 2114, The first resistor 2111, the second resistor 2112 and the third resistor 2113 may have a resistance value twice that of the fourth resistor 2114. And R-2R DAC (211) in order to be further processed a 1-bit in the column between the capacitor 212 and the R-2R DAC (211) -2R R U U It is possible to additionally add the resistance string of

Referring to the timing chart of the 7b SAR ADC of the second stage shown in FIG. 2, the operation of the DAC of the second stage 7b SAR ADC in the residual voltage sampling period will be described.

Referring to FIGS. 2 and 6, the V CM switch connected to the V OUT - side of FIG. 6 is opened to terminate the residual voltage sampling and the bottom plate of all the capacitor rows including the R-2R DAC 211 -plate) can be connected to the common-mode voltage V CM . Then, the SAR Op. (SAR Operation) is started. At this time, the sampled input signal of the top plate is directly compared with the common mode voltage V CM of the bottom plate by the V CM switching technique The most significant bit (MSB) value can be determined.

Then, the value output through the comparator 220 enters the asynchronous SAR logic as illustrated in FIG. 1, and the switch operation of the capacitor DAC 212 and the R-2R DAC 211 is determined according to the output value of the asynchronous SAR logic do. Here, the switching operation of the R-2R DAC 211 is the same as the switching operation of the capacitor row except for input signal sampling switching.

7 is a diagram provided for comparing the timing of the synchronous SAR algorithm and the timing of the asynchronous SAR algorithm.

In the case of the N-bit SAR ADC of the general synchronization type, as shown in FIG. 7 (a), N conversion processes having the same period after the sampling operation from the MSB to the LSB are required. The overall period is determined based on the longest time of the delay time and the reference voltage settling time.

In the case of an internal clock designed considering the longest period, some signals have an IDLE state waiting for a clock of the next signal, which limits high-speed operation. On the other hand, in the case of the asynchronous SAR ADC, there is no such IDLE state because it performs the next operation together with the completion of each operation, which is therefore advantageous for high-speed operation.

When a synchronous SAR algorithm is applied to a dual channel SAR ADC device according to the present invention, the first stage 4-bit SAR ADC and the second stage 7-bit SAR ADC each require a clock signal having a high frequency of 1.6 GHz and 1.4 GHz, respectively Do. However, when a 100 MHz clock for sampling and amplification operation and a high frequency clock for SAR operation are simultaneously applied from the outside, a synchronization problem of two clock signals occurs. Clock generation with high frequencies of 1.6 GHz and 1.4 GHz results in increased power consumption and area.

Therefore, the dual-channel SAR ADC according to the present invention not only realizes a high-speed SAR operation without generating a high-frequency clock itself by applying the asynchronous SAR algorithm at the timing shown in FIG. 7 (b) It is desirable to remove the area completely and minimize power consumption.

On the other hand, a SAR ADC based on a comparator will take a long time until the output of the comparator is finally determined as a logic level value due to the metastable state generated when a very small input signal is applied to the comparator, And performance. Conventionally, a ramp signal generator is added to reduce the comparator metastability problem, and a logic is used to generate a flag when a metastable state occurs in the comparator. However, this has the problem of increasing area and power consumption due to the addition of complicated digital circuits.

In order to solve this problem, the comparator according to the present invention includes a metastable state sensing circuit having a simple structure as shown in FIG. 8, thereby reducing the output error due to the metastable state of the comparator.

FIG. 8 is a diagram for explaining a metastable state sensing circuit applied to a dual channel SAR ADC device according to the present invention, and FIG. 9 is a timing diagram provided to explain the operation principle of the metastable state sensing logic.

8 and 9, the comparator 220 according to the present invention includes a clock signal CKL output from the clock timing circuit 500, a clock delay signal CKL_D delayed by a predetermined time of CKL, The comparator 220 receives the ready signal READY corresponding to the completion of the operation of the comparator 220 and senses the metastable state of the comparator 220. When the comparator 220 senses the metastable state of the comparator 220, And a meta-stable detection logic 221 for outputting a detection signal META to be performed.

For example, as shown in FIG. 9, when the READY signal does not become 0 between CKL and CKL_D but remains 1, the NAND gate 222 of FIG. 8 outputs 0 to turn on the connected PMOS By forcing the output of the comparator 220 to be 1, the comparison operation can be terminated and the next comparison operation can be performed.

As described above, the sensing circuit unit 221 for detecting the meta-stable state of the comparator according to the present invention can reduce the output error due to the metastable state of the comparator by using the buffer having the variable delay time and the simple logic have.

10 is a diagram showing a result of metastable state detection of a comparator simulated according to the present invention.

As shown in FIG. 10, the sensing circuit unit 221 according to the present invention confirms that when the READY signal indicating completion of the operation of the comparator is not output for a predetermined time, the META signal for determining the output of the comparator to a high logic level is generated.

On the other hand, a typical pipelined SAR ADC may contain a SAR ADC with high-speed operation and a residual voltage amplifier that requires high accuracy, so that different operation modes may overlap and some reference reset operation may be unstable.

11 is a view for explaining a comparison between a case where one reference voltage is shared and a case where a reference voltage driving circuit is separated in a dual channel SAR ADC device according to the present invention.

Referring to FIG. 11, in the dual channel SAR ADC device according to the present invention, the reference voltage used in the residual voltage amplification is required to have a high accuracy of 10 bits. However, as shown in FIG. 11 (a) The SAR operation causes the problem of the reference voltage interference, and there is a restriction on the generation of the reference voltage having a high accuracy of 10 bits. On the other hand, in the case of separately designing the final driving circuit among the reference voltages used in the SAR operation and the residual voltage amplification as shown in FIG. 11 (b), the reference voltage interference due to the fast switching operation of the SAR ADC is minimized, Voltage can be generated.

Therefore, the dual channel SAR ADC device according to the present invention preferably separates the reference voltage driving circuit for the 4-bit SAR operation, the residual voltage amplification in the first stage, and the 7-bit SAR operation in the second stage, respectively. In order to amplify the residual voltage, a reference voltage driving circuit having a high resolution of 10 bits and a reference voltage driving circuit having a resolution of 4 bits and 7 bits are operated for SAR ADC operation, thereby generating reference voltage interference and interchannel gain inconsistency Problems can be reduced. The reference voltage generation circuit can be shared to optimize the area and power consumption.

FIG. 12 illustrates a dual channel SAR ADC device according to the present invention implemented on a chip, FIG. 13 illustrates a measured differential non-linearity (DNL) and an integral non- linearity, and FIG. 14 is a diagram illustrating a measured FFT spectrum of the dual channel SAR ADC device of FIG.

The dual channel SAR ADC device according to the present invention illustrated in FIG. 12 is a 10 bit 200 MS / s pipelined SAR ADC, fabricated in a 28 nm CMOS process, with a total area of 0.23 mm 2 . In the layout, as shown in FIG. 12, the most important residual voltage amplifier for operation is arranged in the center, and the first and second SAR ADCs of the dual channel are symmetrically arranged. In order to minimize capacitor mismatch, capacitors of two channels are alternately mixed and placed in the center of the chip.

According to the dual channel SAR ADC device of the present invention illustrated in FIG. 12, MOS on-chip capacitors of the level of 890 pF are integrated in the boundaries of the idle spaces except for each operation circuit block, The noise of the reference voltage and the interference between the blocks can be minimized. It consumes 6.7mW when the reference voltage generator is included at 1.0V analog and digital power supply voltage, 200MS / s and consumes 3.6mW when the reference voltage generator is not used.

The measured DNL and INL for the dual channel SAR ADC device according to the present invention illustrated in FIG. 12 were found to be 0.71 LSB and 0.70 LSB, respectively, as shown in FIG.

14 shows a typical signal spectrum of a dual channel SAR ADC device according to the present invention measured at 4 MHz input frequency, 25 MS / s, 160 MS / s and 200 MS / s operating speed. It can be seen that no tone occurs at the fs / 2 point at all three operating speeds, and it can be seen that the offset mismatch problem between channels is solved properly by the comparator sharing technique between two channels.

FIG. 15 is a graph showing signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) measured according to a sampling frequency of a dual channel SAR ADC device according to the present invention, FIG. 3 is a graph illustrating dynamic performance of a dual-channel SAR ADC according to an embodiment of the present invention; FIG.

Figure 15 is a graph summarizing the measured dynamic performance of a dual channel SAR ADC device in accordance with the present invention showing SNDR and SFDR at a 4MHz differential input frequency as the operating speed increases from 25MS / s to 200MS / s . SNDR and SFDR are maintained at 51.44dB and 62.51dB, respectively, up to the operation speed of 160MS / s, and the performance is degraded by about 3dB from 180MS / s or more.

FIG. 16 shows the dynamic performance of the dual channel SAR ADC device according to the present invention as the input frequency increases at an operating speed of 160 MS / s. Even though the TI structure is applied, the SNDR and SFDR at the Nyquist input frequency The performance is maintained at 51.07dB and 60.94dB respectively. Also, the effective resolution bandwidth (3 dB ERBW) is measured at 100 MHz, which means that there is no significant performance degradation at high input frequencies above Nyquist.

The measured performance results of the dual channel SAR ADC device according to the present invention are summarized in Table 2. Table 3 compares the performance of the previously announced T-I ADC with the proposed dual channel SAR ADC device. The dual-channel SAR ADC device according to the present invention maintains SNDR of 51 dB or more at Nyquist input frequency without using a separate calibration technique in the T-I structure, and shows excellent performance in terms of FoM (figure of merit).

[Table 2]

Figure 112016017837333-pat00003

[Table 3]

Figure 112016017837333-pat00004

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, And all changes and modifications to the scope of the invention.

Claims (8)

delete The first stage is formed such that the first SAR ADC and the second SAR ADC implemented as dual channels each include asynchronous SAR logic and a DAC and share a first comparator and the second stage is formed by a third SAR ADC And the fourth SAR ADC are configured to include the asynchronous SAR logic and the DAC, respectively, and share the second comparator,
A residual voltage amplifier located between the first stage and the second stage for performing a residual voltage amplification of the SAR ADC selected from the first SAR ADC and the second SAR ADC,
And a clock timing circuit portion for generating a clock signal,
Wherein the first comparator receives the clock signal, a clock delay signal delayed by a predetermined time of the clock signal, and a ready signal corresponding to the completion of the operation of the first comparator to sense the metastable state of the first comparator, And a first sensing circuit for outputting a sensing signal for causing the first comparator to output a predetermined output and to perform a next operation when the first comparator senses a metastable state of the first comparator,
Channel asynchronous pipeline SAR ADC. The first stage is formed such that the first SAR ADC and the second SAR ADC implemented as dual channels each include asynchronous SAR logic and a DAC and share a first comparator and the second stage is formed by a third SAR ADC And the fourth SAR ADC are configured to include the asynchronous SAR logic and the DAC, respectively, and share the second comparator,
A residual voltage amplifier located between the first stage and the second stage for performing a residual voltage amplification of the SAR ADC selected from the first SAR ADC and the second SAR ADC,
And a clock timing circuit portion for generating a clock signal,
Wherein the second comparator receives the clock signal, a clock delay signal delayed by a predetermined time of the clock signal, and a ready signal corresponding to the completion of the operation of the second comparator to sense the metastable state of the second comparator, And a second sensing circuit for outputting a sensing signal for causing the second comparator to output a predetermined output and to perform a next operation when a metastable state of the second comparator is sensed,
Channel asynchronous pipeline SAR ADC. 3. The method according to claim 2 or 3,
The third SAR ADC and the fourth SAR ADC,
A capacitor-resistor hybrid DAC, each of which includes a capacitor row that determines upper bits of the sampled input signal and a resistor row that determines a lower bit of the sampled input signal,
The resistance column
A first resistor whose one end is connected to the common mode voltage input terminal by a switching element,
A second resistor and a third resistor, one end of which is connected to the common mode voltage input terminal, the first reference voltage input terminal, and the second reference voltage input terminal,
And a fourth resistor connecting the second resistor and the third resistor
/ RTI >
Wherein the first resistor, the second resistor, and the third resistor have a resistance twice that of the fourth resistor. 5. The method of claim 4,
The capacitor-resistor hybrid DAC
And comparing the sampled input signal with the common mode voltage to determine a most significant bit. SAR ADCs, including asynchronous SAR logic and DACs,
A comparator for comparing the voltage output from the DAC with a predetermined reference voltage and outputting a comparison result to the SAR logic;
A clock timing circuit for generating a clock signal for operation of the comparator,
Lt; / RTI >
The comparator comprising:
A clock delay signal delayed by a predetermined time of the clock signal, and a ready signal corresponding to the completion of the operation of the comparator, and detects a metastable state of the comparator. When the metastable state of the comparator is sensed, A sensing circuit for outputting a sensing signal for causing a predetermined output to be output and performing the next operation;
And the SAR ADC. The method of claim 6,
The DAC includes:
A capacitor row for determining upper bits of the sampled input signal and a resistor row for determining lower bits of the sampled input signal,
The resistance column
A first resistor whose one end is connected to the common mode voltage input terminal by a switching element,
A second resistor and a third resistor, one end of which is connected to the common mode voltage input terminal, the first reference voltage input terminal, and the second reference voltage input terminal,
And a fourth resistor connecting the second resistor and the third resistor
/ RTI >
Wherein the first resistor, the second resistor, and the third resistor have a resistance twice that of the fourth resistor. 8. The method of claim 7,
The DAC
And compares the sampled input signal with the common mode voltage to determine a most significant bit.
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