JP2001244810A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable operation with a reference clock of low frequency, to accurately make phase comparison, and to increase the phase precision of a VCO output. SOLUTION: A digital VCO comprises a 1st n-bit register (n: integer larger than 2) operating with a reference clock and an n-bit adder 1 adding the output bus value of the 1st n-bit register 2 and an input value determining an oscillation frequency, and inputs the output bus value of the n-bit adder 1 to the 1st n-bit register 2; and the phase comparison output composed of successive binary mean values outputted by the 1st n-bit register 2 in the phase comparison timing is inputted to the n-bit adder 1 as the input determining the oscillation frequency. Further, the MSBs of two successive output bus values of the 1st n-bit register 2 are compared and the absolute values of the 1st n-bit register 2 are compared to control the delay quantity of the VCO output according to the comparison results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention compares the phase of a clock reproduced from a variable frequency oscillator with a signal reproduced from a medium on which digital data is recorded, such as an optical disk, and controls the oscillation frequency of the variable frequency oscillator. The present invention relates to a digital PLL circuit for obtaining a reproduced clock phase-synchronized with a signal reproduced from a medium.

[0002]

2. Description of the Related Art As a field to which the present invention can be applied, the case of a compact disk (hereinafter abbreviated as CD) will be described below.
In the CD format, the recording information is written in EFM (8-14).
Modulation). At the time of reproduction, a phase locked loop (PLL) circuit that compares the phase of the EFM signal with the clock of the output of the variable frequency oscillator and generates a reproduction clock synchronized with the EFM signal is used. When this PLL circuit is constituted by a digital circuit, it is necessary to digitize the variable frequency oscillator.

FIG. 4 shows a first example of a conventional digital variable frequency oscillator. In FIG. 4, reference numeral 14 denotes a counter. A conventional digital variable frequency oscillator has a counter 14
Is used to obtain a variable frequency oscillator output by variably dividing a reference clock at an arbitrary frequency division ratio.

FIG. 5 shows a digital variable frequency oscillator using a pulse swallow method as a second example of a conventional digital variable frequency oscillator. In FIG. 5, reference numeral 15 denotes a frequency dividing circuit for dividing the reference clock by 1 / n and 1 / (n + 1) to obtain a variable frequency oscillator output, and 16 denotes a swallow counter.

[0005] The digital variable frequency oscillator having the above-described configuration uses a frequency dividing circuit 1 based on the output of the swallow counter 11.
In this system, the frequency resolution is obtained by switching the division ratio of 0 to two stages of 1/8 and 1/9.

FIG. 6 shows a time chart of a second example of the conventional digital variable frequency oscillator. This time chart shows that the frequency division ratio of the swallow counter 11 is 1/8 and 1/9.
2 shows a reference clock, a variable frequency oscillator output, and a swallow counter output when the ratio is set to 1: 1. The average of the output of the variable frequency oscillator between the part divided by 1/8 and the part divided by 1/9 is as follows. That is, variable frequency oscillator output = (16/17) · (reference clock / 8)

[0007]

However, in the first example of the conventional digital variable frequency oscillator, in order to obtain a frequency resolution of 1 / a in the output of the variable frequency oscillator, a frequency a times as large as the output of the variable frequency oscillator is required. When the output frequency of the variable frequency oscillator is high and a fine frequency resolution is required, a reference clock having a very high frequency is required, which makes it difficult to generate a clock.

The second example of the conventional digital variable frequency oscillator is a swallow counter 1 as described above.
In this system, the frequency division ratio of the frequency dividing circuit 10 is switched in two stages by the output of 1 to obtain frequency resolution. As can be seen from FIG. 6, the digital variable frequency oscillator itself has jitter and constitutes a digital PLL circuit. In this case, there is a problem that the phase comparison cannot be performed accurately.

The present invention solves the problems in the first and second examples of the conventional digital variable frequency oscillator. The present invention provides a digital PLL circuit using the first example of the conventional digital variable frequency oscillator. The same frequency resolution as that of the first example can be obtained with a reference clock having a low frequency, and the phase comparison can be performed more accurately than the digital PLL circuit using the second example of the above-mentioned conventional digital variable frequency oscillator. It is intended to realize a digital PLL circuit.

[0010]

In order to solve this problem, a digital PLL circuit according to a first aspect of the present invention comprises a first n-bit register (where n is 2) operating on a reference clock.
Integer) and an n-bit adder for adding the output bus value of the first n-bit register and the input value for determining the oscillation frequency. The output bus value of the n-bit adder is represented by the first n As an input to the bit register, the MSB of two consecutive output bus values of the first n-bit register is compared, and the absolute value of two consecutive output bus values of the first n-bit register is compared. , Based on the comparison result of the MSB of two consecutive output bus values of the first n-bit register and the comparison result of the absolute value of two consecutive output bus values of the first n-bit register. Using a digital variable frequency oscillator that optimally controls the delay amount of the MSB of the output bus value of the bit register and uses the MSB delay signal of the output bus value of the first n-bit register as the variable frequency oscillator output, And wherein the input of the phase comparison output consisting of the mean value of two output buses value continuous output by the first n-bit register in the grayed as an input value for determining the oscillation frequency to n-bit adder.

A digital PLL circuit according to a second aspect of the present invention includes a first n-bit register (n is an integer of 2 or more) operated by a reference clock, an output bus value of the first n-bit register, and oscillation. An n-bit adder for adding an input value for determining a frequency, and using an output bus value of the n-bit adder as an input to a first n-bit register,
The MSBs of two consecutive output bus values of the bit register are compared, the absolute values of two consecutive output bus values of the first n-bit register are compared, and the consecutive two output bus values of the first n-bit register are compared. Delay amount of the MSB of the output bus value of the first n-bit register based on the comparison result of the MSB of the output bus values and the comparison result of the absolute value of two consecutive output bus values of the first n-bit register Using a digital variable frequency oscillator that uses the MSB delay signal of the output bus value of the first n-bit register as the variable frequency oscillator output, and provides an edge detector that detects an edge of the phase comparison target signal; A second n-bit register which operates with a reference clock and receives an output of the first n-bit register as an input is provided. And an average for calculating an average value of the output values of the first and second n-bit latches. The first and second n-bit latches respectively hold the output of the n-bit register in response to the output of the edge detector. Conversion circuit,
The output of the averaging circuit is input to an n-bit adder as an input value for determining the oscillation frequency.

An MSB comparing circuit for comparing the MSBs of the output bus values of the first and second n-bit registers to detect a match / mismatch is provided, and an output bus value of the first and second n-bit registers is provided. An absolute value comparison circuit for detecting a magnitude relationship between absolute values is provided. A logic circuit for logically synthesizing a comparison result by the MSB comparison circuit and a comparison result by the absolute value comparison circuit is provided. a D flip-flop for providing a selector circuit for selecting either the MSB of the output bus value of the n-bit register or the MSB of the output bus value of the second n-bit register, and holding the output of the selector circuit in response to a reference clock And the output of the D flip-flop is used as the variable frequency oscillator output. The absolute value is compared, for example, in the 2 'complement,
7FF = -1, 7FE = -2, $ 400 = -102
This is because it is considered 4.

By adopting the configuration of claim 1 or 2, a digital variable frequency oscillator operating at a frequency lower than a times as a reference clock can be realized even when the frequency resolution is desired to be 1 / a. Further, since the average of two consecutive output bus values of the first n-bit register at the phase comparison timing is used as the phase comparison output, the phase comparison can be accurately performed.

Further, based on the comparison result of the MSB of two consecutive output bus values of the first n-bit register and the comparison result of the absolute value of two consecutive output bus values of the first n-bit register. Since the amount of delay of the MSB of the output bus value of the first n-bit register is optimally controlled, the phase accuracy of the output of the variable frequency oscillator can be improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital PLL circuit according to an embodiment of the present invention. In FIG. 1, 1 is an n-bit adder (n is an integer of 2 or more), 2
Is a first n-bit register, 3 is a second n-bit register, 4 is a second n-bit latch, 5 is an edge detector, 6
Is a first n-bit latch, 7 is an averaging circuit, 8 is a digital filter, 9 is an absolute value comparing circuit, 10 is an MSB comparing circuit, 11 is an AND circuit, 12 is a selector circuit, and 13 is D
It is a flip-flop.

In the above configuration, the n-bit adder 1 adds the digital variable frequency oscillator input value output from the digital filter 8 for determining the oscillation frequency and the output bus value of the first n-bit register 2. Has functions.

The first n-bit register 2 operates with a reference clock, has a function of holding an output bus value of the n-bit adder 1, and has an MSB (Most Significa) of the output bus value.
nt Bit (most significant bit) is selectively used as a variable frequency oscillator output. Similarly, the second n-bit register 3 operates with the reference clock and has a function of holding the output of the first n-bit register 2, so that the output bus value of the n-bit adder 1 becomes equal to the first bus value. n-bit register 2
The output is delayed by one reference clock.
The MSB delay signal of the output bus value of the second n-bit register 3 is also selectively used as the variable frequency oscillator output.

The edge detector 5 has a function of detecting, for example, a rising edge of an EFM signal as a phase comparison target signal as a phase comparison timing.

The first n-bit latch 6 has a function of holding the output bus value of the first n-bit register 2 in response to the rising edge of the EFM signal detected by the edge detector 5. The second n-bit latch 4 has a function of holding the output bus value of the second n-bit register 3 in response to the rising edge of the EFM signal detected by the edge detector 5. As a result, the first and second n-bit latches 6 and 4 provide the phase comparison timing (EF
At the rising edge of the M signal, two consecutive output bus values of the first n-bit register 2 are held. Specifically, the output bus value of the first n-bit register 2 at the phase comparison timing and the output bus value of the first n-bit register 2 one reference clock earlier than the output bus value are held.

The averaging circuit 7 includes a first n-bit latch 6
Has the function of calculating the average value of the output value of the first n-bit register 2 and the output value of the second n-bit latch 4, and calculates the average value of the two consecutive output bus values of the first n-bit register 2 at the phase comparison timing. Will generate a phase comparison output.

The digital filter 8 receives the phase comparison output from the averaging circuit 7 as an input, and performs necessary processing such as gain adjustment, high-pass low-pass filtering, and low-pass integration on the phase comparison output. After that, it is provided to the n-bit adder 1 as a digital variable frequency oscillator input value for determining the oscillation frequency.

The absolute value comparison circuit 9 receives the output bus value of the first n-bit register 2 as input B, the output bus value of the second n-bit register 3 as input A, and outputs the first and second n bits.
The magnitude relationship between the absolute values of the output bus values of the bit registers 2 and 3, that is, the magnitude relationship between the inputs A and B is detected. When A <B, that is, the output bus value of the preceding first n-bit register 2. When the output bus value of the second n-bit register 3 is smaller, the output is set to “H”. The absolute value is compared with, for example, the 2 ′ complement,
This is because F = −1, 7FE = −2, ‥‥‥ 400 = −1024.

The MSB comparison circuit 10 receives the MSBs of the output bus values of the first and second n-bit registers 2 and 3 as inputs and detects a match / mismatch by comparing the two MSBs. At this time, the output is set to “H”.

The AND circuit (logic circuit) 11 logically combines the comparison result of the absolute value comparison circuit 9 and the comparison result of the MSB comparison circuit 10, and in this example, outputs the absolute value comparison circuit 9 and the MSB comparison circuit 10. And the output is set to "H" when A <B and when they do not match.

The selector circuit 12 includes first and second n
The MSB of each output bus value of the bit registers 2 and 3 is input, and when the output of the AND circuit 11 is “H”, the MSB of the output bus value of the second n-bit register 3 is selected.
When the output of the circuit 11 is "L", the MSB of the output bus value of the first n-bit register 2 is selected.

The D flip-flop 13 receives the output of the selector circuit 12 as a D input, receives a reference clock as a clock input, and holds the output of the selector circuit 12 in response to the reference clock. Therefore, in this part, the MSB of the output bus value of the first or second n-bit register 2 or 3 is 1
The reference clock will be delayed.

With the above configuration, the digital variable frequency oscillator in this digital PLL circuit has the first
M of two consecutive output bus values of the n-bit register 2
SB, and the absolute values of two consecutive output bus values of the first n-bit register 2 are compared.
MSB of two consecutive output bus values of bit register 2
And the delay amount of the output of the variable frequency oscillator is set to one of the reference clocks or the two reference clocks, based on the comparison result of (i) and the comparison result of the absolute values of the two consecutive output bus values of the first n-bit register 2. Control will be optimal.

The digital PLL circuit having the above-described configuration operates in a first n-bit register 2 operating with a reference clock.
And the input value for determining the oscillation frequency are added by an n-bit adder 1, and the output bus value of the n-bit adder 1 is
The data is input to a first n-bit register 2 that operates on the reference clock. Then, the delay signal of the MSB of the output bus value of the first n-bit register 2 is selectively output as a variable frequency oscillator output.

For example, if the output of the variable frequency oscillator is 10 MHz
z. To obtain a frequency resolution of 1/256 for this clock (variable frequency oscillator output), the value input to the n-bit adder 1 is 256. For example, if the phase resolution required for the output of the variable frequency oscillator is 1/8, the frequency of the reference clock is set to 80 MHz, which is eight times the output of the variable frequency oscillator. In this case, n = 11 (256 × 8 = 20) because 256 additions make one cycle with eight additions.
48 = 2 ¹¹ ).

Next, the operation of the circuit will be described with reference to the time chart of FIG. Hereinafter, the operation will be described on the assumption that the MSB of the first n-bit register 2 is assumed to be a variable frequency oscillator output. When the frequency division ratio is 256, when the digital variable frequency oscillator input value is 100h (h means hexadecimal notation), the output bus value of the first n-bit register 2 is 000h, 100h, 200h , 30
0h, 400h, 500h, 600h, 700h, 00
0h,... Every 100h for each reference clock, and the output of the variable frequency oscillator (first n-bit register 2
Is the same as the output obtained by dividing the reference clock by 8, and is always 4 clocks “L” and 4 clocks “H”.

Next, considering the case where the frequency division ratio is 255, in this case, the input value of the digital variable frequency oscillator is 0.
FFh, and the output bus value of the first n-bit register 2 is 000h, 0FFh, 1FEh, 2FDh, 3FC
h, 4FBh, 5FAh, 6F9h, 7F8h, 0F7
h,... and increase by 0FFh for each reference clock,
In the output of the variable frequency oscillator (MSB of the output bus value of the first n-bit register 2), a case appears in which the clock becomes “L” or “H” for 5 clocks. In this case, the average frequency of the output of the variable frequency oscillator is 10 MHz × (255/256) ≒ 9.961 MHz in this example. That is, the frequency resolution is 1/256.

In the above description, the case where the input values of the digital variable frequency oscillator are 256 and 255 has been described. However, there are also cases where the input values are 257. In this case, when the clock becomes "H" or "L" for three clocks. Appears. In this case, the average frequency of the output of the variable frequency oscillator is 257/256. Also, the digital variable frequency oscillator input value is
Not limited to the above 255, 256, and 257, but changes according to the phase relationship between the rising edge of the EFM signal detected by the edge detector 5 and the output of the variable frequency oscillator.

Next, the phase comparison will be considered. Input E
It is assumed that the FM signal is input at the position shown in FIG. However, at which position in the timing (A) the input EFM
It is impossible to determine whether or not there is an edge (rising) of the signal as long as the phase comparison is performed digitally.

Thus, it is apparent that the most preferable approximation is to consider the timing at the center of (A). However, even when the edge is considered to be at the center, it is not desirable to compare the phase of the edge of the input EFM signal with the output of the variable frequency oscillator itself. This is because, as described above, the output of the variable frequency oscillator is quantized in terms of phases such as 5 clocks “L” and 4 clocks “H” and includes jitter.

Therefore, in the present embodiment, two consecutive 2 bits of the first n-bit register 2 at the phase comparison timing.
First n-bit register 2 to obtain
Is delayed by one reference clock in the second n-bit register 3, and the output bus values of the first and second n-bit registers 2 and 3 are changed to the first n by the output timing of the edge detector 5. The output value of the first n-bit latch 6 (0F7h (247d)) and the output value of the second n-bit latch 4 (7F8h (-8d)) are latched by the bit latch 6 and the second n-bit latch 4, respectively. The average value of the averaging circuit 7) is used as a phase comparison output. The calculation of the average value at this time is performed assuming that it is a 2's complement (two's complement). Note that the symbol d after the numerical value means a decimal notation.

With this circuit, a value of 119.5d in the case of FIG. 2 is obtained as a result of the case where there is an edge at the center at the timing (A). It is clear that this value is appropriate by considering the following. That is, as shown in FIG. 3, assuming that a clock that is 255 times the reference clock virtually exists and considers a value counted up for each clock of the virtual clock, the value of the first n-bit register 2 is The output bus value is considered to represent the value immediately after the rising edge of the reference clock. Considering this way, the falling edge of the output of the variable frequency oscillator can be virtually considered to be at the point (B) in FIG. 3, and this falling edge and the input EFM signal at the center of the reference clock are Is 7F8h
It can be seen that this is the average value of 0F7h.

Next, consider the output of the variable frequency oscillator. The description so far is based on M of the first n-bit register 2.
Although the description has been made assuming that SB is a variable frequency oscillator output, as can be seen from FIGS. 2 and 3, the MSB of the output bus value of the first n-bit register 2 is a virtual change point of the variable frequency oscillator output. In contrast, the output always has a delay. In the case of FIG. 3, the virtual transition edge (ie, the transition point of the virtual variable frequency oscillator output) is at the MSB of the output bus value of the first n-bit register 2 despite being in the first half of the reference clock. Causes a delay of about 0.97 reference clock. That is, when the MSB of the output bus value of the first n-bit register 2 is used as the output of the variable frequency oscillator, a phase error corresponding to a maximum of one reference clock occurs.

In the present invention, in order to solve this problem, the output of the variable frequency oscillator is obtained by continuously outputting two consecutive bits of the first n-bit register 2.
MSBs of the output bus values and compare the first n
The absolute values of two consecutive output bus values of the bit register 2 are compared, and the result of comparison of the MSB of two consecutive output bus values of the first n-bit register and the two consecutive bus values of the first n-bit register are compared. The configuration is such that the MSB delay amount of the first n-bit register 2 is optimized based on the comparison result of the absolute values of the output bus values.

That is, the MSB comparison circuit 1 in FIG.
0, it is determined that the MSB is changing (that is, the changing point of the variable frequency oscillator output), and at that time the first
The absolute value of two consecutive output bus values of the n-bit register 2 is compared by an absolute value comparison circuit 9 and only when the absolute value of the preceding value is small, the first n-bit register 3 The AND circuit 11 and the selector circuit 12 are configured to select the MSB of the output bus value. Otherwise, the MSB of the second n-bit register 2 is selected.

The selected signal is sampled by the D flip-flop 13 at the final stage and becomes a variable frequency oscillator output. With this circuit, the values (7F8h,
In the case of (0F7h), since 7F8 = −8 and 0F7 = 247, | 7F8h | <| 0F7h |. As a result, the MSB of the output bus value of the first n-bit register is selected, and the delay is one stage (one reference clock) by the last D flip-flop.

Next, considering the case where the outputs of the first n-bit register 2 in FIG. 3 are 702h and 001h, since 702h = −254 and 001h = 1,
| 702h |> | 001h |. As a result, the output of the second n-bit register 3 is selected, so that the output is delayed by two reference clocks from the MSB of the output bus value of the first n-bit register 2.

That is, whether the transition edge of the virtual variable frequency oscillator output is in the first half or the second half of the reference clock is determined by comparing the absolute values of two consecutive output bus values of the first n-bit register. It is determined that the accuracy is within 0.5 reference clocks by delaying one reference clock if it is in the first half and delaying two reference clocks if it is in the second half.

With the above operation, the output of the variable frequency oscillator can be suppressed to a phase accuracy of a maximum of 0.5 clock with respect to a virtual change edge.

In the above configuration example, a steady delay of two clocks is generated. However, for applications where this delay is a problem, the input of the averaging circuit for generating the phase comparison output is
It is clear that the phase can be adjusted by inserting a delay circuit of the number of stages corresponding to the stationary delay. In the example of FIG. 1, the first and second n-bit latches 6,
In other words, n-bit registers 21 and 22 for delay are inserted in the preceding stages of each of the four stages corresponding to the number of stages corresponding to the stationary delay. Note that the n-bit register 21 at the preceding stage of the first n-bit latch 6 is
Can also be shared.

The above-mentioned stationary delay of two clocks is defined as the output bus value of the first n-bit register at the timing when there is a virtual changing edge of the variable frequency oscillator output, and the reference bus one reference clock after that. This is because, after comparing with the output bus value of the first n-bit register, it is determined whether to delay by one reference clock or two reference clocks.

According to the digital PLL circuit of this embodiment, it is possible to realize a digital variable frequency oscillator that operates at a frequency lower than 256 times as a reference clock even when the frequency resolution is desired to be 1/256, for example.
Further, since the average of two consecutive output bus values of the first n-bit register 2 at the phase comparison timing is used as the phase comparison output, the phase comparison can be accurately performed.

The delay amount of the output of the variable frequency oscillator is set to 1 in accordance with the comparison result of the absolute value of the two consecutive output bus values of the first n-bit register 2 and the comparison result of the MSB.
Since the mode is switched to one of the reference clock and the two reference clocks, the phase accuracy of the output of the variable frequency oscillator can be reduced to 0.5 reference clock or less.

[0049]

As described above, according to the present invention, a high frequency resolution can be obtained with a reference clock having a low frequency, a phase comparison can be accurately performed, and the phase accuracy of the output of the variable frequency oscillator can be adjusted to a maximum of 0.5. Reference clock, ie 0.5
A digital PLL circuit with a reference clock or less can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital PLL circuit according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the digital PLL circuit according to the embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation of the digital PLL circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a first example of a conventional digital variable frequency oscillator.

FIG. 5 is a block diagram showing a second example of a conventional digital variable frequency oscillator.

FIG. 6 is a time chart showing an operation of a second example of the conventional digital variable frequency oscillator.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 n-bit adder 2 first n-bit register 3 second n-bit register 4 second n-bit latch 5 edge detector 6 first n-bit latch 7 averaging circuit 8 digital filter 9 absolute value comparison circuit 10 MSB comparison circuit 11 AND circuit 12 Selector circuit 13 D flip-flop 14 Counter 15 Divider circuit 16 Swallow counter

Claims (2)

[Claims] 1. A first n-bit register (n is an integer of 2 or more) operated by a reference clock, and an output bus value of the first n-bit register and an input value for determining an oscillation frequency are added. A bit adder, wherein the output bus value of the n-bit adder is used as an input to the first n-bit register, and the MSBs of two consecutive output bus values of the first n-bit register are compared. Together with the first n
The absolute values of two consecutive output bus values of the bit register are compared, and the result of the comparison of the MSB of two consecutive output bus values of the first n-bit register and the consecutive value of the first n-bit register are compared. The MSB of the output bus value of the first n-bit register is optimally controlled based on the comparison result of the absolute values of the two output bus values, and the MSB of the output bus value of the first n-bit register is optimally controlled. A digital variable frequency oscillator that outputs the delayed signal of the variable frequency oscillator as a variable frequency oscillator, and outputs a phase comparison output consisting of an average value of two consecutive output bus values output from the first n-bit register at the phase comparison timing to the n A digital PLL circuit, which is input to a bit adder as an input value for determining the oscillation frequency. 2. A first n-bit register (n is an integer of 2 or more) operated by a reference clock, and an output bus value of the first n-bit register and an input value for determining an oscillation frequency are added. A bit adder, wherein the output bus value of the n-bit adder is used as an input to the first n-bit register, and the MSBs of two consecutive output bus values of the first n-bit register are compared. Together with the first n
The absolute values of two consecutive output bus values of the bit register are compared, and the result of the comparison of the MSB of two consecutive output bus values of the first n-bit register and the consecutive value of the first n-bit register are compared. The MSB of the output bus value of the first n-bit register is optimally controlled based on the comparison result of the absolute values of the two output bus values, and the MSB of the output bus value of the first n-bit register is optimally controlled. Using a digital variable frequency oscillator that outputs the delayed signal of the variable frequency oscillator as an output, providing an edge detector that detects an edge of the phase comparison target signal, using the edge of the phase comparison target signal as a phase comparison timing, and operating with the reference clock A second n-bit register which receives an output of the first n-bit register as an input; and outputs the outputs of the first and second n-bit registers to the edge detector. And an averaging circuit for calculating an average value of output values of the first and second n-bit latches. Is input to the n-bit adder as an input value for determining the oscillation frequency, and the output bus value of the first and second n-bit registers is MS
An MSB comparing circuit for comparing B to detect a match / mismatch, and an absolute value comparing circuit for detecting a magnitude relation between absolute values of output bus values of the first and second n-bit registers, A logic circuit for logically synthesizing a comparison result by the circuit and a comparison result by the absolute value comparison circuit; and, in accordance with an output of the logic circuit, an MSB of an output bus value of the first n-bit register and the second a selector circuit for selecting one of the MSBs of the output bus value of the n-bit register; a D flip-flop for holding an output of the selector circuit in response to the reference clock; A digital PLL circuit that outputs a frequency oscillator.