JP2004266594A - High-speed pll frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-speed PLL (Phase-Locked Loop) frequency synthesizer which is fast locked with a simple configuration. <P>SOLUTION: The synthesizer is provided with a means in which a plurality of resistors and capacitors that are components of a loop filter are switched with an SW to transmission/reception, so as to be set to correspond to each loop filter characteristics of transmission and reception, a means in which a calculation amplifier is connected between the output of a PLL IC and a capacitor, and charging/discharging of an electric charge with the capacitor is performed by the calculation amplifier at a prescribed timing for switching transmission/reception channel frequency, and a means in which a capacitor on such side as not to be used at reception is charged to the neutral point potential of a control voltage of VCO (Voltage controlled oscillator) to reduce variation amount of the operation potential of the capacitor when switching from reception to transmission. The synthesizer is characterised in that the convergence of time constant at switching from transmission to reception is speeded up. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a high-speed PLL (Phase-Locked Loop) frequency synthesizer having a loop filter.
[0002]
[Prior art]
In a configuration of a PLL frequency synthesizer capable of controlling a transmission / reception frequency of a VCO (Voltage Controlled Oscillator) by one system of PLL circuit, the loop filter used in the conventional method includes “one type of low-pass filter or two types of low-pass filter”. Use the one that is continuously connected. " It is not such that the transmission and reception low-pass filter characteristics can be set individually. (For example, see Non-Patent Document 1)
In some cases, a method for realizing high-speed lock-up of a PLL frequency synthesizer is implemented by devising an LPF (low-pass filter) circuit. (For example, see Non-Patent Document 2)
[0003]
[Non-patent document 1]
Nobuo Ogawa, "New PLL Technology" Ohm Publishing, June 20, 1987, p. 39-42
[Non-patent document 2]
"Practical PLL Frequency Synthesizer," edited by Masafumi Hagiwara and Yuichi Suzuki, Sogo Denshi Shuppan, March 10, 1995, p. 186-188
[0004]
FIG. 3 shows an example showing the configuration principle of a PLL frequency synthesizer conventionally used. FIG. 3 shows a PLL-IC1 having a program counter, a reference counter, and a phase comparator, an LPF2 as a loop filter that obtains a DC component from a phase correction pulse output from the PLL-IC1, and outputs a predetermined local oscillation frequency. The VCO 3 comprises a VCO 3, a prescaler for dividing the output frequency of the VCO 3 by a preset type, and a reference frequency oscillator.
In the conventional example, when it is desired to make the characteristics of the PLL frequency synthesizer at the time of transmission different from the characteristics of the PLL frequency synthesizer at the time of reception, a common reference frequency oscillator is used, and any one of the PLL-IC, LPF, VCO, and prescaler is used. Have a configuration for transmission and a configuration for reception.
Further, as a high-speed lock means of the PLL frequency synthesizer, the LPF side having a small time constant is selected to increase the lock speed at the time of frequency transition at the time of channel frequency switching or the like. There is also a configuration example that ensures lock stability (see Non-Patent Document 2).
[0005]
[Problems to be solved by the invention]
A PLL frequency synthesizer used in a mobile communication device has a narrow channel frequency interval and has to perform high-speed channel frequency switching in order to follow the moving speed of a mobile object.
Further, in a radio device in which FM modulation and FSK modulation are directly applied to the VCO on the transmission side to perform data modulation, in addition to the voice band (0.3 to 3 kHz), the lower band (about 1 to 300 Hz) is used. Since it is necessary to realize signal transmission, a PLL filter having a large time constant is required in the PLL frequency synthesizer, and as a result, the lock time of the PLL frequency synthesizer is prolonged. Since the same loop filter configuration is used on the receiving side, the lock time becomes longer. For these reasons, conventionally, it has been considered difficult to realize high-speed lock unless a PLL frequency synthesizer having a complicated configuration is used.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed PLL frequency synthesizer that can be locked at a high speed with a simple configuration by solving the above problems.
[0007]
[Means for Solving the Problems]
In order to achieve this object, a high-speed PLL frequency synthesizer according to the present invention is a PLL frequency synthesizer in which a PLL IC, a loop filter, and a VCO are formed in one system,
A plurality of resistors and a plurality of capacitors, which are constituent elements of the loop filter, are switched to transmission and reception using SW, respectively, and are set to correspond to the respective loop filter characteristics of the transmission and reception, and
An operational amplifier is connected between the output of the PLL IC and the capacitor as a buffer amplifier for current amplification, and charges and discharges of the capacitor are performed by the operational amplifier at a predetermined timing time when a transmission / reception channel frequency is switched. Means,
Further, means for charging the unused capacitor during reception to the midpoint potential of the control voltage of the VCO in order to reduce the amount of change in the operating potential of the capacitor when switching from reception to transmission. The convergence of the time constant at the time of switching between the transmission and the reception is accelerated, thereby solving the above problem.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit diagram showing an embodiment of the present invention, which is a PLL frequency synthesizer having a PLL-IC1, which is an integrated circuit PLL, a loop filter 2, an operational amplifier 4, a midpoint potential power supply 5, an inverter 6, a VCO 3, and the like. This is the main part.
The loop filter 2 has a basic configuration of an LPF including a plurality of elements of a resistor and a capacitor. There is a resistor R1 connected between the input and output of the loop filter 2 and constituting a time constant, and a resistor R2 and a resistor R3 connected in parallel between the output side of this R1 and GND to constitute a time constant. There is a switch SW1 connected in series with R3, which can perform transmission / reception switching control. SW1 is turned on at the time of transmission, and a parallel resistance value composed of R2 and R3 is formed to provide a time constant at the time of transmission. At the time of reception, only R2 is set.
Further, there are a capacitor C1 and a capacitor C2 constituting a time constant, and a switch SW2 connected in series to the C2 for performing transmission / reception switching control. When the switch SW2 is turned on at the time of transmission, a parallel capacitance value of C1 and C2 is formed. This is a capacity value that gives the time constant at the time of transmission. At the time of reception, only C1 is set. SW1 and SW2 are each controlled by a TX / RX control signal (for example, “H” level: ON at transmission, “L” level: OFF at reception).
By the above operation, the time constant of the loop filter at the time of reception is set as a lag-lead filter type composed of R1, R2, and C1, and the loop filter at the time of transmission is R1, the parallel resistance value of R2 and R3, C1 A time constant is set as a lag-lead filter type composed of a parallel capacitance value of C2 and C2 and is used in a PLL frequency synthesizer.
In this way, for each of transmission and reception, elements corresponding to a desired resistance value and a desired capacitance value are switched and selected, and the time constant is switched so that the transmission and reception loop filter characteristics can be separately set. By doing so, the LPF as a loop filter corresponding to the respective channel frequencies at the time of transmission and reception of the PLL frequency synthesizer is configured with a single transmission / reception circuit configuration.
In particular, at the time of transmission, the modulation frequency characteristic can be set to the time constant of the loop filter corresponding to the data modulation characteristic having a frequency band from the vicinity of the DC component to the high frequency range of the audio frequency.
[0009]
Next, an operational amplifier 4 connected between the PLL-IC1 and C1 and acting as a buffer amplifier for current amplification and a switch SW3 for controlling the loop of this circuit are provided. A circuit that allows charging and discharging of the capacitor directly to the capacitor, so that the charge and discharge of C1 and C2 can be performed directly without waiting for charging and discharging after the desired RC time constant of the loop filter, thereby realizing a high-speed lock time. This is a high-speed control circuit capable of increasing the speed of the entire PLL frequency synthesizer (transmission and reception).
SW3 is controlled by a Loop sel signal (a signal controlled by software by a microcomputer). The SW3 is synchronized with a rising pulse of an LE (load enable) signal output from the microcomputer and is connected to a Loop sel for several msec. This signal is input to this circuit. For example, when the Loop SEL signal is at “H” level, SW3 is turned on, the output of the operational amplifier 4 is connected to C1, and when transmitting, the output is also connected to C2. In C1, transmission and charging of C1 and C2 during transmission are performed directly between the above-mentioned timings, thereby increasing the speed.
Note that the PLL lock loop at a timing other than the time of switching the frequency channel is a circuit in which loop control is performed with a desired time constant of the loop filter.
[0010]
Further, the capacitor C2 connected as a time constant at the time of transmission is connected to the midpoint potential power supply unit 5 having a predetermined DC voltage via a switch SW4 used as a transmission / reception switching control. At the time of reception, since C2 is unused as a time constant, SW4 is turned on, and the charge of C2 is charged to the midpoint potential of the control voltage of VCO3 by the voltage of the midpoint potential power supply unit 5. This is a high-speed control circuit that realizes a high-speed lock time by reducing the amount of change in the potential of C2 as a transmission-side time constant when switching the channel frequency to reception shell transmission.
SW4 is controlled by the inverted signal of TX / RX. For example, by setting the output of the midpoint potential power supply unit 5 to 2.5 V, the start potential of the capacitor C2 on the transmission side that determines the time constant of the PLL lock loop at the time of switching the reception to transmission channel frequency is always 2.5 V. . In the case of the transmission VCO control in which the control voltage of the Lo channel frequency is 1 V and the control voltage of the Hi channel frequency is 4 V, the maximum voltage change at the time of switching the channel frequency is 2 C at the time of charge-up. The voltage change amount is from 0.5 V to 4 V, and the C2 control voltage at the time of charge-down changes from 2.5 V to 1 V, and both voltage changes become 1.5 V, which is the voltage of the conventional circuit without this circuit. (The conventional voltage change amount is 4 V from 0 V to 4 V during charge-up and 3 V from 4 V to 1 V during charge-down.)
As described above, by reducing the load of charging and discharging the capacitor for the time constant of the PLL lock loop, the speed of the entire PLL frequency synthesizer (transmission and reception) can be increased.
[0011]
FIG. 2 shows an example of a time chart of the control signal. FIG. 2A shows a time chart for channel frequency switching from transmission to reception. In accordance with the instruction of the LE signal output from the microcomputer, first, the Loop sel signal is set to, for example, "H" level for about 4 milliseconds, and SW3 is turned on. During the ON timing, charge and discharge control of C1 and C2 for switching the channel frequency is performed. Further, the TX / RX signal is switched to the RX mode, for example, at "L" level, SW1 and SW2 are turned off, and the circuit configuration of the time constant for reception at R1, R2 and C1 is obtained. SW4 is turned on, and C2 and the midpoint potential power supply unit 5 are connected to be in a charged state.
FIG. 2B is a time chart of channel frequency switching from reception to transmission. In accordance with the instruction of the LE signal output from the microcomputer, first, the Loop sel signal is set to, for example, "H" level for about 7 milliseconds, and SW3 is turned on. During the ON timing, charge / discharge control of C1 and C2 for switching the channel frequency is performed, and further, the TX / RX signal is switched to the TX mode, for example, at “H” level, SW1 is turned on, and R2 and R3 are turned on. Are connected in parallel, SW2 is also turned on, and C1 and C2 are connected in parallel. The circuit configuration of the time constant for transmission in R1, R2, R3, C1, and C2. SW4 is turned off, and C2 is disconnected from the midpoint potential power supply unit 5.
[0012]
【The invention's effect】
As described above in detail, the present invention has the following effects as a PLL frequency synthesizer used in a mobile communication device to satisfy the demand.
(1) The time constant of the loop filter can be partially changed for each transmission / reception, so that the PLL frequency synthesizer requires only a single loop filter configuration, thereby saving the circuit configuration.
(2) Since the characteristic value of the time constant of the loop filter is set for each transmission / reception, a highly accurate PLL loop characteristic can be obtained for each transmission / reception.
(3) The charge / discharge of the capacitor for the time constant of the loop filter can be forcibly performed at a limited timing when the channel frequency is switched, so that high-speed PLL loop characteristics can be obtained for both transmission and reception.
(4) Since the VCO midpoint potential is given to the transmission capacitor at the timing of the receiver, a high-speed PLL loop characteristic can be obtained during transmission.
(5) It is suitable for a high-speed PLL frequency synthesizer of a device that transmits data by directly modulating a VCO.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a control signal time chart of the present invention.
FIG. 3 is a basic configuration example of a conventional PLL frequency synthesizer.
[Explanation of symbols]
1 PLL-IC
2 Loop filter (LPF)
3 VCO
4 Operational amplifier 5 Midpoint potential power supply (DC)
6 Inverter

Claims (1)

A PLL frequency synthesizer in which a PLL IC, a loop filter, and a VCO are formed in one system,
A plurality of resistors and a plurality of capacitors, which are constituent elements of the loop filter, are switched to transmission and reception using SW, respectively, and are set to correspond to the respective loop filter characteristics of the transmission and reception, and
An operational amplifier is connected between the output of the PLL IC and the capacitor as a buffer amplifier for current amplification, and charges and discharges of the capacitor are performed by the operational amplifier at a predetermined timing time when a transmission / reception channel frequency is switched. Means,
Further, means for charging the unused capacitor during reception to the midpoint potential of the control voltage of the VCO in order to reduce the amount of change in the operating potential of the capacitor when switching from reception to transmission. Wherein the convergence of a time constant at the time of switching between transmission and reception is accelerated.

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