JPH0851360A - Phase synchronizing loop circuit - Google Patents

Abstract

PURPOSE:To obtain a phase synchronizing loop circuit whereby lock-up time at the time of channel change-over is shortened in a phase synchronizing loop circuit used for a radio equipment utilizing multiple channel frequencies. CONSTITUTION:A voltage control oscillator 11, a variable frequency divider 12 frequency-dividing its output, a reference frequency signal generator 13, a fixed frequency divider 14 frequency-dividing its output, a phase comparator 15 comparing the respective frequency divider outputs with each other and a D/A converter 17 connected to the capacitor 16b of a first loop filter 16 are provided. Then, a control voltage corresponding to a target frequency is outputted from the D/A converter 17 at the time of channel change-over and the potential of the capacitor 16b is made the potential near a final value in a short time. After that, the count values of the number of pieces of each frequency division are simultaneously cleared and counting is restarted so that the charging and discharging time of the capacitor 16b is shortened, the jump of the phase is reduced and channel change-over time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used in a radio apparatus such as a cellular telephone or a cordless telephone which switches a plurality of frequencies and transmits and receives.

[0002]

2. Description of the Related Art In recent years, the number of users has increased remarkably due to the development of wireless telephones such as cellular telephones and cordless telephones. In such a system, a plurality of frequencies are prepared for transmission / reception, and the device is designed to avoid the currently used frequency and transmit / receive at an unused frequency. Therefore, the radio section of the device incorporates a device for switching the frequency, and recently, most of them use a phase locked loop circuit.

A conventional phase locked loop circuit will be described below with reference to the drawings. FIG. 6 is a block diagram of a conventional phase locked loop circuit, where 1 is a voltage controlled oscillator that oscillates at a frequency according to the voltage applied to the control terminal, and 2 is the output of the voltage controlled oscillator 1 specified by a frequency division setting signal. A variable frequency divider that divides the reference frequency signal generator 3 that generates a reference frequency, and a fixed frequency divider that divides the output of the reference frequency signal generator 3 into 1 / M. Reference numeral 5 indicates H depending on the phase difference between the output of the variable frequency divider 2 and the output of the fixed frequency divider 4.
A phase comparator that generates outputs in three states, i-state, Low-state, and high-impedance state, 6 removes the harmonic generation contained in the output of the phase comparator, and also determines the response characteristics and synchronization characteristics of the phase-locked loop. A loop filter composed of a resistor 6a and a capacitor 6b, and a control unit 7 for generating a frequency division number setting signal for setting the frequency division number of the variable frequency divider 2.

FIG. 7 is a timing chart showing the output of the phase comparator when the frequency input from the conventional variable frequency divider is lower than the frequency input from the reference frequency signal generator. 2 shows the output state of the phase comparator 5 when the output frequency fp of 2 is lower than the output frequency fr of the reference frequency signal generator 3, that is, when fr> fp.
At this time, the output of the phase comparator 5 is in the Hi state at the rising of the output of the fixed frequency divider 4, and is reset at the rising of the output of the variable frequency divider 2 to be in the high impedance state.

FIG. 8 is a timing chart showing the output of the phase comparator when the frequency input from the conventional variable frequency divider is higher than the frequency input from the reference frequency signal generator. Output frequency fp is higher than the output frequency fr of the fixed frequency divider 4, that is, fr <fp
The output state of the phase comparator 5 at the time of is shown. At this time, the output of the phase comparator 5 becomes L at the rising edge of the output of the variable frequency divider 2.
The ow state is set, and the fixed frequency divider 4 is reset at the rising edge of the output and becomes the high impedance state.

FIG. 9 is a graph showing the oscillation frequency with respect to the control terminal voltage of the conventional voltage controlled oscillator. FIG. 10 is a time response waveform diagram showing a transient state of the control terminal voltage of the voltage controlled oscillator at the time of channel switching in the conventional phase locked loop circuit, which is almost equal to the change in the potential difference across the capacitor of the loop filter 6.

The operation principle of the loop phase locked loop configured as described above will be described. First, although it is in the steady state, the voltage control generator 1 oscillates at a frequency according to the fV curve shown in FIG. 9 according to its control terminal voltage. The output of the voltage controlled oscillator 1 is transmitted to the variable frequency divider 2, where it is divided into 1 / N and transmitted to the phase comparator 5. The output of the reference frequency signal generator 3 is divided into 1 / M by the fixed frequency divider 4 and added to the phase comparator 5.
The phase comparator 5 shows three states of Hi state, Low state and high impedance state according to the phase difference between these two inputs. However, in the steady state, there is no phase difference between the two inputs, so there is a high impedance state. Is output. Therefore, charging / discharging does not occur in the capacitor 6a of the loop filter 6, the control terminal voltage of the voltage controlled oscillator 1 is held constant, and the voltage controlled oscillator 1 continues to oscillate at the same frequency.

Next, the operation when the output of the voltage controlled oscillator 1 changes due to the influence of temperature change and the like will be described. When the output frequency of the voltage controlled oscillator 1 becomes low,
The frequency transmitted from the variable frequency divider 2 to the phase comparator 5 is also
It becomes lower than the frequency transmitted from the fixed frequency divider 4 to the phase comparator 5. Therefore, as shown in FIG. 7, the output of the phase comparator 5 is in the Hi state at the rising of the output of the fixed frequency divider 4, and is reset at the rising of the output of the variable frequency divider 2 to be in the high impedance state. While the output of the phase comparator 5 is in the Hi state, the capacitor 6b of the loop filter 6
Are charged, the control terminal voltage of the voltage controlled oscillator 1 rises, the oscillation frequency gradually increases, and the frequency fluctuation is suppressed. On the contrary, when the output frequency of the voltage controlled oscillator 1 becomes high, the variable frequency divider 2 to the phase comparator 5
Also the frequency transmitted to the fixed frequency divider 4 to the phase comparator 5
It is higher than the frequency transmitted to. Therefore, as shown in FIG. 8, the output of the phase comparator 5 is in a Low state at the rising edge of the output of the variable frequency divider 2 and is reset in the high impedance state at the rising edge of the output of the fixed frequency divider 4. While the output of the variable frequency divider 2 is in the Low state, the capacitor 6b of the loop filter 6 is discharged, the control terminal voltage of the voltage controlled oscillator 1 is lowered, the oscillation frequency is gradually lowered, and the fluctuation of the frequency is suppressed. To go.

Next, the operation when switching channels will be described. When switching channels, first, a channel switching signal is output from the control unit 7 and transmitted to the variable frequency divider 2. In the variable frequency divider 2, the frequency division number N is changed according to the channel switching signal. In the steady state, the output frequency fr of the fixed frequency divider 4 obtained by dividing the output fr of the reference frequency signal generator 3 into 1 / M.
/ M, the output frequency fp of the voltage controlled oscillator 1 and the frequency division number N of the variable frequency divider 2 have a relationship of fr / M = fp / N, and when the channel is switched from the low frequency to the high frequency, the frequency division is performed. The number is increased and the divisor is reduced when switching the channel from a higher frequency to a lower frequency. Therefore, immediately after the channel switching, the frequency transmitted from the variable frequency divider 2 to the phase comparator 5 when the channel is switched from the low frequency to the high frequency as compared with the frequency transmitted from the fixed frequency divider 4 to the phase comparator 5. Will be lower. Further, when the channel is switched from the high frequency to the low frequency, the frequency transmitted from the variable frequency divider 2 to the phase comparator 5 becomes high. The output of the phase comparator 5 is shown in FIG. 7 when switching the channel from the low frequency to the high frequency.
When the channel is switched from the high frequency to the low frequency, it becomes as shown in FIG. When the output of the phase comparator 5 is transmitted to the loop filter 6, the capacitor 6b of the loop filter 6 is charged and discharged, the control terminal voltage of the voltage controlled oscillator 1 changes, and the output frequency changes accordingly. Further, assuming that the output frequency in the steady state of the voltage controlled oscillator 1 is f1 before the channel switching and f2 after the channel switching, the control terminal voltages of the voltage controlled oscillator 1 are V1 and V2, respectively, as shown in FIG. Becomes At this time, the time-varying waveform of the control terminal voltage of the voltage controlled oscillator 1 is as shown in FIG. 10, and this waveform is determined by the time constant of the loop filter 6 and the like.

[0010]

However, in the conventional phase-locked loop circuit described above, when FM modulation is directly applied to the voltage controlled oscillator as in the recent FM modulation transmitter, the time constant of the loop filter is increased to some extent. There is a problem that it is difficult to shorten the time required for channel switching because it is necessary to set it.

An object of the present invention is to solve the above problems and to provide a phase locked loop circuit in which the channel switching time is fast even when the time constant of the loop filter is increased.

[0012]

To this end, the phase-locked loop circuit of the present invention includes a voltage-controlled oscillation means for oscillating and outputting at a frequency according to a control voltage input to a control terminal, and a frequency division number by a reset signal. First dividing means for dividing the output of the voltage controlled oscillating means having a function of restarting counting from the beginning into a dividing number according to the dividing number setting signal; and a reference frequency oscillating means for oscillating at the reference frequency. A second frequency dividing means for dividing the output of the reference frequency oscillating means having a function of restarting counting of the frequency dividing number by the reset signal into a frequency dividing number according to the frequency dividing number setting signal; Output of frequency dividing means and second
Comparing the output of the frequency dividing means, to generate an output according to the phase difference, the phase comparison means, a loop filter consisting of a resistor and a capacitor provided between the control terminals of the phase comparison means and the voltage controlled oscillation means, Voltage generating means for generating a voltage according to the voltage control signal; a switch for connecting and disconnecting the capacitor of the loop filter and the output of the voltage generating means according to the switching control signal; the first frequency dividing means and the first frequency dividing means. A reset signal, a frequency division number setting signal, a voltage control signal, and a control signal for controlling the switching signal to the frequency dividing means of No. 2 are provided, and the output frequency of the voltage controlled oscillation means is changed from the first frequency to the second frequency. At this time, at the same time as outputting the frequency division number setting signal corresponding to the second frequency, the control voltage of the voltage control means necessary for generating the second output frequency is generated from the voltage generation means, and the switch is connected. State, the potential of the capacitor of the loop filter is changed by the voltage generation means, the frequency division numbers of the first frequency division means and the second frequency division means are simultaneously reset, counting of the frequency division number is restarted, and the switch is released. I made it to the state.

Further, the output of the voltage control oscillating means having a function of oscillating and outputting at a frequency according to the control voltage inputted to the control terminal and the function of re-counting the frequency division number by the reset signal from the beginning is provided. It has a first frequency dividing means for dividing into a frequency division number according to the frequency division number setting signal, a reference frequency oscillating means for oscillating at a reference frequency, and a function of restarting counting of the frequency division number from the beginning by a reset signal. The output of the reference frequency oscillating means is divided into a second dividing means for dividing the output by the dividing number setting signal, and the output of the first dividing means and the output of the second dividing means are compared. , A phase comparison means for generating an output according to the phase difference, at least two voltage holding means for removing an AC component of the output of the phase comparison means and holding a DC component, and a voltage holding means for the output of the phase comparison means. One of
And a second changeover switch for connecting the input of the voltage control oscillation means to any one of the voltage holding means, and a predetermined changeover for each oscillation frequency generated in the voltage control oscillation means. One of the selected voltage holding means is selected, and the selected one of the voltage holding means is connected between the output of the phase comparison means and the control terminal of the voltage controlled oscillation means by the first changeover switch and the second changeover switch. , A reset signal for resetting the frequency division numbers of the first frequency division means and the second frequency division means at the same time and restarting counting of the frequency division numbers is output, and a frequency corresponding to the oscillation frequency generated in the voltage controlled oscillation means. The control means for controlling to output the circumference setting signal is provided.

[0014]

According to the present invention, when the output frequency of the voltage controlled oscillating means is switched from the first frequency to the second frequency, the capacitor in the loop filter is directly charged by the voltage generating means via the switch. Further, the count values of the first frequency dividing means and the second frequency dividing means are simultaneously reset and the counting is restarted.

Further, when the voltage controlled oscillating means oscillates by switching a plurality of different frequencies, the direct current applied to the control terminal of the voltage controlled oscillating means in any one of the voltage holding means determined for each frequency. Each time the voltage is held and the frequency is switched, the voltage holding means connected to the control terminals of the phase comparison means and the voltage control means is switched, and further, the first frequency dividing means and the second frequency dividing means. The count value is reset at the same time and the count is restarted.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a phase locked loop circuit according to the first embodiment of the present invention, and 11 is a voltage applied to a control terminal. A voltage controlled oscillator that oscillates at a frequency according to
12 is a variable frequency divider that divides the output of the voltage controlled oscillator 11 by a number specified by the frequency division setting signal, 13 is a reference frequency signal generator that generates a reference frequency, and 14 is a reference frequency signal generator 13. A fixed frequency divider that divides the output of 1 to 1 / M, and 15 has three states of Hi state, Low state and high impedance state according to the phase difference between the outputs of the variable frequency divider 12 and the fixed frequency divider 14. Phase comparator that produces output, 1
Reference numeral 6 denotes a first loop filter including a resistor 16a and a capacitor 16b that determines a response characteristic and a synchronization characteristic of the phase locked loop, while removing a harmonic component included in the output of the phase comparator. 1 is a D / A converter for charging and discharging the capacitor 16b in the loop filter 16, 18 is a switch for opening / closing between the D / A converter 17 and the first loop filter 16, and 19 is a frequency divider of the variable frequency divider 12. Frequency division setting signal and variable frequency divider 1
2 and a reset signal for resetting the frequency division number of the fixed frequency divider 14 to restart the frequency division, a voltage setting signal for controlling the output voltage of the D / A converter 17, and a switching signal for controlling the opening / closing of the switch 18. It is a control unit that does.

FIG. 2 is a time response waveform diagram showing a transient state of the control terminal voltage of the voltage controlled oscillator 11 at the time of channel switching according to the first embodiment of the present invention.
Is almost equal to the change in the potential difference across the capacitor 16b. The operation of the phase-locked loop circuit configured as above will be described below.

Regarding the operation of correcting the frequency fluctuation of the voltage controlled oscillator 11 due to the steady state and the temperature change, etc., the switch 18 is in the released state, which is the same as the operation principle of the conventional phase locked loop circuit. Next, the operation when switching channels will be described. When switching channels, first, a channel switching signal is output from the control unit 19 and transmitted to the variable frequency divider 12, as in the conventional example. In the variable frequency divider 12, the frequency division number N is changed according to the channel switching signal. As in the conventional example, if the output frequency in the steady state with the voltage controlled oscillator 11 is f1 before channel switching and f2 after channel switching, when the voltage controlled oscillator 11 has output characteristics as shown in FIG. The control terminal voltages of the controlled oscillator 11 need to be V1 and V2, respectively. In the phase locked loop circuit of the present invention, when the channel is switched, the voltage setting signal is output from the controller 19 to the D / A converter 17 in addition to the channel switching signal described above.

When the frequency after channel switching becomes f2, a voltage setting signal in which the output from the D / A converter 17 becomes V2 is issued from the control unit 19 and transmitted to the D / A converter 17. Upon receiving the voltage setting signal, the D / A converter 17 immediately sets the output voltage to V2 and outputs it. Subsequently, a switching signal is output from the control unit 19 to the switch 18, the switch 18 is turned on, and D
The output of the A / A converter 17 is the first loop filter 16
Is transmitted to the condenser 16b. At this time, since the internal resistances of the D / A converter 17 and the switch 18 are very small, the potential difference across the capacitor 16b is instantaneously V
It becomes 2. After the potential difference between both ends of the capacitor 16b becomes V2, the control unit 19 further outputs a reset signal to the variable frequency divider 12 and the fixed frequency divider 14 at the same time, and the respective frequency division numbers are counted from 0 at the same timing. It will be restarted. Finally, the switch 18 is turned off by the switching signal from the control unit 19. Then, similarly to the phase locked loop circuit of the conventional example, a minute frequency error is corrected and the steady state is entered. FIG. 2 shows a time change waveform of the control terminal voltage of the voltage controlled oscillator 11 at this time. As shown in FIG. 2, the control terminal voltage of the voltage controlled oscillator 11 of the phase locked loop circuit in the present invention becomes substantially equal to the voltage value in the steady state at the same time when the channel is switched, and then finely adjusted by the feedback control of the phase locked loop. It

FIG. 3 is a block diagram of a phase locked loop circuit according to the second embodiment of the present invention, in which 21 is a voltage controlled oscillator which oscillates at a frequency corresponding to the voltage applied to the control terminal, 22.
Is a variable frequency divider that divides the output of the voltage controlled oscillator 21 by a number specified by the frequency division setting signal, 23 is a reference frequency signal generator that generates a reference frequency, and 24 is a reference frequency signal generator 23. A fixed frequency divider that divides the output into 1 / M, and 25 has three states of Hi state, Low state, and high impedance state according to the phase difference between the output of the variable frequency divider 22 and the output of the fixed frequency divider 24. A phase comparator for generating the output of the first comparator 26 removes a harmonic component contained in the output of the phase comparator, and includes a resistor 26a and a capacitor 26b for determining the response characteristic and the synchronization characteristic of the phase locked loop.
A loop filter 27 for removing the harmonic components contained in the output of the phase comparator, and a resistor 27a and a capacitor 27 for determining the response characteristics and the synchronization characteristics of the phase locked loop.
b is a second loop filter, and 28 is a phase comparator 2
5, a switch for switching connection between the first loop filter 26 and the second loop filter 27, a and b fixed contacts thereof, 29 a control terminal of the voltage controlled oscillator 21, the first loop filter 26 and the second loop filter 26. A switch for switching connection to the loop filter 27, c and d are fixed contacts thereof, 20 is a frequency division number setting signal for setting the frequency division number of the variable frequency divider 22, variable frequency divider 22 and fixed frequency divider 24. The control unit generates a reset signal for resetting counting of the frequency division number and restarting frequency division, and a switching signal for controlling switching of the switches 28 and 29.

FIG. 4 is a time response waveform diagram showing a transient state of the control terminal voltage of the voltage controlled oscillator at the time of channel switching in the phase locked loop circuit of the second embodiment of the present invention, and FIG. 5 is each part in the phase locked loop circuit. FIG.

The operation of the phase-locked loop circuit configured as described above will be described below. Regarding the operation of correcting the frequency fluctuation of the voltage controlled oscillator 21 due to the steady state and the temperature change, etc., the switch 28, the switch 2
9 between the phase comparator 25 and the voltage controlled oscillator 21
Since the loop filter 26 or the second loop filter 27 is connected and the operation is similar to that of the conventional phase locked loop circuit, the description thereof will be omitted here and the operation at the time of channel switching will be described.

First, the output frequency f of the voltage controlled oscillator 21.
The operation when p is changed from the first frequency f1 to the second frequency f2 will be described. As shown in a part of FIG. 5, first, at time t1, the switch 28 is opened by the switching signal A from the control unit 20, and then at time t2.
In response to the switching signal B from the control unit 20, the switch 29 is switched to the second loop filter 27 side. At this time, the output voltage of the second loop filter 27 is substantially equal to the final output voltage when the voltage controlled oscillator 21 was oscillating at f2 immediately before, and the control terminal of the voltage controlled oscillator 21 has a voltage of approximately V2. Voltage is applied. At the same time, the variable frequency divider 24 is changed by the channel switching signal from the controller 20.
The frequency division number N is changed to a value corresponding to the output frequency f2, and the control unit 20 further controls the variable frequency divider 22 and the fixed frequency divider 2
4, the reset signal is output to 4, and the variable frequency divider 22 and the fixed frequency divider 24 clear the count value of the frequency division number, and at the same time, the counting of the frequency division number is restarted from 0. After that, at time t3 in FIG. 4, the switch 29 outputs the output of the phase comparator 25 to the second loop filter 2 by the switching signal B from the controller 20.
It is switched to the one connected to 7. The transient response of the terminal voltage Vc of the control terminal of the voltage controlled oscillator 21 at this time is shown in FIG.
It is shown in the part of b. The terminal voltage Vc is measured by the switch 29 from the first loop filter 26 side to the second loop filter 2 side.
After time t3 when the switch 28 is switched and the output of the phase comparator 25 is transmitted to the second loop filter 27, a minute error is corrected and eventually V2 is reached. Get sick.

Next, the output frequency f of the voltage controlled oscillator 21
The operation when p is changed from the second frequency f2 to the first frequency f1 will be described. As shown in C of FIG. 5, first, at time t4, the switch 28 is released by the switching signal A from the control unit 20, and then at time t5.
Then, the switch 29 is switched to the first loop filter 26 side by the switching signal B from the control unit 20. At this time, the output voltage of the first loop filter 26 is almost equal to the final output voltage when the voltage controlled oscillator 21 was oscillating at f1 immediately before, and the control terminal of the voltage controlled oscillator 21 has a voltage of approximately V1. Voltage is applied. At the same time, the variable frequency divider 22 is controlled by the channel switching signal from the controller 20.
The frequency division number N is changed to a value corresponding to the output frequency f1, and the control unit 20 further controls the variable frequency divider 22 and the fixed frequency divider 2
4, the reset signal is output to 4, and the variable frequency divider 22 and the fixed frequency divider 24 clear the count value of the frequency division number, and at the same time, the counting of the frequency division number is restarted from 0. After that, at time t6 in FIG. 5, the switch 28 outputs the output of the phase comparator 25 to the first loop filter 2 by the switching signal A from the control unit 20.
It is switched to the one connected to 6. The transient response of the terminal voltage Vc of the control terminal of the voltage controlled oscillator 21 at this time is shown in FIG.
It is shown in the two parts. The terminal voltage Vc is measured by the switch 29 from the second loop filter 27 side to the first loop filter 2
After time t6 when the switch 28 is switched and the output of the phase comparator 25 is transmitted to the first loop filter 26 after time t6 when the switch to the 6 side is switched to approximately V1, the correction of the minute error is performed, and eventually V1. Get sick.

[0025]

As described above, according to the phase locked loop circuit of the present invention, the capacitor of the loop filter is directly charged and discharged by the D / A converter at the time of channel switching, and the frequency division for phase comparison is restarted. , Whether using a phase comparator with any output characteristics or using a loop filter with any time constant, reduces the charging time of the loop filter capacitor regardless of them, and It is possible to reduce jumps and remarkably shorten the channel switching time.

Further, the control voltage at the time of oscillating at the same frequency immediately before the channel switching is held in the capacitors in the plurality of loop filters, and by utilizing it, the next oscillation is started and input to the phase comparator. Since the count of each frequency divider is reset to 0 and the count is restarted at the same time, when viewed from the output of each loop filter, the fluctuation range of the control voltage is smaller than that of the conventional example, and when the channel is switched. There is little phase jump, and the channel switching time can be significantly shortened regardless of the output characteristics of the phase comparator and the time constant of the loop filter.

[Brief description of drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a time response waveform diagram showing a transient state of the control terminal voltage of the voltage controlled oscillator during channel switching according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a phase locked loop circuit according to a second embodiment of the present invention.

FIG. 4 is a time response waveform diagram showing a transient state of the control terminal voltage of the voltage controlled oscillator during channel switching in the phase locked loop circuit of the second embodiment of the present invention.

FIG. 5 is a timing chart of each part in the phase locked loop circuit according to the second embodiment of the present invention.

FIG. 6 is a block diagram of a conventional phase locked loop circuit.

FIG. 7 is a timing chart showing the output of the phase comparator when the frequency input from the conventional variable frequency divider is lower than the frequency input from the reference frequency signal generator.

FIG. 8 is a timing diagram showing the output of the phase comparator when the frequency input from the conventional variable frequency divider is higher than the frequency input from the reference frequency signal generator.

FIG. 9 is a diagram showing an oscillation frequency with respect to a control terminal voltage of a conventional voltage controlled oscillator.

FIG. 10 is a time response waveform diagram showing a transient state of the control terminal voltage of the voltage controlled oscillator during channel switching in the conventional phase locked loop circuit.

[Explanation of symbols]

 11, 21 Voltage controlled oscillator 12, 22 Variable frequency divider 13, 23 Reference frequency signal generator 14, 24 Fixed frequency divider 15, 25 Phase comparator 16, 26 First loop filter 16a, 26a, 27a Resistor 16b, 26b, 27b Capacitors 18, 28, 29 Switch 19, 20 Control unit 27 Second loop filter

Claims (2)

[Claims] 1. A voltage-controlled oscillating means for oscillating and outputting at a frequency according to a control voltage inputted to a control terminal, and a voltage-controlled oscillating means having a function of restarting counting of a frequency division number by a reset signal. A first frequency dividing means for dividing the output into a frequency division number according to the frequency division number setting signal, a reference frequency oscillating means for oscillating at the reference frequency, and a function for restarting counting of the frequency division number from the beginning by a reset signal. Second frequency dividing means for dividing the output of the provided reference frequency oscillating means into a frequency dividing number according to the frequency dividing number setting signal, an output of the first frequency dividing means and the second frequency dividing means. Phase comparison means for comparing the outputs of the voltage control means and the output according to the phase difference, a loop filter including a resistor and a capacitor provided between the phase comparison means and the control terminal of the voltage controlled oscillation means, and voltage control Voltage according to the signal Generated voltage generation means, a switch for connecting and disconnecting the capacitor of the loop filter and the output of the voltage generation means according to a switching control signal, the first frequency dividing means and the second frequency dividing means. A reset signal and a frequency division number setting signal to the means, a control means for controlling the voltage control signal and the switching signal, and changing the output frequency of the voltage controlled oscillation means from the first frequency to the second frequency. , A frequency division number setting signal corresponding to the second frequency is output, and at the same time, a control voltage of the voltage control means necessary for generating the second output frequency is generated from the voltage generation means, and a switch is connected. And the potential of the capacitor of the loop filter is changed by the voltage generating means.
2. The phase-locked loop circuit, wherein the frequency dividing means and the second frequency dividing means are reset at the same time, counting of the frequency dividing number is restarted, and the switch is brought into an open state. 2. A voltage-controlled oscillating means for oscillating and outputting at a frequency according to a control voltage inputted to a control terminal, and a voltage-controlled oscillating means having a function of restarting counting of a frequency division number by a reset signal. A first frequency dividing means for dividing the output into a frequency division number according to the frequency division number setting signal, a reference frequency oscillating means for oscillating at the reference frequency, and a function for restarting counting of the frequency division number from the beginning by a reset signal. Second frequency dividing means for dividing the output of the provided reference frequency oscillating means into a frequency dividing number according to the frequency dividing number setting signal, an output of the first frequency dividing means and the second frequency dividing means. Phase comparison means for comparing the outputs of the phase comparison means and generating an output according to the phase difference, at least two voltage holding means for removing the AC component of the output of the phase comparison means and holding the DC component, and the phase comparison The output of the means of the voltage holding means A first changeover switch connected to one of them, a second changeover switch connecting the input of the voltage controlled oscillation means to any one of the voltage holding means, and generated in the voltage controlled oscillation means One of the voltage holding means, which is predetermined for each oscillation frequency, is selected, and between the output of the phase comparison means and the control terminal of the voltage controlled oscillation means by the first changeover switch and the second changeover switch. The selected one voltage holding means is connected, and a reset signal for simultaneously resetting the frequency division numbers of the first frequency division means and the second frequency division means and restarting counting of the frequency division numbers is output, A phase-locked loop circuit comprising: a control unit that controls to output the frequency division setting signal corresponding to the oscillation frequency generated in the voltage controlled oscillation unit.