JPH09121158A - Frequency synthesizer tuner - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce further a lockup time by decreasing a time till an oscillating frequency of a VCO is tuned to an object channel selection frequency. SOLUTION: This tuner uses a frequency comparison means 5 to obtain a frequency difference Δf between an object channel selection frequency f1 and an oscillator frequency do of a VCO 3 and has a frequency comparison loop to feed back the obtained frequency difference signal Δf to the VCO 3 and the channel frequency f1 is adjusted by controlling the oscillator frequency fo of the VCO 3 with the frequency comparison loop. In this case, a count time setting means 7 to vary a count time Tc for measuring the oscillator frequency of the VCO 3 used by the frequency comparison means 5 is provided, and the frequency comparison means 5 increases the count time Tc every time the measurement of the oscillator frequency of the VCO 3 is repeated by the frequency comparison means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL in a receiver.
The present invention relates to a frequency synthesizer tuner using a (Phase Locked Loop) circuit, and more particularly to a frequency synthesizer tuner that shortens the lock-up time of the PLL circuit and can tune to a target tuning frequency in a short time.

[0002]

2. Description of the Related Art In a frequency synthesizer tuner, a P section is provided in a receiving section for demodulating a received signal in synchronization with a target tuning frequency.
The LL circuit is used. FIG. 11 shows the principle configuration of a PLL circuit used in a conventional frequency synthesizer tuner.

As shown in FIG. 11, a PLL circuit used in a conventional frequency synthesizer tuner has a phase comparator 1, a low-pass filter (hereinafter referred to as LPF) 2,
It is composed of a voltage controlled oscillator (hereinafter referred to as VCO) 3 and a programmable divider 4 which constitutes a frequency divider.

The phase comparator 1 has a reference signal f _ref and a frequency division output f _V = f _o / M from the programmable divider 4.
_i (M _i is a frequency division value for giving a target tuning frequency) is input. The phase comparator 1 uses the two input signals f
The phase difference Δθ between _ref and f _v is detected. Then, the obtained phase difference signal Δθ is converted into direct current by the LPF 2 and then input to the VCO 3 as a voltage control signal. The oscillation frequency f _o of the VCO3 will vary according to the magnitude of the voltage control signal sent from the LPF2. The oscillation output of the VCO 3 is sent again to the phase comparator 1 via the programmable divider 4 and the phase comparison operation described above is repeated. As a result of repeating such a phase comparison operation, the oscillation frequency f of the VCO 3
_0, eventually converge to _{f o = M i × f ref} .

Therefore, the above f_oIs the target tuning frequency
In order to be the same as _iPrepare various
If it is flicker, the dividing value M of the programmable divider 4_iChange
Just by doing, you can freely switch to the desired broadcast station and receive
It becomes possible. The f_o= M_i× f_refof
As is clear from the formula, the frequency synthesizer tuner
Tuning accuracy is the reference frequency f_refDepends on

By the way, in a frequency synthesizer tuner using a PLL, upon reception thereof, the PLL system is stable, the time until locking to a target frequency (so-called lock-up time) is as short as possible, It is necessary to satisfy the contradictory conditions that the system noise is small. Therefore, if the loop constant of the PLL circuit is set with an emphasis only on the lockup time, the system will not be stable and is not suitable for practical use.

For this reason, in the conventional frequency synthesizer tuner using the PLL, the loop constant of the PLL circuit is set so as to satisfy each of the above-mentioned conditions within a practically usable range. Therefore, it is difficult to shorten the lockup time, and when switching the tuning frequency, a mute process is performed to prevent noise and the demodulation output is attenuated each time.

Therefore, in order to solve such a problem, the present applicant has previously made it possible to greatly reduce the lock-up time and to eliminate the need for mute processing when switching the tuning frequency. Proposed a synthesizer tuner. FIG. 12 shows the principle configuration of the PLL circuit adopted in the frequency synthesizer tuner according to this prior application.

The PLL circuit shown in FIG.
Vibration frequency f_oAnd the target tuning frequency f _iFrequency difference Δf
The frequency comparator 5 for obtaining the
In addition to the conventional phase comparison loop, the frequency comparison means 5
A frequency comparison loop consisting of is added. What
The same parts as those in FIG. 11 are designated by the same reference numerals.

The operation of the PLL circuit of FIG. 12 will be described below.
At the start of switching the tuning frequency f _i, the switch 6 is turned off and the phase comparison loop by the phase comparator 1 is opened. In this state, first, obtains a frequency difference Δf between the oscillation frequency f _o and the target tuning frequency f _i of the VCO3 the frequency comparison means 5, feeds back the obtained frequency difference signal Δf to LPF2 .

[0011] As a result, the oscillation frequency f _o of VCO3 changes toward the tuning frequency f _i of purpose. And VC
O3 of the oscillation frequency f _o is detected by such lock detector (not shown) that is substantially equal to the tuning frequency f _i of the object, by turning on the switch 6 activates the phase comparison loop by the phase comparator 1, usually The PLL operation is started.

With such a configuration, the VCO3
Vibration frequency f_oIs the target tuning frequency f _iIs almost equal to
Since the control is performed in the frequency comparison loop up to
Frequency f_refThe phase comparison operation with VCO3 becomes unnecessary and VCO3
Oscillation frequency f_oTuning frequency f for_iUp to high speed
You can bring it with you. For this reason, lock-up
Im can be greatly shortened.

[0013]

The frequency synthesizer tuner according to the prior application was sufficiently satisfactory in its performance. However, from the viewpoint of high-speed switching of the receiving station, the smaller the lockup time, the more desirable. For example, taking the RDS (Radio Data System) that uses multiplex broadcasting, which has been put to practical use in Europe, as an example, this RDS broadcasts while listening to the radio while driving at high speed in a car. When the area changes or the reception sensitivity decreases, a function of searching for another broadcasting station that is broadcasting the same program as the program that has been listened up to and automatically switching and receiving is provided. In order to realize such a function, it is necessary to check the reception status of the alternative candidate station broadcasting the same program. However, the smaller the lockup time, the faster the check can be performed. You don't have to.

By the way, in the case of the PLL circuit of the frequency synthesizer charger according to the prior application, the frequency comparing means 5 has one cycle T of the reference frequency f _ref as shown in FIG.
_ref (hereinafter referred to as the reference cycle. Note that T _ref = 1 / f
utilizing _ref) as a count time T _C, determine the oscillation frequency f _o of the VCO3 by counting the number of oscillation pulses between the count time T _C = T _ref,
The frequency difference Δf from the target tuning frequency f _i is calculated. In FIG. 13, W _t is a wait time until the frequency of the VOC 3 is changed and stabilized, and the next frequency difference detection can be performed.

The oscillation frequency f of the VCO 3_oMeasure
Count time T for_CAs the reference period T_ref
The reason for using is as follows. Ie the phase
The amount set in the programmable divider 4 of the comparison loop
Circumference M_iIs the target tuning frequency f_iAnd then M_i= F_i/ F_ref= F_i・ T_ref Given by As is clear from this formula, the division value M_i
Is the reference period T_refTuning frequency f_iThe pulse power
It represents the number of und. Therefore, this reference period T _refof
The frequency division value is calculated by counting the number of VCO3 oscillation pulses between
M_iBy taking the difference with_iAnd VCO
Oscillation frequency f of 3_oThe frequency difference Δf with
This is because you can

The frequency difference detection processing is performed by the VCO 3
Vibration frequency f_oIs the target tuning frequency f _iIs almost equal to
Up to at least several times. Accordingly
And the oscillation frequency f of VCO3_oThe target tuning frequency f_i
At least the reference period T_refA few laps of
It requires more processing time than expected. Tuning frequency for this purpose
Number f_iIt is possible to shorten the total time to reach
If that happens, the lockup time will be further shortened.
Can be

After proposing the frequency synthesizer tuner according to the above-mentioned prior application, the inventors of the present invention conducted intensive research and found that the VC
The oscillation frequency f _o of the O3 to further reduce the time to match the tuning frequency f _i of the object is obtained by developing a frequency synthesizer tuner which can further reduce the lock-up time.

That is, the present invention relates to an improvement of the frequency synthesizer tuner according to the prior application, and an object thereof is to provide a frequency synthesizer tuner capable of further shortening the lockup time. .

[0019]

FIG. 1 is a principle block diagram of a PLL circuit used in a frequency synthesizer tuner according to the present invention. The means adopted by the present invention to solve the above problems will be described with reference to FIG. The same parts as those in FIG. 12 are designated by the same reference numerals.

The invention according to claim 1 is the frequency comparing means 5
Depending on the target tuning frequency f_iAnd VCO3 oscillation frequency
f_oAnd a frequency difference Δf from the obtained frequency difference signal
Frequency comparison rule for feeding back Δf to the VCO 3.
Of the VCO3 by the frequency comparison loop.
Oscillation frequency f_oTuning frequency f by controlling _i
Frequency synthesizer tuner
In the VCO3 used in the frequency comparing means 5,
Time T for measuring the oscillation frequency of_cCan be changed
Equipped with an effective count time setting means 7 to compare the frequencies
The operation of measuring the oscillation frequency of the VCO 3 is repeated by means 5.
Each time the count time T_cTo increase
It is characterized by the following.

As described above, the frequency comparison loop is used.
Oscillation frequency f of VCO3_oThe target tuning frequency f_iTo
Even if you try to get closer, the tuning frequency will be
Number f _iIt is difficult to get close to Things like this
If you pay attention to the fact, count time T from the beginning_CLengthen
The first time, rather than performing highly accurate frequency difference detection.
Don't time T_CTo reduce accuracy and
The frequency difference is detected quickly in time, and the second frequency is detected.
In the number difference detection, the count time T is longer than that in the first time._C
To increase the accuracy by increasing the count time
T_CIt is better to gradually increase the oscillation frequency of VCO3.
Wave number f_oThe target tuning frequency f_iTo reach
Total time can be shortened.

Therefore, according to the present invention, the count time T
A count time setting means 7 capable of varying _C is provided, and the count time T _C is increased each time the count operation is repeated in the frequency comparing means 5.

With such a structure, for example, as shown in FIG. 2, V is detected by three frequency difference detecting operations.
Oscillation frequency f _o of CO3 is to have reached the tuning frequency f _i of the purpose, the first round of counting time T _c = 1/4 ·
T _ref , second count time T _C = 1/2 · T
_Assuming that _ref and the third count time T _C = T _ref are set, the total time required for the three count operations excluding the wait time W _t is (1/4 · T
_ref + 1/2 · T _ref + T _ref ) = 1.75T _C , whereas in the case of the invention of the prior application, as shown in FIG. 13, the total time required for three counting operations excluding the wait time W _t Is 3T _C , and the present invention can match the target tuning frequency f _i in a shorter time.

In the invention according to claim 2, at least the frequency comparison means 7 is constituted by a digital circuit, and a D / A converter 8 (dotted line block in FIG. 1) is provided on the output side of the frequency comparison means 7. In the frequency synthesizer tuner according to claim 1, the input / output conversion characteristic of the D / A converter 8 is the same as the voltage-frequency characteristic of the VCO 3.

As described above, in the frequency control by the frequency comparison loop, it is necessary to count the oscillation pulses of the VCO 3 in order to obtain the frequency difference from the target tuning frequency f _i . To perform this counting process, the digital circuit is easier to process than the analog circuit. For this reason, the frequency comparison means 5 often has a digital circuit configuration. Therefore, when the frequency comparison means 5 has a digital circuit configuration as described above, an LP including an analog circuit for receiving the output of the frequency comparison means 5 is used.
Since it is necessary to match the signal format with that of F2, a D / A converter 8 is attached to the output side of the frequency comparison means 5 as shown by the dotted line block in FIG.

By the way, the input / output conversion characteristic of the D / A converter used in audio equipment such as a radio receiver is a linear characteristic shown by a dotted line in FIG. 3 so as not to generate distortion. It is normal to On the other hand, VC
A non-linear element such as a varicap is used for O3, and its V (voltage) -f (frequency) characteristic exhibits non-linearity as shown by the solid line in FIG. Therefore, if the D / A converter 8 having a linear conversion characteristic is used,
Cause errors due to the difference in the conversion characteristic, end up spending the extra time to until the oscillation frequency f _o of VCO3 converges to the tuning frequency f _i of purpose.

Therefore, in the present invention, the D / A converter 8
The input / output conversion characteristic of is the same as the Vf characteristic of the VCO 3. With such a configuration, there is no error due to the difference in characteristics, so that amount only conversion accuracy goes up, the oscillation frequency f _o of the VCO3 is shortened more time to converge to the tuning frequency f _i of interest You can

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 shows an example of the PLL circuit in the frequency synthesizer tuner according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

The PLL circuit in the illustrated example is composed of the phase comparators 1 and L.
It comprises a PF2, a VCO3, a programmable divider 4 constituting a frequency divider, a frequency comparison means 5, a D / A converter 8, a synchronization control section 9, a master clock oscillator 10, a reference divider 11, and a data holding section 12. The synchronization control section 9 also serves as the count time setting means 7. The switch 6 for switching from the frequency comparison loop to the phase comparison loop is L
As is clear from the specific example of PF2 (FIG. 8), LP
It is built into F2.

The frequency comparison means 5 counts the oscillation frequency of the VCO 3 based on the count time pulse P _c sent from the synchronization control section 9, and the tuning frequency f sent from the data holding section 12. min M _i dividing unit 14 division values M _i and 1 / n and outputs, M _i division dividing value sent from the unit 14 M _i / n for setting the _i
And a frequency difference detector 1 for subtracting the pulse count value N _i / n of the VCO 3 sent from the VCO counter 14.
5. Adder / subtractor 1 that constitutes the digital charge pump 16
7 and latch circuit 18, VCO 3 of the oscillation frequency f _o is constituted from the lock detector 19 for detecting that substantially coincides with the channel selection frequency f _i of interest. Specific examples of the M _i division unit 14 and the frequency difference detector 15 will be described later (FIGS. 6 and 7).

Under the control of a CPU (not shown), the synchronization controller 9 uses the master clock of the master clock oscillator 11 so that its time length T _C is 1 / n of the reference period T _ref.
A pulse P _C consisting of (n ≦ 1 or more) is created and output to the VCO counter 13 as a count time pulse P _c , and a reset signal RS, a frequency division value n of the count time pulse P _c , a synchronization signal, etc. Creates and outputs various control signals of.

The reference divider 11 is a master clock.
Divides the master clock generated by the lock oscillator 10.
Therefore, the reference frequency f_refA reference pulse consisting of
Generate and output. The data holding unit 12 uses
Wave number f_iDividing value M to set _iTo store and hold
It is a circuit including a shift register. This division value M _i
Is sent from a CPU (not shown).

Next, regarding the operation of the circuit, referring to the time chart of FIG. 5, the current oscillation frequency f of the VCO 3 is shown.
A case will be described as an example where _o = f _i ′ is changed to a new channel selection frequency f _i instructed by the CPU.

[0034] First, the oscillation frequency of VCO3 f _o = f _i
In order to change to, the frequency division value M _i giving this new channel selection frequency f _i is given to the data holding unit 12 by the CPU (not shown) and stored in the data holding unit 12. Further, a CPU (not shown) sends an end identification signal End indicating the end of data sending as shown in FIG. 5A to the tuning controller 9. The synchronization control unit 9 receives this end identification signal End
When receiving the, control each component circuit as follows,
The operation of changing the oscillation frequency of the VCO 3 is started.

The synchronization control section 9 outputs a reset signal RS as shown in FIG. 5 (h) in synchronization with the end identification signal End. This reset signal RS
Is a signal for switching the control of the PLL circuit to the frequency comparison loop side, and this reset signal RS is "H".
While the level is set, the reference divider 11,
The operations of the programmable divider 4 and the phase comparator 1 are stopped.

Upon receipt of the end identification signal End, the synchronization controller 9 sets the reference cycle T _ref to n, as shown in FIG. 5 (b).
The first count time pulse P _c having a time length of 1 / n · T _{ref obtained} by frequency division is sent to the VCO counter 13, and the frequency division value n at this time is sent to the M _i division unit 14.

For example, assuming that n = 2 is set for the first counting operation, the synchronization control unit 9 determines that the time T _c = 1 / n · T _ref = 1/2 · T _ref . Make a long count time pulse P _c
While sending to the CO counter 13, n = 2 is sent to the M _i division unit 14.

The VCO counter 13 keeps the VCO 3 while the count time pulse P _c sent thereto arrives.
Count the number of pulses of the oscillation output sent from
The pulse count value N _i / n is sent to the frequency difference detector 15.

[0039] That is, now, in the case where the assumed time length T _C of the count time pulse P _c is the reference period T _{re f,} pulse count value of the oscillation output of VCO3 in the reference period T _ref is at N _i Assuming that there is one, the pulse count value when counting with the count time pulse P _c having the time length of T _c = 1 / n · T _ref is 1 / n times N _i / n. Therefore,
The VCO counter 13 sends this pulse count value N _i / n to the frequency difference detector 15.

On the other hand, the M _i division unit 14 which has received the frequency division value n of the count time pulse P _c from the tuning control unit 9
Is obtained by dividing the frequency dividing value M _i , which gives the target tuning frequency f _i sent from the data holding unit 12, by this n,
Tuning frequency f _i corresponding to the count time T _C at that time
Converted into count pulse value M _i / n and sent to the frequency difference detector 15.

The frequency difference detector 15 has M_iDividing section 14
The target tuning frequency f sent from _iPulse count
Value M_i/ N and the current oscillation sent from the VCO 13
Frequency pulse count value N_i/ N and subtract
Difference value of (M_i/ N)-(N _i/ N) is calculated. Soshi
This difference value (M_i/ N)-(N_i/ N) was multiplied by n
Value (M_i-N_i) As the frequency difference Δf at that time
Output to the ji pump 16.

The difference value (M _i / n)-(N _i /
The reason why n) is multiplied by n and then output is as follows.
That is, the difference value (M _i / n)-(N _i / n) is
Since the frequency difference in the time of 1 / n of the reference period T _ref, it has a value of 1 / n of the original frequency difference Δf in the case of counting the reference period T _ref. Therefore, in order to restore the original frequency difference Δf, the difference value (M _i / n) −
(N _i / n) is multiplied by n and output as Δf = M _i −N _i .

The frequency difference Δf = M thus obtained
_{In i} −N _i , the time length of the count time T _C is 1 / n as compared with the case of counting using the reference cycle T _ref ,
The frequency difference Δf can be obtained within an extremely short time. However, instead, the detection accuracy drops to 1 / n.

The digital charge pump 16 is composed of an adder / subtractor 17 and a latch circuit 18. The adder / subtractor 17 holds the oscillation frequency f _o of the VCO 3 held in the latch circuit 18 and a frequency difference detector. Addition / subtraction with the frequency difference Δf input from 15 is performed. The frequency data obtained as a result of this addition / subtraction is again latched by the latch circuit 18.
To hold. The frequency difference Δf input from the frequency difference detector 15 has positive and negative values. Therefore, a positive value is added and a negative value is subtracted. The result of this addition and subtraction is shown in FIG. FIG. 5 (e) shows the case of addition.

The frequency data after addition / subtraction newly held in the latch circuit 18 is sent to the D / A converter 8 to be converted from a digital signal to an analog signal and applied to the VCO 3. As a result, the oscillation frequency of the VCO 3 is as shown in FIG.
As shown in (f), the current oscillation frequency f _i ′ changes rapidly toward the target tuning frequency f _i .

By the way, the VCO 3 has a resonance circuit composed of a varicap, a capacitor, a coil and the like. For this reason, the frequency cannot be changed instantaneously, and FIG.
As shown in, it gradually changes toward the target frequency with a time constant determined by the circuit. Therefore, if the next counting operation is started before the changed oscillation frequency of the VCO 3 stabilizes, accurate frequency control cannot be performed.

Therefore, in order to prevent the next counting operation from being started until the oscillation frequency of the VCO 3 stabilizes, the synchronization control unit 9 creates a predetermined wait time W _t with the internal counter, and FIG. As shown, after the wait time W _t has elapsed, the next count time pulse P _c is output.

On the other hand, the frequency difference Δf calculated by the frequency difference detector 15 is also sent to the lock detector 19. The lock detector 19 is composed of a counter and the like, as shown in FIG.
As shown in (d), whether the input frequency difference Δf is within a predetermined lock range, that is, V
Oscillation frequency f _o of CO3 is determined whether or not substantially equal to the tuning frequency f _i of purpose. Then, as shown in FIG. 5 (h), when it is not within the lock range, it is set to the "H" level which indicates the unlocked state, and when it is within the lock range, it is the "L" level which indicates the lock state. Level.

After the wait time W _t has elapsed, the synchronization controller 9 outputs a count time pulse P _c for the second counting operation, as shown in FIG. 5 (b). In the case of the second time, the oscillation frequency of the VCO 3 has already become a value considerably close to the target tuning frequency f _i as shown in FIG. 5 (f) by the above-described first frequency comparison operation. Therefore, in the second counting operation, the time length of the count time pulse P _c is made longer than that in the first counting in order to increase the frequency detection accuracy and perform more accurate frequency control. Therefore, in the illustrated example, n = 1 is set at the time of the second counting, and as shown in FIG. 5B, T _c = T which is twice as long as that at the time of the first counting.
_It outputs a count time pulse P _c consisting of _ref .

This count time pulse P _c is sent to the VCO counter 13. Further, the M _i division unit 14 _calculates M _i according to the frequency division value n = 1 of the count time pulse P _c.
And the value M _i / n = M _i is divided by the frequency difference detector 1
Send to 5. Then, similarly to the above-described first counting operation, the VCO counter 3 counts the oscillation frequency of the VCO 3 and the frequency difference detector 15 calculates the frequency difference Δf, and the frequency of the VCO 3 is controlled.

At the time of the second counting, since the time length of the count time pulse P _c is twice as long as that of the first time, the counting operation takes twice as long, but the frequency detection accuracy is doubled. Becomes Therefore, as a result of the frequency control by the second counting operation, the oscillation frequency f ₀ of the VCO 3 becomes a value close to the target tuning frequency f _i as shown in FIG. 5 (f).

However, in the case of this example, FIG.
As shown in, the frequency difference Δf is still not within the lock range. Therefore, a pulse having a time length of T _c = T _ref is output as the third count time pulse P _c , and the oscillation frequency f of the VCO 3 is output in the same manner as described above.
Control _o .

[0053] As a result of the third round of counting, as shown in FIG. 5 (d), the frequency difference Δf enters lock range within the oscillation frequency f _o is the purpose of channel selection frequency f _i of the VCO3 Assuming that they substantially coincide with each other, the lock detector 19 detects this and switches its output from the “H” level to the “L” level indicating the locked state, as shown in FIG. And send to the required circuits.

Upon receiving the lock detection signal from the lock detector 19, the synchronization control unit 9 switches the reset signal RS from the "H" level to the "L" level as shown in FIG. 5 (h). When the reset signal RS is switched from the “H” level to the “L” level, the phase comparator 1 starts operating and the switch 6 incorporated in the LPF 2 is started.
(See FIG. 12) is turned on, and the LPF 2 is set to a state in which the phase difference signal Δθ from the phase comparator 1 can also be input. Furthermore, the reference divider 11 and the programmable divider 4, which have been stopped until then, also start the frequency division operation at the same time, instead of the frequency comparison loop,
The control by the phase comparison loop is started.

When the control by the phase comparison loop is started, V is generated by the phase difference signal Δθ output from the phase comparator 1.
Fine adjustment of the oscillation frequency f _o of CO3 is performed. The oscillation frequency f _o of the VCO 3 is the target tuning frequency f _i
Converge to a state completely synchronized with.

As described above, in the case of the present invention, the frequency
When performing frequency control using the number comparison loop,
As the number of counts in tier 5 progresses, the count tie
Mu T _cIs set to gradually increase, so VC
Oscillation frequency f of O3_oThe target tuning frequency f_iUp to
Can be taken in a short time, and the PLL
The lockup time of the circuit can be shortened.

In the present invention, when switching from the frequency comparison loop to the phase comparison loop, as shown in FIG.
As shown in (j), the reference divider 11,
The dividing operation of the programmable divider 4 is started at the same time. If the frequency dividing operations of the reference divider 11 and the programmable divider 4 are started at the same time as described above, the phase error when switching the control from the frequency comparison loop to the phase comparison loop can be reduced, and the synchronization state can be pulled in within a shorter time. be able to.

That is, the frequency comparison loop has a frequency difference Δ
The oscillation output of the VCO 3 is controlled based on f, and the phase difference comparison loop uses the phase difference Δθ to control the VCO 3
Control the oscillation output of, and the control principles of the two are completely different. Therefore, when the control by the frequency comparison loop is inadvertently switched to the control by the phase comparison loop, the comparison signals f _ref and f input to the phase comparator 1 are input.
Even if the frequencies of _V are equal, the phase shift of both signals is output as a phase error.

Therefore, when the control is switched from the frequency comparison loop to the phase comparison loop, the dividing operations of the reference divider 11 and the programmable divider 4 are started at the same time, as shown in FIGS. It is possible to eliminate the phase shift when switching from the frequency comparison loop to the phase comparison loop. Therefore, the time until the two signals are in phase synchronization is shortened, and the lockup time can be further shortened.

FIG. 6 shows a concrete circuit example of the M _i division unit 14. The M _i division unit 14 determines the target tuning frequency f _i.
Is a circuit for dividing the frequency division value M _i that gives the frequency division value M _i by the frequency division value n of the count time pulse P _C , and includes a RAM 20 for storing the frequency division value M _i and a divider 21.
The divider 21 divides the frequency division value M _i stored in the RAM 20 by the frequency division value n of the count time pulse P _C sent from the synchronization control unit 9, and obtains the obtained division value M _i. / N is sent to the frequency difference detector 15 as a pulse count value of the tuning frequency f _i at the count time T _c at that time.

FIG. 7 shows a specific circuit example of the frequency difference detector 15. The frequency difference detector 15 includes a subtracter 22 and a multiplier 23. In the subtractor 22, the pulse count value M _i / n sent from the M _i division unit 14 and the VCO counter 13 are included. The pulse count value N _i / n sent from is subtracted, and the difference value (M _i / n)-(N _i / n) is multiplied by n in the multiplier 23 to obtain the reference period T _ref. Frequency difference Δf = M _i
It is converted into −n _i and output.

FIG. 8 shows a concrete circuit example of the LPF 2. The LPF 2 in FIG. 8 is composed of a first amplifier 24 that functions as a low-pass filter and a second amplifier 25 that functions as an adder / subtractor. A switch 6 (see FIG. 1) for turning on / off the phase comparison loop is connected between the input and output of the first amplifier 24. The switch 6 has a reset signal RS output from the synchronization control unit 9.
It is turned on / off by (FIG. 5 (h)). Also, the first
The phase difference signal Δθ from the phase comparator 1 is input to the input terminal of the amplifier 24, and the analog signal from the D / A converter 8 is input to the non-inverting input terminal of the second amplifier.

When the reset signal RS supplied from the synchronization control unit 9 is at the "H" level as shown in FIG. 5 (h), that is, in the control state by the frequency comparison loop,
The switch 6 is turned on and closed, and the input and output of the first amplifier 24 are completely short-circuited. Further, the phase comparator 1 connected to the input terminal of the first amplifier 24 is circuit-configured so that the output impedance becomes high impedance. Therefore, when the switch 6 is closed, the second amplifier 25 operates as a buffer amplifier,
Only the output from the D / A converter 8 input to the input terminal of the second amplifier 25 is sent to the VCO 3.

On the other hand, as shown in FIG. 5 (h), the reset signal RS supplied from the synchronization control unit 9 is at "L" level,
That is, when the control state by the phase comparison loop is reached, the switch 6 is turned off and opened, and the first amplifier 24 operates as a low pass filter. Further, when the reset signal RS becomes “L” level, the phase comparator 1 also starts the phase comparison operation (FIG. 5).
(See (i) (j)).

Therefore, when the switch 6 is opened, the phase difference signal Δf sent from the phase comparator 1 is converted into a DC signal by the first amplifier 24 which operates as a low pass filter, and then the second amplifier 25. Is sent to the inverting input terminal of, and the control by the phase comparison loop is started instead of the control by the frequency comparison loop that has been performed until then.

When the control by this phase comparison loop is started, the D / A converter 8 to the second amplifier 25
The analog signal input to the non-inversion input terminal of is substantially equal to the value of the frequency data held in the latch circuit 18 at the time of switching from the frequency comparison loop to the phase comparison loop, that is, the target tuning frequency f _i . It will be fixed to the matching value. Accordingly, the phase difference signal Δf is subtraction as an error signal to the analog signal, VCO 3 of the oscillation frequency f _o is the purpose of channel selection frequency f
Fine-tuned to match _i exactly.

According to the present invention, the PLL circuit can be locked up within an extremely short time as described above, but the input / output conversion characteristic of the D / A converter 8 is VC.
If it is different from the conversion characteristic of O3, a conversion error occurs, and it takes an extra time to match the oscillation frequency of the VCO 3 with the target tuning frequency f _i .

Therefore, in order to eliminate such a conversion error, it is desirable to use the D / A converter 8 having the circuit configuration shown in FIG. The D / A converter 8 of FIG. 9 decodes the data input from the digital charge pump 16 by the decoder 26 and turns on / off the corresponding switches 27 _{1 to} 27 _n to turn on the resistor R.
By shorting and opening the ₁ to R _n, but is for converting a digital signal into an analog signal, previously the resistor R
Leave the weighting ₁ to R _n, the input-output conversion characteristic, as indicated by a dotted line in FIG. 10, the voltage of the VCO 3 - are those configured to be the same as the frequency characteristics.

Instead of weighting the resistors R _{1 to} R _n , as shown by a dotted line block in FIG. 9, either the input side or the output side is utilized, for example, the B-E characteristic of a transistor or the like. Exponential conversion circuit 28 or 2
Even if 9 is connected, the same effect can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to these, and various modifications can be made in accordance with the gist of the invention.

[0071]

As described above, according to the first aspect of the invention, the frequency comparison means obtains the frequency difference between the target tuning frequency and the oscillation frequency of the voltage controlled oscillator,
A frequency synthesizer having a frequency comparison loop for feeding back the obtained frequency difference signal to a voltage controlled oscillator, and adjusting the tuning frequency by controlling the oscillation frequency of the voltage controlled oscillator by the frequency comparison loop. The tuner is provided with count time setting means capable of variably setting the count time for measuring the oscillation frequency of the voltage controlled oscillator used in the frequency comparison means, and the frequency comparison means is capable of measuring the oscillation frequency of the voltage controlled oscillator. Since the count time is increased each time it is repeated, the time until the oscillation frequency of the VCO matches the target tuning frequency is shortened,
The lockup time can be further reduced.

According to the second aspect of the invention,
2. The frequency synthesizer tuner according to claim 1, wherein at least the frequency comparison means is composed of a digital circuit, and a D / A converter is provided on the output side of the frequency comparison means. Since the voltage-frequency characteristic of the VCO is the same as that of the VCO, the conversion error due to the difference in the conversion characteristics of the VCO and the D / A converter can be eliminated, and the lock-up time can be further reduced accordingly.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of a PLL circuit used in a frequency synthesizer tuner according to the present invention.

FIG. 2 is an explanatory diagram of a count operation in the circuit of FIG.

FIG. 3 is a diagram showing conversion characteristics of a VCO and a D / A converter.

FIG. 4 is a block diagram showing an example of implementation of a PLL circuit in the frequency synthesizer tuner according to the present invention.

5 is a time chart showing the operation of the circuit of FIG.

6 is a diagram showing a specific circuit example of an M _i division unit 14 in FIG.

7 is a diagram showing a specific circuit example of a frequency difference detector 15 in FIG.

FIG. 8 is a diagram showing a specific circuit example of an LPF 2 in FIG.

9 is a diagram showing a specific circuit example of a D / A converter 8 in FIG.

10 is a diagram showing input / output conversion characteristics of the D / A converter of FIG.

FIG. 11 is a principle configuration diagram of a PLL circuit used in a conventional frequency synthesizer tuner.

FIG. 12 is a principle configuration diagram of a PLL circuit adopted in a frequency synthesizer tuner according to a prior application.

13 is an explanatory diagram of a counting operation in the circuit of FIG.

[Explanation of symbols]

1 phase comparator 2 LPF (low pass filter) 3 VCO (voltage controlled oscillator) 4 programmable divider (frequency divider) 5 frequency comparison means 6 switch 7 count time setting means _Tc count time

Claims (2)

[Claims] 1. A frequency difference between a target tuning frequency and an oscillation frequency of a voltage controlled oscillator is obtained by a frequency comparing means,
A frequency synthesizer having a frequency comparison loop for feeding back the obtained frequency difference signal to a voltage controlled oscillator, and adjusting the tuning frequency by controlling the oscillation frequency of the voltage controlled oscillator by the frequency comparison loop. In the tuner, a count time setting means capable of variably setting a count time for measuring the oscillation frequency of the voltage controlled oscillator used in the frequency comparison means is provided, and the frequency comparison means performs an operation of measuring the oscillation frequency of the voltage controlled oscillator. A frequency synthesizer tuner characterized by increasing the count time each time it is repeated. 2. At least the frequency comparison means is constituted by a digital circuit, and a D / A is provided on the output side of the frequency comparison means.
The frequency synthesizer tuner according to claim 1, further comprising a converter, wherein the input / output conversion characteristic of the D / A converter is the same as the voltage-frequency characteristic of the voltage controlled oscillator.