CN102468848A - Phase-locked loop with correcting function and correcting method thereof - Google Patents

Abstract

The invention provides a phase-locked loop, which includes a charging pump, a frequency divider, a voltage detector, a control module and a correction module. When a preset current amount and a preset frequency division amount are used, the voltage detector measures a voltage related to the output frequency of the phase-locked loop to generate a first reference voltage. When a test current amount and the preset frequency division amount are used, the voltage detector measures the voltage to generate a second reference voltage. When the preset current amount and the divide-by-one test frequency division amount are used, the voltage detector measures the voltage to generate a third reference voltage. The control module estimates the loop gain of the phase-locked loop according to the current quantity, the frequency division quantity and the reference voltage. The calibration module calibrates the PLL according to the loop gain.

Description

Phase-locked loop with correction function and its correction method

technical field

The present invention relates to phase-locked loops, and in particular to methods of correcting phase-locked loops.

Background technique

In today's computer systems and communication systems, a phase-locked loop that can provide an oscillating signal with an accurate frequency plays an indispensable and important role. Taking the wireless communication system as an example, the transmitting end usually uses the oscillating signal generated by the phase-locked loop as the reference for sending the signal. The quality of the signal.

FIG. 1 shows a structure diagram of a first type (type-I) phase-locked loop. The loop 10 includes a phase detector 11 , a charge pump 12 , a filter 13 composed of a resistor R and a capacitor C, a voltage-controlled oscillator 14 and a frequency divider 15 . Since the resistor R forms a leakage path between the input terminal of the voltage-controlled oscillator 14 and the ground terminal, no matter whether the loop 10 is locked or not, the phase detector 11 must still output periodic pulses, so that the charge pump 12 is a voltage-controlled oscillator. The input terminal of the device 14 is charged to compensate the charge lost through the resistor R. When the phase-locked loop is stable, charging and discharging are balanced, and the period of the above-mentioned pulse is equal to the period of the reference signal. The existence of the periodic pulse will interfere with the oscillating signal at the output end of the voltage-controlled oscillator 14 . The larger the phase difference between the reference signal and the feedback signal, the wider and higher the energy of the pulse. Take the case where the frequency of the oscillation signal is 3.66 GHz and the frequency of the reference signal is 26 MHz as an example. In the frequency spectrum of the output signal of the voltage-controlled oscillator 14, in addition to the main component appearing at 3.66 GHz, so-called spikes also appear at two places at 3.66 GHz±26 MHz. Many wireless communication standards will regulate the upper limit of the burst energy. A disadvantage of the first type of phase-locked loop is that the charging pulse usually results in too high a surge energy.

FIG. 2 shows the structure diagram of the second type (type-II) phase-locked loop. The loop 20 includes a phase detector 21 , two charge pumps 22A and 22B, an active filter 23 composed of a resistor R, capacitors C1 / C2 / C3 , an operational amplifier 23A, a voltage controlled oscillator 24 and a frequency divider 25 . During the process of the loop 20 entering the locked state from the unlocked state, the second charging pump 22B is responsible for charging/discharging the capacitor C1 in the active filter 23 according to the phase difference measured by the phase detector 21 until the The marked reference voltage V _REF is stepped up/down to be equal to the desired control voltage at the input of the VCO 24 when the loop 20 is locked. V _REF and the control voltage typically have a period of damping before they stabilize before locking. Although this structure does not have the problem of high surge energy of the first type PLL, the speed of charging/discharging the capacitor C1 by the second charging pump 22B will directly limit the locking speed of the loop 20 . In addition, this damping phenomenon also leads to an increase in the locking time required for the circuit 20 .

Regardless of the phase-locked loop with any of the above structures, the parameters may vary with environmental factors such as manufacturing process, temperature, and voltage, and have a considerable degree of drift, resulting in many characteristics (such as bandwidth) of the actual operation of the phase-locked loop. It is different from the preset value expected to be achieved during the original design.

Contents of the invention

In order to solve the above problems, the present invention proposes a phase-locked loop calibration method, by providing a test current and a frequency division value and observing the voltage change in the loop to find out the error of the loop gain.

A specific embodiment according to the present invention is a calibration method in conjunction with a phase-locked loop. The first step of the method is: after the charging pump of the phase-locked loop provides a preset current amount and the frequency divider of the phase-locked loop provides a preset frequency division amount, measure an output frequency related to the phase-locked loop A related voltage is used to generate a first reference voltage value. Then, the method executes a test step: measuring the voltage after the charge pump provides a test current, so as to generate a second reference voltage value. Then, the method executes another test step: measuring the voltage after the frequency divider provides a test frequency division value to generate a third reference voltage value, wherein the test frequency division value is a specific value. According to the preset current amount, the preset frequency division amount, the test current amount, the test frequency division amount, the first reference voltage value, the second reference voltage value, the third reference voltage value and a reference frequency, The loop gain of the PLL can be estimated, and the PLL can be calibrated according to the loop gain.

The correction method according to the present invention can be widely applied to PLLs of various architectures. The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Description of drawings

Fig. 1 shows the structure diagram of the traditional first-type phase-locked loop.

FIG. 2 shows the structure diagram of the traditional second-type phase-locked loop.

FIG. 3 is a block diagram of a phase-locked loop according to a first embodiment of the present invention.

FIG. 4 is an example of a voltage lock state comparing the present embodiment with the prior art.

FIG. 5 is a block diagram of a phase-locked loop according to a second embodiment of the present invention.

FIG. 6(A) is a block diagram of a phase-locked loop according to a third embodiment of the present invention.

FIG. 6(B) is a block diagram of a phase-locked loop according to a fourth embodiment of the present invention.

FIG. 7 is a flowchart of a PLL calibration method according to a fifth specific embodiment of the present invention.

Description of main component symbols

10, 20: Phase-locked loop 11, 21: Phase detector

12: Charge pump 13: Filter

14, 24: voltage controlled oscillator 15, 25: frequency divider

22A: First charge pump 22B: Second charge pump

23: Active filter 23A: Operational amplifier

30: Phase-locked loop 31A: First phase detector

31B: second phase detector 32: charge pump

33: Active filter 33A: Operational amplifier

34: Voltage controlled oscillator 35: Frequency divider

36: Digital/Analog Converter 37: Switch

38: Switching module 39: Voltage detector

40: Control module 41: Calibration module

42: Sigma-Delta Modulator 43: Pre-emphasis Circuit

S71～S78: process steps

Detailed ways

The first embodiment according to the present invention is the phase locked loop shown in FIG. 3 . This loop 30 includes two-phase detectors 31A and 31B, a charge pump 32, an active filter 33 made up of a resistor R, a capacitor C, and an operational amplifier 33A, a voltage-controlled oscillator 34, a frequency divider 35, and a Digital/Analog Converter 36.

As shown in FIG. 3 , the active filter 33 includes a first input terminal connected to the charge pump 32 , a second input terminal connected to the digital/analog converter 36 , and an output terminal for providing a control signal. The capacitor C and the resistor R are coupled in parallel between the first input terminal and the output terminal. The function of the voltage controlled oscillator 34 is to generate an oscillation signal according to the control signal. The frequency divider 35 is responsible for dividing the frequency of the oscillating signal to generate a feedback signal. According to the reference signal input to the loop 30 and the feedback signal, the first phase detector 31A generates a phase difference signal. The charging pump 32 provides a charging current to the first input terminal of the active filter 33 according to the phase difference signal.

The second phase detector 31B is used to detect the phase difference between the reference signal and the feedback signal, and its output signal is a digital reference voltage. For example, the digital reference voltage can be an 8-bit binary signal; the voltage can be generated by sending multi-segment digital unit values with different sizes to a digital accumulator (not shown in the figure). The positive or negative of the above-mentioned phase difference will determine the positive or negative of the input signal of the accumulator, and the change speed of the output value of the accumulator depends on the magnitude of the input signal of the accumulator. For example, when the phase of the reference signal leads the phase of the feedback signal, the input signal to the accumulator is positive. Conversely, when the phase of the reference signal lags behind the phase of the feedback signal, the input signal to the accumulator is negative. Next, the digital/analog converter 36 is responsible for converting the digital reference voltage into an analog reference voltage and providing the analog reference voltage to the second input terminal of the active filter 33 .

Different from the traditional second-type phase-locked loop, before the loop 30 is locked, the digital charging path composed of the second phase detector 31B and the digital/analog converter 36 can be designed to be directly based on the positive and negative phase difference. and size provide a specific amount of charge. Fig. 4 shows a voltage locked state example comparing the present embodiment and the prior art; the horizontal axis in the figure is time, and the vertical axis is the voltage value of the output terminal of the active filter 33 (that is, provided to the voltage controlled oscillator 34 control voltage). It can be seen from Fig. 4 that if the traditional architecture as shown in Fig. 2 is adopted, the voltage will be damped for a period of time before becoming stable. In contrast, if the architecture according to the present invention is adopted, the analog reference voltage provided by the digital/analog converter 36 can quickly approach a certain stable value, so that the voltage at the output terminal of the active filter 33 can be quickly stabilized.

For example, as indicated in section O-A of FIG. 4, the second phase detector 31B can fix the input of the accumulator to a predetermined larger unit value, so that the voltage at the output terminal of the active filter 33 is rapidly pulled Lift. Then, as in the section A-B marked in Figure 4, when a certain set time passes, the second phase detector 31B can change the input of the accumulator to another preset medium unit value, so that the active filter 33 The rising slope of the voltage at the output terminal slows down and gradually approaches the locked state. As shown in FIG. 4 , if the architecture according to the present embodiment is adopted, the phase-locked loop can enter the locked state faster than the prior art. In other words, by properly controlling the reference voltage provided to the active filter 33 , the method according to the present invention can avoid damping and effectively shorten the time required for the loop 30 to enter the locked state. In practice, it is not limited to that shown in Figure 4, the initial value of the output of the above-mentioned accumulator can be settable, for example, it is set to one-half of the power supply voltage VDD of the phase-locked loop or any preset value selected by design . If the voltage at the output terminal of the active filter 33 is stabilized from VDD/2 to the target voltage, the locking speed is faster because the required voltage difference changes are less.

Please refer to FIG. 5 , which is a block diagram according to a second specific embodiment of the present invention. Compared with that shown in FIG. 3 , the circuit 30 in this embodiment further includes a capacitor C _P , a switch 37 and a switching module 38 for replacing the above-mentioned accumulator. The capacitor C _P is coupled to the second input terminal of the active filter 33 , and the switch 37 is coupled between the second input terminal and the digital/analog converter 36 . When the PLL 30 will enter the tracking mode from the acquisition mode, the switching module 38 will control the switch 37 to cut off the connection between the digital/analog converter 36 and the second input terminal.

When the switch 37 is in the state that the digital/analog converter 36 is connected to the second input terminal, the mode of operation of this phase-locked loop is substantially the same as that shown in FIG. 3 , and is also equivalent to the second type lock shown in FIG. 2 phase loop. When the switch 37 is controlled to cut off the connection between the digital/analog converter 36 and the second input terminal, it means that the charge stored in the capacitor C _P continues to supply the reference voltage required by the active filter 33 . After the connection is cut off, the operation mode of this loop is equivalent to the first type of phase-locked loop.

The advantages of the phase-locked loop shown in Figure 5 are: (1) Compared with the traditional first-type phase-locked loop, the acquisition mode of this architecture mainly uses the digital charging path to provide the reference voltage required by the filter, so it can Avoid shock absorption and effectively shorten the time required for the loop 30 to enter the locked state; (2) change the mode operation of the first-type phase-locked loop after entering the tracking mode, that is, it is not necessary to use a very fine digital/analog converter with the smallest bit 36, the effect of precisely locking the control voltage of the voltage-controlled oscillator 34 can also be achieved.

A third embodiment according to the present invention is a phase-locked loop including a correction function. Please refer to Figure 6(A). In addition to the elements shown in FIG. 3 , the PLL in this embodiment further includes a voltage detector 39 , a control module 40 and a calibration module 41 . In this embodiment, the charge pump 32 is designed to selectively provide a preset current I _norm or a test current I _test , and the frequency divider 35 is designed to selectively provide a preset divider. The frequency N _norm or a specific test frequency division N _test . For example, the preset current amount I _norm and the preset frequency division amount N _norm may be the current amount and the frequency division amount used by the phase-locked loop in a normal operation state, but not limited thereto.

In the case of providing a preset current amount I _norm and a preset frequency division amount N _norm , the loop gain G _loop of the phase-locked loop can be expressed as follows:

$G_{\mathrm{the\; loop}}=\frac{I_{\mathrm{the\; norm}}\×R\×K_{\mathrm{VCO}}}{N_{\mathrm{the\; norm}}},$ ... (Formula 1)

Where R represents the resistance value in the active filter 33 , and K _VCO represents the voltage-frequency conversion coefficient of the voltage-controlled oscillator 34 . The two values of R and K _VCO usually fluctuate with environmental factors such as manufacturing process, temperature, and voltage, and have a considerable degree of drift, resulting in many characteristics (such as bandwidth) of the phase-locked loop in actual operation that are different from the original design. default value. The goal of the calibration function provided in this embodiment is to find out the drift of the loop gain G _loop , and accordingly correct the phase-locked loop or other peripheral circuits that cooperate with the phase-locked loop.

First, the control module 40 enables the charge pump 32 to provide a preset current I _norm and the frequency divider 35 to provide a preset frequency division N _norm . After the PLL is locked, the voltage detector 39 measures a voltage related to the output frequency of the oscillating signal to generate a first reference voltage V ₁ . In this embodiment, what the voltage detector 39 measures is the digital reference voltage provided by the second phase detector 31B. In practice, the measurement object of the voltage detector 39 can also be the analog reference voltage output by the digital/analog converter 36 , or the control voltage provided by the active filter 33 to the voltage-controlled oscillator 34 . Compared with measuring analog voltage, measuring digital voltage has the advantage of being simple and fast.

Next, the control module 40 changes the charge pump 32 to provide the test current I _test and the frequency divider 35 to continue to provide the preset frequency division value N _norm . After the PLL tends to lock, the voltage detector 39 measures the digital reference voltage again to generate a second reference voltage value V ₂ . Since the test current I _test is different from the preset current I _norm , the second reference voltage V ₂ will also be different from the previously measured first reference voltage V ₁ , resulting in an oscillating signal output by the voltage-controlled oscillator 34 frequency is changed. Compared with the frequency of the oscillating signal when the digital reference voltage is the first reference voltage value V ₁ , the frequency variation Δf ₁ caused by this condition can be expressed as follows:

Δf ₁ ＝ΔV ₁ ×K _VCO ＝ΔI×R×K _VCO , ...... (Formula 2)

ΔI represents the difference between the preset current I _norm and the test current I _test , and ΔV ₁ represents the difference between the first reference voltage V ₁ and the second reference voltage V ₂ .

Next, the control module 40 changes the charging pump 32 to provide the preset current I _norm and the frequency divider 35 to provide the test frequency division N _test . After the phase-locked loop tends to lock, the voltage detector 39 measures the digital reference voltage again to generate a third reference voltage value V ₃ . Since the test frequency division amount N _test is different from the preset frequency division amount N _norm , the third reference voltage value V ₃ will also be different from the previously measured first reference voltage value V ₁ , resulting in the output of the voltage controlled oscillator 34 The frequency of the oscillating signal is changed. Compared with the frequency of the oscillating signal when the digital reference voltage is equal to the first reference voltage value V ₁ , the frequency variation Δf ₂ caused by this condition can be expressed as follows:

Δf ₂ ＝ΔV ₂ ×K _VCO ＝ΔN×F _ref , ... (Formula 3)

Wherein ΔN represents the difference between the test frequency division amount N _test and the preset frequency division amount N _norm , ΔV ₂ represents the difference between the first reference voltage value V ₁ and the third reference voltage value V ₃ , F _ref represents a reference frequency (also That is, the frequency of the reference signal input to this phase-locked loop).

Divide formula 2 and formula 3 to get:

$\frac{\mathrm{\Δ}{f}_1}{\mathrm{\Δ}{f}_2}=\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}=\frac{\mathrm{\ΔI}\×R\×K_{\mathrm{VCO}}}{\mathrm{\ΔN}\×f_{\mathrm{ref}}}.$ ... (Formula 4)

It can be deduced from formula 4:

$R\×K_{\mathrm{VCO}}=\frac{\mathrm{\ΔN}}{\mathrm{\ΔI}}\×\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}\×f_{\mathrm{ref}}.$ ... (Formula 5)

Combining Equation 5 and Equation 1, the loop gain G _loop of the phase-locked loop can be expressed as:

$G_{\mathrm{the\; loop}}=\frac{I_{\mathrm{the\; norm}}}{N_{\mathrm{the\; norm}}}\×R\×K_{\mathrm{VCO}}=\frac{I_{\mathrm{the\; norm}}}{N_{\mathrm{the\; norm}}}\×\frac{\mathrm{\ΔN}}{\mathrm{\ΔI}}\×\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}\×f_{\mathrm{ref}}.$ ... (Formula 6)

It can be seen from Equation 6 that even if the drift of the two values of R and K _VCO is unknown, according to the preset current I _norm , the preset frequency division N _norm , the test current I _test , and the test frequency division N _trst , the first reference voltage value V ₁ , the second reference voltage value V ₂ , the third reference voltage value V ₃ and the reference frequency F _ref , the control module 40 can still estimate the loop gain G _loop of the PLL. Furthermore, the control module 40 can find out the difference between the current loop gain G _loop and the loop gain G _loop expected to be achieved by the original design (that is, when R and K _VCO do not drift).

The calibration module 41 is used for calibrating the PLL according to the loop gain G _loop estimated by the control module 40 . In this embodiment, the calibration module 41 calibrates the VCO 34 according to the difference between the loop gain G _loop and the ideal value. In practical applications, the calibration module 41 can also use the filter element (such as the resistor R or the capacitor C) in the active filter 33 as a calibration target.

Please refer to FIG. 6(B). FIG. 6(B) is a block diagram of a phase-locked loop according to a fourth embodiment of the present invention. The main difference between this embodiment and the previous embodiment is that a sigma-delta modulator (sigma-delta (∑Δ) modulator) 42 is connected between the control module 40 and the frequency divider 35 of this embodiment to modulate the test signal frequency, so that the effect of making the frequency division difference ΔN non-integer can be achieved. In addition, when the PLL is used in a digitally modulated transmitter, the calibration object of the calibration module 41 can be a pre-emphasis circuit 43 therein. The function of the pre-emphasis circuit 43 is to provide a high-pass filter effect to compensate the attenuation of the modulated signal caused by the low-pass filter characteristic of the PLL.

In practice, the design of the pre-emphasis circuit 43 is related to the loop gain G _loop . Therefore, when the loop gain G _loop drifts, the parameters in the pre-emphasis circuit 43 may need to be adjusted accordingly. The correction module 41 in this embodiment is to correct the pre-emphasis circuit 43 according to the loop gain G _loop estimated by the control module 40 . The above examples are used to illustrate that the loop gain G _loop estimated by the control module 40 can also be used to calibrate peripheral circuits matching the PLL, rather than being limited to the main functional blocks of the PLL itself.

It should be noted that the above calibration method can be applied to various circuits including charge pumps and frequency dividers, not limited to those shown in FIG. 6(A) or FIG. 6(B).

The fifth embodiment of the present invention is a calibration method with a phase-locked loop; the phase-locked loop includes a charge pump and a frequency divider. The calibration method includes the steps shown in FIG. 7 . Firstly, step S71 is to provide a preset current I _norm to the charge pump and a preset frequency division N _norm to the frequency divider. Next, step S72 is to measure a voltage related to an output frequency of the phase-locked loop to generate a first reference voltage value V ₁ after the loop is locked. Step S73 is to provide a test current I _test to the charge pump and provide the preset frequency division N _norm to the frequency divider. Step S74 is to measure the voltage again after the loop is locked, so as to generate a second reference voltage V ₂ .

Next, in step S75 , the charge pump provides the preset current I _norm , and the frequency divider provides a specific test frequency division N _test . Step S76 is to measure the voltage again after the loop is locked, so as to generate the third reference voltage V ₃ . Step S77 is based on the preset current I _norm , the preset frequency division N _norm , the test current I _test , the test frequency division N _test , the first reference voltage V ₁ , the second reference voltage V ₂ , the third The loop gain G _loop of the PLL is estimated with reference voltage V ₃ and a reference frequency F _ref . Step S78 is to calibrate the PLL according to the loop gain G _loop .

The detailed method of estimating the loop gain G _loop and calibrating the phase-locked loop in this embodiment is the same as that of the previous embodiment, so details are not repeated here. It should be noted that the order of steps S73 to S74 and steps S75 to S76 may be interchanged. This correction method can be applied to PLLs with various architectures, not limited to those shown in FIG. 6(A) or FIG. 6(B).

As mentioned above, the phase-locked loop proposed by the present invention replaces the analog charging path composed of charge pump and capacitor in the prior art with a digital charging path. The digital charging path according to the present invention can be designed to provide a specific charging amount directly according to the positive and negative phase difference, thereby stably pulling up the reference voltage provided to the active filter, thereby avoiding shock absorption and effectively locking the phase-locked loop The time required for the state. Compared with the prior art, the phase-locked loop according to the invention has the advantages of fast locking speed and low surge energy.

Through the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention.

Claims (12)

1. A calibration method that cooperates with a phase-locked loop, the phase-locked loop includes a charge pump and a frequency divider, and the calibration method comprises the following steps: After the charge pump provides a predetermined amount of current and the frequency divider provides a predetermined frequency division amount, measuring a voltage related to an output frequency of the phase-locked loop to generate a first reference voltage value; After the charge pump provides a test current and the frequency divider provides the preset frequency division value, the voltage is measured to generate a second reference voltage value; After the charge pump provides the preset current and the frequency divider provides a test frequency division, measure the voltage to generate a third reference voltage value, wherein the test frequency division is a specific value; According to the preset current amount, the preset frequency division amount, the test current amount, the test frequency division amount, the first reference voltage value, the second reference voltage value, the third reference voltage value and a reference frequency, Estimate the primary loop gain of the phase-locked loop; and The phase locked loop is calibrated according to the loop gain. 2. correction method as claimed in claim 1, is characterized in that, this loop gain G _loop is: ${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; loop</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; norm</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; norm</span>}}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;N</span>}}{\mathrm{<span\; class="notranslate">\; \&Delta;I</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; ,</span>$ Among them, I _norm represents the preset current amount, N _norm represents the preset frequency division amount, ΔI represents the difference between the preset current amount and the test current amount, and ΔN represents the difference between the test frequency division amount and the preset frequency division amount ΔV ₁ represents the difference between the first reference voltage value and the second reference voltage value, ΔV ₂ represents the difference between the first reference voltage value and the third reference voltage value, and F _ref represents the reference frequency. 3. The calibration method according to claim 1, wherein the phase-locked loop also includes an active filter, a phase detector and a digital/analog converter, and the phase detector is used to A phase difference of a feedback signal generates a digital reference voltage, the digital/analog converter is used to convert the digital reference voltage into an analog reference voltage for the active filter reference, and the measured voltage is the digital reference voltage. 4. The calibration method according to claim 1, wherein the phase-locked loop also includes a filter element and a voltage-controlled oscillator, and the calibration step calibrates the filter element or the voltage-controlled oscillator according to the loop gain . 5. The calibration method according to claim 1, wherein the PLL also includes a pre-emphasis circuit, and the calibration step is to calibrate the pre-emphasis circuit according to the loop gain. 6. The calibration method according to claim 1, wherein the test frequency division value is subjected to a delta-sigma modulation. 7. A phase-locked loop with correction function, comprising: A charge pump, used to provide a preset current or a test current; A frequency divider for providing a preset frequency division or a test frequency division, wherein the test frequency division is a specific value; a voltage detector, when the charge pump provides the preset current amount and the frequency divider provides the preset frequency division amount, the voltage detector measures a voltage related to an output frequency of the phase-locked loop to generate The first reference voltage value; when the charge pump provides the test current and the frequency divider provides the preset frequency division value, the voltage detector measures the voltage to generate a second reference voltage value; when the charge pump providing the preset current amount and the frequency divider providing the test frequency division amount, the voltage detector measures the voltage to generate a third reference voltage value; A control module, used for according to the preset current amount, the preset frequency division amount, the test current amount, the test frequency division amount, the first reference voltage value, the second reference voltage value, and the third reference voltage value and a reference frequency, estimate a loop gain of the phase-locked loop; and A correction module is used for correcting the PLL according to the loop gain. 8. phase-locked loop as claimed in claim 7, is characterized in that, this loop gain G _loop is: ${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; loop</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; norm</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; the\; norm</span>}}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;N</span>}}{\mathrm{<span\; class="notranslate">\; \&Delta;I</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; ,</span>$ Among them, I _norm represents the preset current amount, N _norm represents the preset frequency division amount, ΔI represents the difference between the preset current amount and the test current amount, and ΔN represents the difference between the test frequency division amount and the preset frequency division amount ΔV ₁ represents the difference between the first reference voltage value and the second reference voltage value, ΔV ₂ represents the difference between the first reference voltage value and the third reference voltage value, and F _ref represents the reference frequency. 9. The phase-locked loop as claimed in claim 7, further comprising: an active filter; a phase detector for generating a digital reference voltage according to a phase difference between a reference signal and a feedback signal; and A digital/analog converter is used to convert the digital reference voltage into an analog reference voltage for the active filter, and the voltage measured by the voltage detector is the digital reference voltage. 10. The phase-locked loop of claim 7, comprising a filter element and a voltage-controlled oscillator, and the calibration module calibrates the filter element or the voltage-controlled oscillator according to the loop gain. 11. The PLL of claim 7, further comprising a pre-emphasis circuit, and the calibration module calibrates the pre-emphasis circuit according to the loop gain. 12. The phase-locked loop as claimed in claim 7, comprising a sigma-delta modulator for modulating the test frequency division value.

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