CN102468848A - Phase-locked loop with correcting function and correcting method thereof - Google Patents

Abstract

The invention provides a phase-locked loop, comprising a charging pump, a frequency demultiplier, a voltage detector, a control module and a correction module. The voltage detector measures voltage which is related to an output frequency of the phase-locked loop to generate first reference voltage when a preset current magnitude and a preset frequency-division magnitude are adopted; the voltage detector measures the voltage to generate second reference voltage when a test current magnitude and the preset frequency-division amount are adopted; the voltage detector measures the voltage to generate third reference voltage when the preset current magnitude and the frequency-division magnitudes except for a test frequency-division magnitude are adopted. The control module estimates loop gain of the phase-locked loop according to these current magnitudes, the frequency-division magnitude and the reference voltage, and the correction module corrects the phase-locked loop according to the loop gain.

Description

Phase-locked loop and bearing calibration thereof with calibration function

Technical field

The present invention is relevant with the phase-locked loop, and especially the bearing calibration with the phase-locked loop is relevant.

Background technology

In computer system and communication system now, can provide the phase-locked loop of oscillator signal to play the part of indispensable key player with accurate frequency.With the wireless communication system is example, and the oscillator signal that its transmission end utilizes the phase-locked loop usually and produced is for sending the reference data of signal, and characteristics such as the lock speed of phase-locked loop, loop frequency range and surging (spur) energy all can directly influence the quality of wireless signal.

Shown in Figure 1 is the Organization Chart of first type (type-I) phase-locked loop.Filter 13, voltage controlled oscillator 14 and frequency divider 15 that this loop 10 comprises phase detectors 11, charge pumping 12, is made up of resistance R and capacitor C.Because resistance R forms a leakage path between the input of voltage controlled oscillator 14 and earth terminal; No matter whether loop 10 is in the lock state; Phase detectors 11 still must be exported recurrent pulses; Make the input charging of charge pumping 12, with the electric charge of compensation via the resistance R loss for voltage controlled oscillator 14.When stablized the phase-locked loop, charge and discharge reached balance, and the cycle of above-mentioned pulse equals the cycle of reference signal.The existence of these recurrent pulses can form the oscillator signal of voltage controlled oscillator 14 outputs and disturb.The phase difference of reference signal and feedback signal is bigger, and this pulse is wideer, and its energy is higher.Frequency with oscillator signal is 3.66GHz, is example and the frequency of reference signal is the situation of 26MHz.In the frequency spectrum of the output signal of voltage controlled oscillator 14, except the principal component that appears at 3.66GHz, also so-called surging can appear at 3.66GHz ± 26MHz two places.Many wireless communication standards all can be made standard to the upper limit of surging energy.The shortcoming of the first type phase-locked loop is that this charging pulse can cause too high surging energy usually.

Shown in Figure 2 is the Organization Chart of second type (type-II) phase-locked loop.Active filter 23, voltage controlled oscillator 24 and frequency divider 25 that this loop 20 comprises phase detectors 21, two charge pumping 22A and 22B, is made up of resistance R, capacitor C 1/C2/C3, operational amplifier 23A.Got in the process of lock-out state by unlocked state in loop 20, the second charge pumping 22B is responsible for according to the measured phase difference of phase detectors 21 1 charge/discharge of the capacitor C in the active filter 23, the reference voltage V that in figure, is indicated _REFProgressively promoted/be pulled low to the deserved control voltage of voltage controlled oscillator 24 inputs when equaling loop 20 lockings.Before locking, V _REFUsually also can just tend towards stability with this control voltage through damping (damping) after a while.Though this framework does not have the too high problem of the first type phase-locked loop surging energy, the second charge pumping 22B is to the lock speed of the direct limit circuit 20 of speed meeting of capacitor C 1 charge/discharge.In addition, this damping phenomenon also can cause the loop to be extended for 20 required locking times.

No matter be the phase-locked loop of above any framework; Parameter wherein all maybe be along with the change of environmental factors such as processing procedure, temperature, voltage; The drift of certain degree is arranged, hope the preset value that reaches when the numerous characteristics when causing the phase-locked loop actual operation (for example frequency range) is different from former the design.

Summary of the invention

For addressing the above problem, the present invention proposes the bearing calibration of a kind of phase-locked loop, by the measuring current amount being provided and testing the frequency division amount and observe the change in voltage in the loop, finds out the margin of error of loop gain.

A specific embodiment according to the present invention is a kind of bearing calibration that cooperates the phase-locked loop.The step that this method is at first carried out is: one predetermined current amount is provided and after the frequency divider of phase-locked loop provides a preset frequency division amount in the charge pumping of phase-locked loop; Measure a voltage relevant, to produce first reference voltage level with an output frequency of this phase-locked loop.Then, this method is carried out a testing procedure: after this charge pumping provides a measuring current amount, measure this voltage, to produce second reference voltage level.Then, this method is carried out another testing procedure: after this frequency divider provides a test frequency division amount, measure this voltage, to produce the 3rd reference voltage level, wherein this test frequency division amount is a particular value.Based on this predetermined current amount, this preset frequency division amount, this measuring current amount, this test frequency division amount, this first reference voltage level, this second reference voltage level, the 3rd reference voltage level and a reference frequency; Can estimate the loop gain (loop gain) of this phase-locked loop, and proofread and correct this phase-locked loop based on this loop gain.

Can be widely used in the phase-locked loop of various different frameworks according to bearing calibration of the present invention.Can further be understood by following detailed Description Of The Invention and accompanying drawing about advantage of the present invention and spirit.

Description of drawings

Shown in Figure 1 is the Organization Chart of traditional first type phase-locked loop.

Shown in Figure 2 is the Organization Chart of traditional second type phase-locked loop.

Fig. 3 is according to the phase-locked loop calcspar in first specific embodiment of the present invention.

Fig. 4 is for comparing a voltage lock-out state example of present embodiment and prior art.

Fig. 5 is according to the phase-locked loop calcspar in second specific embodiment of the present invention.

Fig. 6 (A) is according to the phase-locked loop calcspar in the 3rd specific embodiment of the present invention.

Fig. 6 (B) is according to the phase-locked loop calcspar in the 4th specific embodiment of the present invention.

Fig. 7 is according to the phase-locked loop bearing calibration flow chart in the 5th specific embodiment of the present invention.

The main element symbol description

10,20: phase-locked loop 11,21: phase detectors

12: charge pumping 13: filter

14,24: voltage controlled oscillator 15,25: frequency divider

22A: the first charge pumping 22B: second charge pumping

23: active filter 23A: operational amplifier

30: phase-locked loop 31A: first phase detectors

31B: second phase detectors 32: charge pumping

33: active filter 33A: operational amplifier

34: voltage controlled oscillator 35: frequency divider

36: digital/analog converter 37: switch

38: handover module 39: voltage detector

40: control module 41: correction module

42: integral triangle modulator 43: accentuator in advance

S71～S78: process step

Embodiment

According to first specific embodiment of the present invention is the phase-locked loop that Fig. 3 illustrated.Active filter that this loop 30 comprises two phase place detector 31A and 31B, a charge pumping 32, be made up of resistance R, capacitor C, operational amplifier 33A 33, a voltage controlled oscillator 34, a frequency divider 35 and a digital/analog converter 36.

As shown in Figure 3, active filter 33 comprises the first input end that is connected to charge pumping 32, second input that is connected to digital/analog converter 36, and in order to the output of a control signal to be provided.Capacitor C and resistance R coupled in parallel are between this first input end and this output.The function of voltage controlled oscillator 34 is to produce an oscillator signal according to this control signal.35 of frequency dividers are to be responsible for this oscillation signal frequency dividing, to produce a feedback signal.According to reference signal and this feedback signal of input circuit 30, the first phase detectors 31A produces a phase difference signal.Charge pumping 32 can provide the first input end of a charging current to active filter 33 according to this phase difference signal.

The second phase detectors 31B is used for phase difference positive and negative of reference signal detection and feedback signal, and its output signal is a digital reference voltage.For example, this digital reference voltage can be the binary system formula signal of eight bits; This voltage can be the multisection type digital units value that size is had nothing in common with each other to be sent into a digital accumulator (not being illustrated among the figure) produce.Above-mentioned phase difference positive and negative will determine input signal positive and negative of accumulator, and the pace of change of accumulator output valve depends on the size of the input signal of accumulator.For example, when the phase place of the phase-lead feedback signal of reference signal, the input signal of this accumulator is for just.Relatively, when the phase place of the phase lag feedback signal of reference signal, the input signal of this accumulator is for negative.Then, it is an analog reference voltage that digital/analog converter 36 is responsible for this digital reference voltage transitions, and with this analog reference voltage second input to active filter 33 is provided.

Different with traditional second type phase-locked loop is; In loop 30 still before the non-locking, the digital charge path of being made up of the second phase detectors 31B and digital/analog converter 36 can be designed to directly according to the positive and negative of phase difference and big or small specific charge volume is provided.Shown in Figure 4 for comparing a voltage lock-out state example of present embodiment and prior art; Transverse axis among the figure is the time, and the longitudinal axis then is the magnitude of voltage control voltage of voltage controlled oscillator 34 (that is offer) of the output of active filter 33.Can find out that by Fig. 4 if adopt the conventional architectures like Fig. 2, the damping of a period of time can appear in this voltage before tending towards stability.Relatively, if adopt according to framework of the present invention, the analog reference voltage that digital/analog converter 36 is provided can be approached certain stationary value fast, makes the voltage of the output of active filter 33 stablize fast by this.

For example, like the section O-A that indicates among Fig. 4, the second phase detectors 31B can be fixed as the input of accumulator one and preset than the big unit value, makes the voltage of the output of active filter 33 drawn high apace.Then; Like the section A-B that indicates among Fig. 4, when certain time that configures of process, the second phase detectors 31B can change the input of this accumulator into another preset intermediate cells value; Make the voltage rate of rise of the output of active filter 33 slow down, and convergence lock-out state gradually.As shown in Figure 4, if adopt according to the framework in the present embodiment, the phase-locked loop can more get into lock-out state than prior art soon.In other words, by suitably controlling the reference voltage that offers active filter 33, can avoid damping and effectively shorten loop 30 getting into the required time of lock-out state according to way of the present invention.Be not limited to shown in Figure 4ly on the practice, the output initial value of above-mentioned accumulator can be the formula of can setting, and for example is set to 1/2nd or any preset value of ordering through the design choosing of the supply voltage VDD of phase-locked loop.If the voltage of output that makes active filter 33 is by the stable target voltage that reaches of VDD/2, pressure reduction that must variation because of institute tails off, and lock speed is faster.

See also Fig. 5, Fig. 5 is the calcspar according to second specific embodiment of the present invention.Compared to shown in Figure 3, the loop 30 in the present embodiment further comprises in order to replace the capacitor C of above-mentioned accumulator _P, switch 37 and handover module 38.Capacitor C _PBe coupled to this second input of active filter 33,37 on switch is to be coupled to 36 of this second input and digital/analog converters.To follow the trail of (tracking) pattern by the entering of acquisition (acquisition) pattern when phase-locked loop 30, handover module 38 meeting control switchs 37 are to block the binding between digital/analog converter 36 and this second input.

Be at switch 37 and make under digital/analog converter 36 and the situation that this second input links to each other, the function mode of this phase-locked loop and shown in Figure 3 roughly the same also is equivalent to the second type phase-locked loop shown in Figure 2.When switch 37 is controlled as the binding of blocking between digital/analog converter 36 and this second input, be equivalent to by capacitor C _PStored electric charge continues the required reference voltage of supply active filter 33.After this binding was blocked, the operating mode in this loop promptly was equivalent to the first type phase-locked loop.

The advantage of phase-locked loop shown in Figure 5 is: (1) is compared to the first traditional type phase-locked loop; The acquisition pattern of this framework mainly provides filter required reference voltage by digital charge path, therefore can avoid damping and effectively shorten loop 30 getting into the required time of lock-out state; (2) change mode operating after will getting into the tracking pattern, promptly needn't adopt the very meticulous digital/analog converter 36 of minimum bit, also can reach the accurate effect of locking of control voltage that makes voltage controlled oscillator 34 with the first type phase-locked loop.

The 3rd specific embodiment according to the present invention is the phase-locked loop that comprises calibration function.See also Fig. 6 (A).Except the element that Fig. 3 has illustrated, the phase-locked loop in the present embodiment further comprises a voltage detector 39, a control module 40 and a correction module 41.In this embodiment, charge pumping 32 is designed to optionally provide a predetermined current amount I _NormAn or measuring current amount I _Test, 35 of frequency dividers are designed to optionally provide a preset frequency division amount N _NormAn or specific test frequency division amount N _TestFor example, predetermined current amount I _NormWith preset frequency division amount N _NormCan be the magnitude of current and the frequency division amount that this phase-locked loop is adopted under the normal operation state, but not as limit.

Predetermined current amount I is being provided _NormWith preset frequency division amount N _NormSituation under, the loop gain G of this phase-locked loop _LoopCan represent as follows:

$G_{\mathrm{Loop}}=\frac{I_{\mathrm{Norm}}\×R\×K_{\mathrm{VCO}}}{N_{\mathrm{Norm}}},$ (formula one)

Wherein R represents the resistance value in the active filter 33, K _VCORepresent the voltage-frequency conversion coefficient of voltage controlled oscillator 34.R and K _VCOThese two numerical value all can have the drift of certain degree along with environmental factors such as processing procedure, temperature, voltage changes usually, hope the preset value that reaches when the numerous characteristics when causing the phase-locked loop actual operation (for example frequency range) is different from former the design.The target of the calibration function that present embodiment provided is for finding out loop gain G _LoopDrift value, and revise the peripheral circuit that this phase-locked loop or other cooperate these phase-locked loops in view of the above.

At first, control module 40 makes charge pumping 32 that predetermined current amount I is provided _NormAnd make frequency divider 35 that preset frequency division amount N is provided _NormAfter this phase-locked loop locking, voltage detector 39 is promptly measured a voltage relevant with the output frequency of this oscillator signal, to produce the first reference voltage level V ₁In this embodiment, voltage detector 39 measured persons are this digital reference voltage that the second phase detectors 31B is provided.On the practice, the measuring object of voltage detector 39 also can be the analog reference voltage of digital/analog converter 36 outputs, or active filter 33 offers the control voltage of voltage controlled oscillator 34.Compared to measure analog voltage, measure digital voltage and have simple and rapid benefit.

Then, control module 40 changes and makes charge pumping 32 that measuring current amount I is provided _TestAnd make frequency divider 35 continue to provide preset frequency division amount N _NormAfter the phase-locked loop was tending towards locking, voltage detector 39 was measured this digital reference voltage once more, to produce the second reference voltage level V ₂Because measuring current amount I _TestBe different from predetermined current amount I _Norm, the second reference voltage level V ₂Also can be different from the previous first measured reference voltage level V ₁, and cause the frequency of the oscillator signal of voltage controlled oscillator 34 outputs to be changed.Compared to this digital reference voltage is the first reference voltage level V ₁The time this oscillator signal frequency, the frequency variation Δ f that this condition causes ₁Can represent as follows:

Δ f ₁=Δ V ₁* K _VCO=Δ I * R * K _VCO... (formula two)

Wherein Δ I represents predetermined current amount I _NormWith measuring current amount I _TestDifference, Δ V ₁Represent the first reference voltage level V ₁With the second reference voltage level V ₂Difference.

Next, control module 40 changes and makes charge pumping 32 that predetermined current amount I is provided _NormAnd make frequency divider 35 that test frequency division amount N is provided _TestAfter the phase-locked loop was tending towards locking, voltage detector 39 was measured this digital reference voltage once more, to produce the 3rd reference voltage level V ₃Because test frequency division amount N _TestBe different from preset frequency division amount N _Norm, the 3rd reference voltage level V ₃Also can be different from the previous first measured reference voltage level V ₁, and cause the frequency of the oscillator signal of voltage controlled oscillator 34 outputs to be changed.Equal the first reference voltage level V compared to this digital reference voltage ₁The time this oscillator signal frequency, the frequency variation Δ f that this condition causes ₂Can represent as follows:

Δ f ₂=Δ V ₂* K _VCO=Δ N * F _Ref... (formula three)

Wherein frequency division amount N is tested in Δ N representative _TestWith preset frequency division amount N _NormDifference, Δ V ₂Represent the first reference voltage level V ₁With the 3rd reference voltage level V ₃Difference, F _RefThen represent the reference frequency frequency of the reference signal of this phase-locked loop (that is import).

Formula two and formula three are divided by, can obtain:

$\frac{\mathrm{\Δ}{f}_1}{\mathrm{\Δ}{f}_2}=\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}=\frac{\mathrm{\Δ\; I}\×R\×K_{\mathrm{VCO}}}{\mathrm{\Δ\; N}\×F_{\mathrm{Ref}}}.$ (formula four)

Can push away by formula four:

$R\×K_{\mathrm{VCO}}=\frac{\mathrm{\Δ\; N}}{\mathrm{\Δ\; I}}\×\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}\×F_{\mathrm{Ref}}.$ (formula five)

Convolution five and formula one, the loop gain G of phase-locked loop _LoopCan be represented as:

$G_{\mathrm{Loop}}=\frac{I_{\mathrm{Norm}}}{N_{\mathrm{Norm}}}\×R\×K_{\mathrm{VCO}}=\frac{I_{\mathrm{Norm}}}{N_{\mathrm{Norm}}}\×\frac{\mathrm{\Δ\; N}}{\mathrm{\Δ\; I}}\×\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}\×F_{\mathrm{Ref}}.$ (formula six)

Can find out by formula six, even R and K _VCOThe drift value of these two numerical value is a unknown number, according to predetermined current amount I _Norm, preset frequency division amount N _Norm, measuring current amount I _Test, test frequency division amount N _Trst, the first reference voltage level V ₁, the second reference voltage level V ₂, the 3rd reference voltage level V ₃And reference frequency F _Ref, control module 40 still can be estimated the loop gain G of this phase-locked loop _LoopFurther, control module 40 can be found out existing loop gain G _LoopHope to reach with former design (that is at R and K _VCOTake place under the situation of drift) loop gain G _LoopDifference.

The loop gain G of correction module 41 in order to be estimated according to control module 40 _LoopProofread and correct this phase-locked loop.In this embodiment, correction module 41 is according to above-mentioned loop gain G _LoopDifference correction voltage controlled oscillator 34 with ideal value.In practical application, the filter element (for example resistance R or capacitor C) of correction module 41 in can also active filter 33 is correcting mark.

See also Fig. 6 (B), Fig. 6 (B) is according to the phase-locked loop calcspar in the 4th specific embodiment of the present invention.The main difference of this embodiment and previous embodiment is; 35 of the control module 40 of present embodiment and frequency dividers are connected with an integral triangle modulator (sigma-delta (∑ Δ) modulator) 42; Should test frequency division amount in order to modulation, can reach by this that to make frequency division amount discrepancy delta N be non-integral effect.In addition, when this phase-locked loop is used for the digital modulation transmitter, the calibration object of correction module 41 can be accentuator in advance (pre-emphasis circuit) 43 wherein.The effect of accentuator 43 in advance is to provide a high-pass filtering effect, with low-frequency filter characteristics the decay that modulation signal is caused of compensation phase-locked loop.

On the practice, the design meeting of accentuator 43 and loop gain G in advance _LoopRelevant.Therefore, as loop gain G _LoopWhen drift took place, the parameter in the accentuator 43 also maybe be along with adjustment in advance.This loop gain G that correction module 41 in the present embodiment is promptly estimated according to control module 40 _LoopProofread and correct accentuator 43 in advance.The loop gain G that above example is estimated in order to explanation control module 40 _LoopAlso can be used for proofreading and correct the peripheral circuit that cooperates this phase-locked loop, but not be defined in the major function block of this phase-locked loop itself.

What must explain is that above-mentioned correcting mode can be applicable to the various circuit that comprise charge pumping and frequency divider, does not exceed with person shown in Fig. 6 (A) or Fig. 6 (B).

The 5th specific embodiment of the present invention is the bearing calibration of a kind of cooperation one phase-locked loop; This phase-locked loop comprises a charge pumping and a frequency divider.This bearing calibration comprises step as shown in Figure 7.At first, step S71 is for to provide a predetermined current amount I in this charge pumping _NormAnd one preset frequency division amount N is provided in this frequency divider _NormThen, step S72 measures a voltage relevant with an output frequency of this phase-locked loop, to produce the first reference voltage level V for after treating the loop locking ₁Step S73 provides a measuring current amount I for changing in this charge pumping _TestAnd this preset frequency division amount N is provided in this frequency divider _NormStep S74 measures this voltage, to produce the second reference voltage level V once more for after treating the loop locking ₂

Then, in step S75, this charge pumping provides this predetermined current amount I _Norm, and this frequency divider provides a specific test frequency division amount N _TestStep S76 after treating the loop locking, measures this voltage, to produce the 3rd reference voltage level V once more ₃Step S77 system is according to predetermined current amount I _Norm, preset frequency division amount N _Norm, measuring current amount I _Test, test frequency division amount N _Test, the first reference voltage level V ₁, the second reference voltage level V ₂, the 3rd reference voltage level V ₃An and reference frequency F _Ref, estimate the loop gain G of this phase-locked loop _LoopStep S78 then is according to loop gain G _LoopProofread and correct this phase-locked loop.

Estimate loop gain G in the present embodiment _LoopIdentical with the detailed method of proofreading and correct the phase-locked loop with previous embodiment, therefore repeat no more.What need explanation is that the order of step S73～step S74 and step S75～step S76 is interchangeable.This bearing calibration can be used in the phase-locked loop of various different frameworks, does not exceed with person shown in Fig. 6 (A) or Fig. 6 (B).

As stated, the phase-locked loop of the present invention's proposition replaces the analog charge path of being made up of charge pumping and electric capacity in the prior art with digital charge path.Digital charge path according to the present invention can be designed to directly according to the positive negative variance of phase place specific charge volume is provided; Stablize by this and draw high the reference voltage that offers active filter, and then avoid damping and effective phase-locked loop to get into the required time of lock-out state.Compared to prior art, phase-locked loop according to the present invention has the fast and low advantage of surging energy of lock speed.

By the detailed description of above preferred embodiment, hope can be known description characteristic of the present invention and spirit more, and is not to come category of the present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.

Claims (12)

1. bearing calibration that cooperates a phase-locked loop, this phase-locked loop comprises a charge pumping and a frequency divider, and this bearing calibration comprises the following step:

One predetermined current amount is provided and after this frequency divider provides a preset frequency division amount, measures a voltage relevant, in this charge pumping to produce first reference voltage level with an output frequency of this phase-locked loop;

One measuring current amount is provided and after this frequency divider provides this preset frequency division amount, measures this voltage, in this charge pumping to produce second reference voltage level;

This predetermined current amount is provided and after this frequency divider provides a test frequency division amount, measures this voltage in this charge pumping, to produce the 3rd reference voltage level, wherein this test frequency division amount is a particular value;

According to this predetermined current amount, this preset frequency division amount, this measuring current amount, this test frequency division amount, this first reference voltage level, this second reference voltage level, the 3rd reference voltage level and a reference frequency, estimate a loop gain of this phase-locked loop; And

Proofread and correct this phase-locked loop according to this loop gain.

2. bearing calibration as claimed in claim 1 is characterized in that, this loop gain G _LoopFor:

$G_{\mathrm{loop}}=\frac{I_{\mathrm{norm}}}{N_{\mathrm{norm}}}\×\frac{\mathrm{\ΔN}}{\mathrm{\ΔI}}\×\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}\×F_{\mathrm{ref}},$

I wherein _NormRepresent this predetermined current amount, N _NormExpression should be preset the frequency division amount, and Δ I representes the difference of this predetermined current amount and this measuring current amount, and Δ N representes this test frequency division amount and the difference of being somebody's turn to do preset frequency division amount, Δ V ₁The difference of representing this first reference voltage level and this second reference voltage level, Δ V ₂The difference of representing this first reference voltage level and the 3rd reference voltage level, F _RefRepresent this reference frequency.

3. bearing calibration as claimed in claim 1; It is characterized in that; This phase-locked loop also comprises an active filter, phase detectors and a digital/analog converter; These phase detectors produce a digital reference voltage in order to the phase difference according to a reference signal and a feedback signal, this digital/analog converter in order to this digital reference voltage transitions for supplying an analog reference voltage of this active filter reference, and this voltage of being measured is this digital reference voltage.

4. bearing calibration as claimed in claim 1 is characterized in that, this phase-locked loop also comprises a filter element and a voltage controlled oscillator, and this aligning step is proofreaied and correct this filter element or this voltage controlled oscillator according to this loop gain.

5. bearing calibration as claimed in claim 1 is characterized in that, this phase-locked loop also comprises an accentuator in advance, and this accentuator is in advance proofreaied and correct according to this loop gain by this aligning step system.

6. bearing calibration as claimed in claim 1 is characterized in that, this test frequency division amount is modulated through an integral triangle.

7. phase-locked loop with calibration function comprises:

One charge pumping is in order to provide a predetermined current amount or a measuring current amount;

One frequency divider, in order to a preset frequency division amount or a test frequency division amount to be provided, wherein this test frequency division amount is a particular value;

One voltage detector provides this preset frequency division amount when this charge pumping provides this predetermined current amount and this frequency divider, and this voltage detector is measured a voltage relevant with an output frequency of this phase-locked loop, to produce first reference voltage level; When this charge pumping provides this measuring current amount and this frequency divider this preset frequency division amount is provided, this voltage detector is measured this voltage, to produce second reference voltage level; When this charge pumping provides this predetermined current amount and this frequency divider this test frequency division amount is provided, this voltage detector is measured this voltage, to produce the 3rd reference voltage level;

One control module; In order to according to this predetermined current amount, this preset frequency division amount, this measuring current amount, this test frequency division amount, this first reference voltage level, this second reference voltage level, the 3rd reference voltage level and a reference frequency, estimate a loop gain of this phase-locked loop; And

One correction module is in order to proofread and correct this phase-locked loop according to this loop gain.

8. phase-locked loop as claimed in claim 7 is characterized in that, this loop gain G _LoopFor:

$G_{\mathrm{loop}}=\frac{I_{\mathrm{norm}}}{N_{\mathrm{norm}}}\×\frac{\mathrm{\ΔN}}{\mathrm{\ΔI}}\×\frac{\mathrm{\Δ}{V}_1}{\mathrm{\Δ}{V}_2}\×F_{\mathrm{ref}},$

I wherein _NormRepresent this predetermined current amount, N _NormExpression should be preset the frequency division amount, and Δ I representes the difference of this predetermined current amount and this measuring current amount, and Δ N representes this test frequency division amount and the difference of being somebody's turn to do preset frequency division amount, Δ V ₁The difference of representing this first reference voltage level and this second reference voltage level, Δ V ₂The difference of representing this first reference voltage level and the 3rd reference voltage level, F _RefRepresent this reference frequency.

9. phase-locked loop as claimed in claim 7 is characterized in that, also comprises:

One active filter;

One phase detectors produce a digital reference voltage in order to the phase difference according to a reference signal and a feedback signal; And

One digital/analog converter, in order to this digital reference voltage transitions for supplying an analog reference voltage of this active filter reference, and this measured voltage of this voltage detector is this digital reference voltage.

10. phase-locked loop as claimed in claim 7 is characterized in that, comprises a filter element and a voltage controlled oscillator, and this correction module is proofreaied and correct this filter element or this voltage controlled oscillator according to this loop gain.

11. phase-locked loop as claimed in claim 7 is characterized in that, also comprises an accentuator in advance, and this correction module is proofreaied and correct this accentuator in advance according to this loop gain.

12. phase-locked loop as claimed in claim 7 is characterized in that, comprises an integral triangle modulator, should test frequency division amount in order to modulation.

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